ADE7756 ,Single Phase Energy Metering IC with Serial Interfacefeatures, i.e., channel offset correction, phaseDigital Power, Phase and Input Offset Calibrationca ..
ADE7756ARS ,Single Phase Energy Metering IC with Serial Interfacefeatures, i.e., channel offset correction, phaseDigital Power, Phase and Input Offset Calibrationca ..
ADE7756ARS ,Single Phase Energy Metering IC with Serial InterfaceGENERAL DESCRIPTIONlated real power register is half-full and also when the registerThe ADE7756 is ..
ADE7756ARSZ ,Single Phase Energy Metering IC with Serial InterfaceCHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5 CHANNEL 2 ADC . . . . . . . . . . . . . ..
ADE7756ARSZRL ,Single Phase Energy Metering IC with Serial InterfaceFEATURESThe ADE7756 contains a sampled Waveform register and anHigh Accuracy, Supports IEC 687/1036 ..
ADE7757ARN ,Energy Metering IC with Integrated OscillatorSPECIFICATIONSParameter Value Units Test Conditions/Comments1, 2ACCURACY1Measurement Error on Chann ..
ADXL150AQC ,+-5 g to +-50 g, Low Noise, Low Power, Single/Dual Axis iMEMS AccelerometersSPECIFICATIONS V = +5.00 V, Acceleration = Zero g, unless otherwise noted)S ADXL150JQC/AQC ADX ..
ADXL150EM-1 ,±50g Single Axis Accelerometer with Analog OutputGENERAL DESCRIPTION 5kV+VSThe ADXL150 and ADXL250 are third generation ±50 g sur-CLOCK 2face microm ..
ADXL150EM-3 ,±50g Single Axis Accelerometer with Analog OutputFEATURESComplete Acceleration Measurement SystemTP(DO NOT CONNECT)on a Single Monolithic IC80 dB Dy ..
ADXL150JQC ,+-5 g to +-50 g, Low Noise, Low Power, Single/Dual Axis iMEMS AccelerometersGENERAL DESCRIPTION 5kV+VSThe ADXL150 and ADXL250 are third generation ±50 g sur-CLOCK 2face microm ..
ADXL180WCPZ-RL1 , Configurable, High g, iMEMS Accelerometer
ADXL190EM-1 ,±100g Single Axis Accelerometer with Analog OutputSPECIFICATIONSA MIN MAX S ADXL190WQCParameter Conditions Min Typ Max UnitsSENSOR INPUT1, 2, 3Dyn ..
ADE7756
Single Phase Energy Metering IC with Serial Interface
REV.0
Active Energy Metering IC
with Serial Interface
FUNCTIONAL BLOCK DIAGRAM
DVDD
DGND
CLKOUT
V1P
V1N
V2P
V2N
AVDD
CLKINREFIN/OUT
RESET
AGND
DINDOUTSCLKCS
SAG
IRQ
FEATURES
High Accuracy, Supports IEC 687/1036
Less than 0.1% Error over a Dynamic Range of 1000 to 1
An On-Chip User Programmable Threshold for Line
Voltage SAG Detection and PSU Supervisory
The ADE7756 Supplies Sampled Waveform Data
(20 Bits) and Active Energy (40 Bits)
Digital Power, Phase and Input Offset Calibration
An On-Chip Temperature Sensor (�3�C Typical after
Calibration)
An SPI-Compatible Serial Interface
A Pulse Output with Programmable Frequency
An Interrupt Request Pin (IRQ) and Status Register
Provide Early Warning of Register Overflow and
Other Conditions
Proprietary ADCs and DSP Provide High Accuracy
over Large Variations in Environmental Conditions
and Time
Reference 2.4 V � 8% (20 ppm/�C Typical) with External
Overdrive Capability
Single 5 V Supply, Low Power (25 mW Typical)*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; other pending.
GENERAL DESCRIPTIONThe ADE7756 is a high-accuracy electrical power measurement
IC with a serial interface and a pulse output. The ADE7756
incorporates two second-order sigma-delta ADCs, reference
circuitry, temperature sensor, and all the signal processing
required to perform active power and energy measurement.
The ADE7756 contains a sampled Waveform register and an
Active Energy register capable of holding at least five seconds of
accumulated power at full load. Data is read from the ADE7756
via the serial interface. The ADE7756 also provides a pulse output
(CF) with a frequency that is proportional to the active power.
In addition to real power information, the ADE7756 also provides
system calibration features, i.e., channel offset correction, phase
calibration, and power calibration. The part also incorporates a
detection circuit for short duration low voltage variations or sags.
The voltage threshold level and the duration (in number of half-
line cycles) of the variation are user programmable. An open drain
logic output (SAG) goes active low when a sag event occurs.
A zero crossing output (ZX) produces an output that is synchro-
nized to the zero crossing point of the line voltage. This output can
be used to extract timing or frequency information from the line.
The signal is also used internally to the chip in the calibration
mode. This permits faster and more accurate calibration of the
real power calculation. This signal is also useful for synchronization
of relay switching with a voltage zero crossing, thus improving
the relay life by reducing the risk of arcing.
The interrupt request output is an open drain, active low logic
output. The IRQ output will become active when the accumu-
lated real power register is half-full and also when the register
overflows. A status register indicates the nature of the interrupt.
The ADE7756 is available in 20-lead DIP and 20-lead
SSOP packages.
ADE7756FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
ADE7756–SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . .6
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MEASUREMENT ERROR . . . . . . . . . . . . . . . . . . . . . . . . . 8
PHASE ERROR BETWEEN CHANNELS . . . . . . . . . . . . . 8
POWER SUPPLY REJECTION . . . . . . . . . . . . . . . . . . . . . . 8
ADC OFFSET ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
GAIN ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
GAIN ERROR MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ANALOG INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
ZERO CROSSING DETECTION . . . . . . . . . . . . . . . . . . .13
LINE VOLTAGE SAG DETECTION . . . . . . . . . . . . . . . .14
Sag Level Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . .14
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Using the ADE7756 Interrupts with an MCU . . . . . . . . .15
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
TEMPERATURE MEASUREMENT . . . . . . . . . . . . . . . .16
ANALOG-TO-DIGITAL CONVERSION . . . . . . . . . . . . .16
Antialias Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . .17
Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
CHANNEL 1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Channel 1 ADC Gain Adjust . . . . . . . . . . . . . . . . . . . . . .18
Channel 1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
CHANNEL 2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Channel 2 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PHASE COMPENSATION . . . . . . . . . . . . . . . . . . . . . . . .20
ACTIVE POWER CALCULATION . . . . . . . . . . . . . . . . .21
ENERGY CALCULATION . . . . . . . . . . . . . . . . . . . . . . . .22
Integration Times under Steady Load . . . . . . . . . . . . . . .23
POWER OFFSET CALIBRATION . . . . . . . . . . . . . . . . . .23
ENERGY-TO-FREQUENCY CONVERSION . . . . . . . . .23
ENERGY CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . .24
CALIBRATING THE ENERGY METER . . . . . . . . . . . . .24
Calculating the Average Active Power . . . . . . . . . . . . . . .24
Calibrating the Frequency at CF . . . . . . . . . . . . . . . . . . .24
Energy Meter Display . . . . . . . . . . . . . . . . . . . . . . . . . . .25
CLKIN FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . .25
SUSPENDING THE ADE7756 FUNCTIONALITY . . . .26
SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Serial Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Serial Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .27
REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . .29
Communications Register . . . . . . . . . . . . . . . . . . . . . . . .29
Mode Register (06H) . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Interrupt Status Register (04H)/Reset Interrupt
Status Register (05H) . . . . . . . . . . . . . . . . . . . . . . . . . .31
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .32
TABLE OF CONTENTS
ADE7756
SPECIFICATIONS1
(AVDD = DVDD = 5 V � 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL,
TMIN to TMAX = –40�C to +85�C, unless otherwise noted.)
ADE7756–SPECIFICATIONSLOGIC INPUTS
LOGIC OUTPUTS
POWER SUPPLY
NOTESSee Terminology section for explanation of specifications.See plots in Typical Performance Characteristic curves.See Analog Inputs section.
Specifications subject to change without notice
TIMING CHARACTERISTICS1, 2NOTESSample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to
90%) and timed from a voltage level of 1.6 V.See timing diagram below and Serial Interface section of this data sheet.Measured with the load circuit in Load Circuit for Timing Specifications and defined as the time required for the output to cross 0.8 V or 2.4 V.Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Load Circuit for Timing Specifications. The measured
number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics
is the true bus relinquish time of the part and is independent of the bus loading.
Specifications subject to change without notice.
Figure 1.Load Circuit for Timing Specifications
Figure 2.Serial Write Timing
(AVDD = DVDD = 5 V � 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz
XTAL, TMIN to TMAX = –40�C to +85�C, unless otherwise noted.)
ADE7756
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADE7756 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . –0.3V to +0.3V
Analog Input Voltage to AGND
V1P, V1N, V2P and V2N . . . . . . . . . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND . . . –0.3 V to AVDD + 0.3V
Digital Input Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
20-Lead Plastic DIP, Power Dissipation . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . 260°C
20-Lead SSOP, Power Dissipation . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 112°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
PIN CONFIGURATION
DIP and SSOP Packages
PIN FUNCTION DESCRIPTIONS3AVDD
ADE7756
TERMINOLOGY
MEASUREMENT ERRORThe error associated with the energy measurement made by the
ADE7756 is defined by the following formula:
Percentage Error =
PHASE ERROR BETWEEN CHANNELSThe HPF (High-Pass Filter) in Channel 1 has a phase lead
response. To offset this phase response and equalize the phase
response between channels, a phase correction network is also
placed in Channel 1. The phase correction network ensures a
phase match between Channel 1 (current) and Channel 2 (volt-
age) to within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2°
over a range 40 Hz to 1 kHz.
POWER SUPPLY REJECTIONThis quantifies the ADE7756 measurement error as a percent-
age of reading when the power supplies are varied. For the ac
PSR measurement, a reading at nominal supplies (5 V) is taken.
A second reading is obtained with the same input signal levels
when an ac (175 mV rms/120 Hz) signal is introduced onto the
supplies. Any error introduced by this ac signal is expressed as a
percentage of reading—see Measurement Error definition above.
For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. A second reading is obtained with the same input
signal levels when the supplies are varied ±5%. Any error intro-
duced is again expressed as a percentage of reading.
ADC OFFSET ERRORThis refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND the ADCs still see a dc analog input signal. The magni-
tude of the offset depends on the gain and input range selection
—see Typical Performance Characteristics. However, when HPF1
is switched on the offset is removed from Channel 1 (current)
and the power calculation is not affected by this offset. The
offsets may be removed by performing an offset calibration—see
Analog Inputs section.
GAIN ERRORThe gain error in the ADE7756 ADCs is defined as the differ-
ence between the measured ADC output code (minus the offset)
and the ideal output code—see Channel 1 ADC and Channel 2
ADC section. It is measured for each of the input ranges on
Channel 1 (1 V, 0.5 V and 0.25 V ). The difference is expressed
as a percentage of the ideal code.
GAIN ERROR MATCHThe Gain Error Match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 (for each of
the input ranges) and a gain of 2, 4, 8, or 16. It is expressed as a
percentage of the output ADC code obtained under a gain of 1.
This gives the gain error observed when the gain selection is
changed from 1 to 2, 4, 8, or 16.
TPC 1.Error as a % of Reading (Power Factor = 1, Internal
Reference, Gain = 1)
TPC 2.Error as a % of Reading (Power Factor = 1, Internal
Reference, Gain = 2)
TPC 3.Error as a % of Reading (Power Factor = 1, Internal
Reference, Gain = 4)
TPC 4.Error as a % of Reading (Power Factor = 0.5, Internal
Reference, Gain = 1)
TPC 5.Error as a % of Reading (Power Factor = 0.5, Internal
Reference, Gain = 2)
TPC 6.Error as a % of Reading (Power Factor = 0.5, Internal
Reference, Gain = 4)
ADE7756TPC 7.Error as a % of Reading (Power Factor = 1, Internal
Reference, Gain = 8)
TPC 8.Error as a % of Reading (Power Factor = 1, Internal
Reference, Gain = 16)
TPC 9.Error as a % of Reading (Power Factor = 1,
External Reference, Gain = 1)
TPC 10.Error as a % of Reading (Power Factor = 0.5,
Internal Reference, Gain = 8)
TPC 11.Error as a % of Reading (Power Factor = 0.5,
Internal Reference, Gain = 16)
TPC 12.Error as a % of Reading (Power Factor = 1,
External Reference, Gain = 2)
TPC 13.Test Circuit for Performance Curves
TPC 14.PSR with Internal Reference
TPC 15.Error as a % of Reading over Frequency
TPC 16.PSR with External Reference
ADE7756
ANALOG INPUTSThe ADE7756 has two fully differential voltage input channels.
The maximum differential input voltage for each input pair
(V1P/V1N and V2P/V2N) is ±1 V. In addition, the maximum
signal level on each analog input (V1P, V1N, V2P, and V2N) is
also ±1 V with respect to AGND.
Each analog input channel has a PGA (Programmable Gain
Amplifier) with possible gain selections of 1, 2, 4, 8, and 16.
The gain selections are made by writing to the Gain regis-
ter—see Figure 5. Bits 0 to 2 select the gain for the PGA in
Channel 1 and the gain selection for the PGA in Channel 2 is
made via bits 5 to 7. Figure 4 shows how a gain selection for
Channel 1 is made using the Gain register.
Figure 4.PGA in Channel 1
In addition to the PGA, Channel 1 also has a full-scale input
range selection for the ADC. The ADC analog input range selec-
tion is also made using the Gain register—see Figure 5. As
mentioned previously, the maximum differential input voltage is
±1 V However, by using Bits 3 and 4 in the Gain register, the
maximum ADC input voltage can be set to 1 V, 0.5 V, or 0.25 V.
This is achieved by adjusting the ADC reference—see Reference
Circuit section. Table I summarizes the maximum differential
input signal level on Channel 1 for the various ADC range and
gain selections.
Table I.Maximum Input Signal Levels for Channel 1Figure 5.Analog Gain Register
It is also possible to adjust offset errors on Channel 1 and Channel
2 by writing to the Offset Correction Registers (CH1OS and
CH2OS respectively). These registers allow channel offsets in the
range ±20 mV to ±60 mV (depending on the gain setting) to be
removed. Note that it is not necessary to perform an offset correc-
tion in an Energy measurement application if HPF1 in Channel 1
is switched on. Figure 6 shows the effect of offsets on the real
power calculation. As can be seen from Figure 6, an offset on
Channel 1 and Channel 2 will contribute a dc component after
multiplication. Since this dc component is extracted by LPF2 to
generate the Active (Real) Power information, the offsets will
have contributed an error to the Active Power calculation. This
problem is easily avoided by enabling HPF1 in Channel 1. By
removing the offset from at least one channel, no error compo-
nent can be generated at dc by the multiplication. Error terms at
Cos(ωt) are removed by LPF2 and by integration of the Active
Power signal in the Active Energy register (AENERGY[39:0]).
See Energy Calculation section.
V�I
FREQUENCY – RADS/Sec 2�0
VOS�IOS
DC COMPONENT (INCLUDING ERROR TERM)Figure 6.Effect of Channel Offsets on the Real Power
Calculation
The contents of the Offset Correction registers are 6-bit, sign
and magnitude coded. The weighting of the LSB size depends
on the gain setting, i.e., 1, 2, 4, 8, or 16. Table II below shows
the correctable offset span for each of the gain settings and the
LSB weight (mV) for the Offset Correction registers. The
maximum value that can be written to the Offset Correction
registers is ±31 decimal—see Figure 7.
Table II.Offset Correction RangeFigure 7 shows the relationship between the Offset Correction
register contents and the offset (mV) on the analog inputs for a
gain setting of one. In order to perform an offset adjustment, The
analog inputs should be first connected to AGND. There should
be no signal on either Channel 1 or Channel 2. A read from
Channel 1 or Channel 2 using the waveform register will give an
indication of the offset in the channel. This offset can be canceled
by writing an equal and opposite offset value to the relevant offset
register. The offset correction can be confirmed by performing
another read. Note when adjusting the offset of Channel 1, one
needs to ensure the HPF has been disabled in the Mode Register.
CH1OS[7:0]Figure 7.Channel Offset Correction Range (Gain = 1)
ZERO CROSSING DETECTIONThe ADE7756 has a zero crossing detection circuit on Channel
2. This zero crossing is used to produce an external zero cross
signal (ZX) and it is also used in the calibration mode—see
Energy Calibration section. The zero crossing signal is also used
to initiate a temperature measurement on the ADE7756—see
Temperature Measurement section.
Figure 8 shows how the zero cross signal is generated from the
output of LPF1.
Figure 8.Zero Cross Detection on Channel 2
The ZX signal will go logic high on a positive going zero crossing
and logic low on a negative going zero crossing on Channel 2.
The zero crossing signal ZX is generated from the output of LPF1.
LPF1 has a single pole at 156 Hz (at CLKIN = 3.579545 MHz).
As a result there will be a phase lag between the analog input
signal V2 and the output of LPF1. The phase response of this
filter is shown in the Channel 2 Sampling section of this data
sheet. The phase lag response of LPF1 results in a time delay of
approximately 0.97 ms (@ 60 Hz) between the zero crossing on
the analog inputs of Channel 2 and the rising or falling edge of ZX.
The zero crossing detection also has an associated time-out
register ZXTOUT. This unsigned, 12-bit register is decre-
mented (1 LSB) every 128/CLKIN seconds. The register is
reset to its user-programmed full-scale value every time a zero
crossing on Channel 2 is detected. The default power-on value
in this register is FFFh. If the register decrements to zero before
a zero crossing is detected, and the DISSAG bit in the Mode
register is Logic 0, the SAG pin will go active low. The absence of
a zero crossing is also indicated on the IRQ output if the SAG
enable bit in the Interrupt Enable register is set to Logic 1.
Irrespective of the enable bit setting, the SAG flag in the Inter-
rupt Status register is always set when the ZXTOUT register is
decremented to zero—see ADE7756 Interrupts section.
The Zero-Cross Time-Out register can be written/read by the
user and has an address of 0Eh—see Serial Interface section.
The resolution of the register is 128/CLKIN seconds per LSB.
Thus the maximum delay for an interrupt is 0.15 second (128/
CLKIN × 212).
ADE7756
LINE VOLTAGE SAG DETECTIONIn addition to the detection of the loss of the line voltage signal
(zero crossing), the ADE7756 can also be programmed to detect
when the absolute value of the line voltage drops below a certain
peak value, for a number of half-cycles. This condition is illus-
trated in Figure 9.
Figure 9.ADE7756 Sag Detection
Figure 9 shows the line voltage fall below a threshold that is set
in the Sag Level register (SAGLVL[7:0]) for nine half-cycles.
Since the Sag Cycle register (SAGCYC[7:0]) contains 06h, the
SAG pin will go active low at the end of the sixth half-cycle for
which the line voltage falls below the threshold, if the DISSAG
bit in the Mode register is Logic 0. As is the case when zero-
crossings are no longer detected, the sag event is also recorded
by setting the SAG flag in the Interrupt Status register. If the
SAG enable bit is set to Logic 1, the IRQ logic output will go
active low—see ADE7756 Interrupts section.
The SAG pin will go logic high again when the absolute value
of the signal on Channel 2 exceeds the sag level set in the Sag
Level register. This is shown in Figure 9 when the SAG pin goes
high during the tenth half-cycle from the time when the signal
on Channel 2 first dropped below the threshold level.
Sag Level SetThe contents of the Sag Level register (1 byte) are compared to
the absolute value of the most significant byte output from
LPF1, after it is shifted left by one bit. Thus for example the
nominal maximum code from LPF1 with a full scale signal on
Channel 2 is 1C396h or (0001, 1100, 0011, 1001, 0110b)—see
Channel 2 Sampling section. Shifting one bit left will give 0011,
1000, 0111, 0010, 1100b or 3872Ch. Therefore writing 38h to
the Sag Level register will put the sag detection level at full
scale. Writing 00h will put the sag detection level at zero. The
Sag Level register is compared to the most significant byte of a
waveform sample after the shift left and detection is made when
the contents of the sag level register are greater.
POWER SUPPLY MONITORThe ADE7756 also contains an on-chip power supply monitor.
The Analog Supply (AVDD) is continuously monitored by the
ADE7756. If the supply is less than 4 V ± 5%, the ADE7756 will
be inactive, i.e., no energy will accumulate regardless of the
input signals at Channel 1 and Channel 2. This is useful to ensure
correct device operation at power-up and during power-down.
The power supply monitor has built-in hysteresis and filtering.
This gives a high degree of immunity to false triggering due to
noisy supplies.
Figure 10.On-Chip Power Supply Monitor
As can be seen from Figure 10, the trigger level is nominally set
at 4 V. The tolerance on this trigger level is about ±5%. The
SAG pin can also be used as a power supply monitor input to
the MCU. The SAG pin will go logic low when the ADE7756 is
reset. The power supply and decoupling for the part should
be such that the ripple at AVDD does not exceed 5 V ± 5% as
specified for normal operation.
INTERRUPTSInterrupts are managed through the Interrupt Status register
(STATUS[7:0]) and the Interrupt Enable register (IRQEN[7:0]).
When an interrupt event occurs in the ADE7756, the corre-
sponding flag in the Status register is set to a Logic 1—see
Interrupt Status register. If the enable bit for this interrupt in
the Interrupt Enable register is Logic 1, the IRQ logic output
goes active low. The flag bits in the Status register are set irre-
spective of the state of the enable bits.
In order to determine the source of the interrupt, the system mas-
ter (MCU) should perform a read from the Status register with
reset (RSTATUS[7:0]). This is achieved by carrying out a read
from address 05h. The IRQ output will go logic high on comple-
tion of the Interrupt Status register read command—see Interrupt
Timing section. When carrying out a read with reset the ADE7756
is designed to ensure that no interrupt events are missed. If an
interrupt event occurs just as the Status register is being read,
the event will not be lost and the IRQ logic output is guaranteed
to go high for the duration of the Interrupt Status register data
transfer before going logic low again to indicate the pending
interrupt. See the next section for a more detailed description.
Using the ADE7756 Interrupts with an MCUShown in Figure 11 is a timing diagram that shows a sug-
gested implementation of ADE7756 interrupt management
using an MCU. At time t1 the IRQ line will go active low indi-
cating that one or more interrupt events have occurred in the
ADE7756. The IRQ logic output should be tied to a negative
edge-triggered external interrupt on the MCU. On detection of
the negative edge, the MCU should be configured to start execut-
ing its Interrupt Service Routine (ISR). On entering the ISR, all
interrupts should be disabled using the global interrupt enable
bit. At this point the MCU external interrupt flag can be cleared
in order to capture interrupt events that occur during the current
ISR. When the MCU interrupt flag is cleared a read from the
Status register with reset is carried out. This will cause the IRQ
line to be reset logic high (t2)—see Interrupt timing section. The
Status register contents are used to determine the source of the
interrupt(s) and hence the appropriate action to be taken. If a
subsequent interrupt event occurs during the ISR, that event will
be recorded by the MCU external interrupt flag being set again
(t3). On returning from the ISR, the global interrupt mask will
be cleared (same instruction cycle) and the external interrupt
flag will cause the MCU to jump to its ISR once again. This will
ensure that the MCU does not miss any external interrupts.
Interrupt TimingThe Serial Interface section should be reviewed first, before
reviewing the interrupt timing. As previously described, when
the IRQ output goes low the MCU ISR must read the Interrupt
Status register in order to determine the source of the interrupt.
When reading the Status register contents, the IRQ output is set
high on the last falling edge of SCLK of the first byte transfer
(read Interrupt Status register command). The IRQ output is
held high until the last bit of the next 8-bit transfer is shifted out
(Interrupt Status register contents). See Figure 12. If an inter-
rupt is pending at this time, the IRQ output will go low again. If
no interrupt is pending the IRQ output will stay high.
Figure 11.Interrupt Management
Figure 12.Interrupt Timing
ADE7756
TEMPERATURE MEASUREMENTADE7756 also includes an on-chip temperature sensor. A tem-
perature measurement can be made by setting Bit 5 in the Mode
register. When Bit 5 is set logic high in the Mode register, the
ADE7756 will initiate a temperature measurement on the next
zero crossing. When the zero crossing on Channel 2 is detected,
the voltage output from the temperature sensing circuit is con-
nected to ADC1 (Channel 1) for digitizing. The resultant code
is processed and placed in the Temperature register (TEMP[7:0])
approximately 26 µs later (24 CLKIN cycles). If enabled in the
Interrupt Enable register (Bit 5), the IRQ output will go active
low when the temperature conversion is finished. Please note
that temperature conversion will introduce a small amount of
noise in the energy calculation. If temperature conversion is
performed frequently (e.g., multiple times per second), a
noticeable error will accumulate in the resulting energy calcu-
lation over time.
The contents of the Temperature register are signed (two’s
complement) with a resolution of approximately 1 LSB/°C. The
temperature register will produce a code of 00h when the ambi-
ent temperature is approximately 70°C—see Figure 13. The
temperature measurement is uncalibrated in the ADE7756 and
has an offset tolerance that could be as high as ±20°C.
Figure 13.Temperature Register
ANALOG-TO-DIGITAL CONVERSIONThe analog-to-digital conversion in the ADE7756 is carried out
using two second-order sigma-delta ADCs. The block diagram
in Figure 14 shows a first-order (for simplicity) sigma-delta
ADC. The converter is made up of two parts, first the sigma-
delta modulator and second the digital low-pass filter.
A sigma-delta modulator converts the input signal into a con-
tinuous serial stream of 1s and 0s at a rate determined by the
sampling clock. In the ADE7756 the sampling clock is equal to
CLKIN/4. The 1-bit DAC in the feedback loop is driven by the
serial data stream. The DAC output is subtracted from the input
signal. If the loop gain is high enough, the average value of the
DAC output (and therefore the bit stream) will approach that of
the input signal level. For any given input value in a single
sampling interval, the data from the 1-bit ADC is virtually mean-
ingless. Only when a large number of samples are averaged, will
a meaningful result be obtained. This averaging is carried out in
the second part of the ADC, the digital low-pass filter. By aver-
aging a large number of bits from the modulator the low-pass
filter can produce 20-bit data words that are proportional to the
input signal level.
The sigma-delta converter uses two techniques to achieve high
resolution from what is essentially a 1-bit conversion technique.
The first is oversampling. By oversampling we mean that the
signal is sampled at a rate (frequency) that is many times higher
than the bandwidth of interest. For example, the sampling rate
in the ADE7756 is CLKIN/4 (894 kHz) and the band of interest
is 40 Hz to 2 kHz. Oversampling has the effect of spreading
the quantization noise (noise due to sampling) over a wider
bandwidth. With the noise spread more thinly over a wider
bandwidth, the quantization noise in the band of interest is
lowered—see Figure 15. However oversampling alone is not an
efficient enough method to improve the signal to noise ratio
(SNR) in the band of interest. For example, an oversampling
ratio of 4 is required just to increase the SNR by only 6 dB
(1 bit). To keep the oversampling ratio at a reasonable level, it is
possible to shape the quantization noise so that the majority of
the noise lies at the higher frequencies. This is what happens in
the sigma-delta modulator, the noise is shaped by the integrator
which has a high-pass-type response for the quantization noise.
The result is that most of the noise is at the higher frequencies
where it can be removed by the digital low-pass filter. This noise
shaping is also shown in Figure 15.
Figure 14.First Order Sigma-Delta (Σ-∆) ADC
SIGNAL
FREQUENCY – kHz 447 894 2
SAMPLING
ANTIALIAS
FILTER (RC) DIGITAL
SIGNAL 447 894 2
