ADE7754ARRL ,Poly Phase Multi-functional Metering IC With Serial PortCHARACTERISTICS . . . . . 7 Communications Register . . . . . . . . . . . . . . . . . . . . . . . . ..
ADE7755 ,Single Phase Energy Metering IC with Synchronized Pulse Outputspecifications surpass the accuracy requirements asLess than 0.1% Error over a Dynamic Range of quo ..
ADE7755ARS ,Energy Metering IC with Pulse OutputSpecifications Unit Test Conditions/Comments1, 2ACCURACY1Measurement Error on Channel 1 Channel 2 w ..
ADE7755ARS-RL ,Energy Metering IC with Pulse OutputSpecifications Unit Test Conditions/Comments3t 275 ms F1 and F2 Pulsewidth (Logic Low)1t See Table ..
ADE7756 ,Single Phase Energy Metering IC with Serial Interfacefeatures, i.e., channel offset correction, phaseDigital Power, Phase and Input Offset Calibrationca ..
ADE7756ARS ,Single Phase Energy Metering IC with Serial Interfacefeatures, i.e., channel offset correction, phaseDigital Power, Phase and Input Offset Calibrationca ..
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ADXL103CE-REEL ,High Precision, ±1.5g, Single Axis AccelerometerSPECIFICATIONS Table 1. TA = –40°C to +125°C, VS = 5 V, CX = CY = 0.1 μF, Acceleration = 0 g, unles ..
ADXL105AQC ,High Accuracy 61 g to 65 g Single Axis iMEMS Accelerometer with Analog InputGENERAL DESCRIPTIONcal of vibration) or static accelerations (such as inertial force,The ADXL105 is ..
ADXL105JQC ,High Accuracy 61 g to 65 g Single Axis iMEMS Accelerometer with Analog InputSPECIFICATIONS␣␣␣␣␣␣␣ ADXL105J/AParameterConditionsMinTypMaxUnitsSENSOR INPUT1Measurement Ran ..
ADXL150AQC ,+-5 g to +-50 g, Low Noise, Low Power, Single/Dual Axis iMEMS AccelerometersSPECIFICATIONS V = +5.00 V, Acceleration = Zero g, unless otherwise noted)S ADXL150JQC/AQC ADX ..
ADXL150EM-1 ,±50g Single Axis Accelerometer with Analog OutputGENERAL DESCRIPTION 5kV+VSThe ADXL150 and ADXL250 are third generation ±50 g sur-CLOCK 2face microm ..
ADE7754AR-ADE7754ARRL
Poly Phase Multi-functional Metering IC With Serial Port
REV.0 *Patents pending.
Polyphase Multifunction
Energy Metering IC with Serial Port
FUNCTIONAL BLOCK DIAGRAM
IAP
IAN
VAP
IBP
IBN
VBP
ICP
ICN
VCP
AGNDREFIN/OUTDINDOUTSCLKCSIRQ
DVDD
DGND
CLKIN
CLKOUT
RESETAVDD
FEATURES
High Accuracy, Supports IEC 687/61036
Compatible with 3-Phase/3-Wire, 3-Phase/4-Wire
and any Type of 3-Phase Services
Less than 0.1% Error in Active Power Measurement over a
Dynamic Range of 1000 to 1
Supplies Active Energy, Apparent Energy, Voltage RMS,
Current RMS, and Sampled Waveform Data
Digital Power, Phase, and Input Offset Calibration
On-Chip Temperature Sensor (�4�C Typical after Calibration)
On-Chip User Programmable Thresholds for Line Voltage
SAG and Overdrive Detections
SPI Compatible Serial Interface with Interrupt
Request Line (IRQ)
Pulse Output with Programmable Frequency
Proprietary ADCs and DSP Provide High Accuracy over
Large Variations in Environmental Conditions and Time
Single 5 V Supply
GENERAL DESCRIPTIONThe ADE7754 is a high accuracy polyphase electrical energy
measurement IC with a serial interface and a pulse output. The
ADE7754 incorporates second order Σ-∆ ADCs, reference
circuitry, temperature sensor, and all the signal processing
required to perform active, apparent energy measurements, and
rms calculation.
The ADE7754 provides different solutions for measuring active
and apparent energy from the six analog inputs, thus enabling
the use of the ADE7754 in various power meter services such as
3-phase/4-wire, 3-phase/3-wire, and 4-wire delta.
In addition to rms calculation, active and apparent power infor-
mation, the ADE7754 provides system calibration features for
each phase (i.e., channel offset correction, phase calibration,
and gain calibration). The CF logic output provides instanta-
neous active power information.
The ADE7754 has a waveform sample register that enables
access to ADC outputs. The part also incorporates a detection
circuit for short duration low or high voltage variations. The
voltage threshold levels and the duration (number of half line
cycles) of the variation are user programmable.
A zero-crossing detection is synchronized with the zero-crossing
point of the line voltage of each of the three phases. The infor-
mation collected is used to measure each line’s period. It is also
used internally to the chip in the line active energy and line
apparent energy accumulation modes. This permits faster and
more accurate calibration of the power calculations. This signal
is also useful for synchronization of relay switching.
Data is read from the ADE7754 via the SPI serial interface. The
interrupt request output (IRQ) is an open-drain, active low
logic output. The IRQ output goes active low when one or more
interrupt events have occurred in the ADE7754. A status regis-
ter indicates the nature of the interrupt.
The ADE7754 is available in a 24-lead SOIC package.
ADE7754
ContentsGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . .4
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . .5
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . .5
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . .5
TYPICAL PERFORMANCE CHARACTERISTICS . . . . .7
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Measurement Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Phase Error Between Channels . . . . . . . . . . . . . . . . . . . . .9
Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . .9
ADC Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Gain Error Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . . .9
ANALOG INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
ANALOG-TO-DIGITAL CONVERSION . . . . . . . . . . . . .10
Antialias Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CURRENT CHANNEL ADC . . . . . . . . . . . . . . . . . . . . . .11
Current Channel ADC Gain Adjust . . . . . . . . . . . . . . . . .11
Current Channel Sampling . . . . . . . . . . . . . . . . . . . . . . .11
VOLTAGE CHANNEL ADC . . . . . . . . . . . . . . . . . . . . . .12
ZERO-CROSSING DETECTION . . . . . . . . . . . . . . . . . . .12
Zero-Crossing Timeout . . . . . . . . . . . . . . . . . . . . . . . . . .13
PERIOD MEASUREMENT . . . . . . . . . . . . . . . . . . . . . . .13
LINE VOLTAGE SAG DETECTION . . . . . . . . . . . . . . . .13
PEAK DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Peak Level Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
TEMPERATURE MEASUREMENT . . . . . . . . . . . . . . . .14
PHASE COMPENSATION . . . . . . . . . . . . . . . . . . . . . . . .14
ROOT MEAN SQUARE MEASUREMENT . . . . . . . . . . .15
Current RMS Calculation . . . . . . . . . . . . . . . . . . . . . . . .15
Current RMS Gain Adjust . . . . . . . . . . . . . . . . . . . . . .16
Current RMS Offset Compensation . . . . . . . . . . . . . . .16
Voltage RMS Calculation . . . . . . . . . . . . . . . . . . . . . . . . .16
Voltage RMS Gain Adjust . . . . . . . . . . . . . . . . . . . . . .16
Voltage RMS Offset Compensation . . . . . . . . . . . . . . .17
ACTIVE POWER CALCULATION . . . . . . . . . . . . . . . . .17
Power Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . .18
Reverse Power Information . . . . . . . . . . . . . . . . . . . . . . .18
TOTAL ACTIVE POWER CALCULATION . . . . . . . . . .18
ENERGY CALCULATION . . . . . . . . . . . . . . . . . . . . . . . .19
Integration Times Under Steady Load . . . . . . . . . . . . . . .20
Energy to Frequency Conversion . . . . . . . . . . . . . . . . . . .20
No Load Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Mode Selection of the Sum of the Three Active Energies .22
LINE ENERGY ACCUMULATION . . . . . . . . . . . . . . . . .22
REACTIVE POWER CALCULATION . . . . . . . . . . . . . . .23
TOTAL REACTIVE POWER CALCULATION . . . . . . . .24
Reactive Energy Accumulation Selection . . . . . . . . . . . . .24
APPARENT POWER CALCULATION . . . . . . . . . . . . . .24
Apparent Power Offset Calibration . . . . . . . . . . . . . . . . .25
TOTAL APPARENT POWER CALCULATION . . . . . . .25
APPARENT ENERGY CALCULATION . . . . . . . . . . . . .26
Integration Times under Steady Load . . . . . . . . . . . . . . .26
ENERGIES SCALING . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
CHECK SUM REGISTER . . . . . . . . . . . . . . . . . . . . . . . . .27
SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Serial Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Serial Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .29
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Using Interrupts with an MCU . . . . . . . . . . . . . . . . . . . .30
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
ACCESSING THE ADE7754 ON-CHIP REGISTERS . .31
Communications Register . . . . . . . . . . . . . . . . . . . . . . . .31
Operational Mode Register (0Ah) . . . . . . . . . . . . . . . . . .35
Gain Register (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
CFNUM Register (25h) . . . . . . . . . . . . . . . . . . . . . . . . . .36
Measurement Mode Register (0Bh) . . . . . . . . . . . . . . . . .37
Waveform Mode Register (0Ch) . . . . . . . . . . . . . . . . . . .37
Watt Mode Register (0Dh) . . . . . . . . . . . . . . . . . . . . . . .38
VA Mode Register (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . .38
Interrupt Enable Register(0Fh) . . . . . . . . . . . . . . . . . . . .39
Interrupt Status Register (10h)/Reset Interrupt Status
Register (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .41
ADE7754–SPECIFICATIONS
(AVDD = DVDD = 5 V � 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz,
TMIN to TMAX = –40�C to +85�C, unless otherwise noted.)NOTESSee Terminology section for explanation of specifications.See plots in the Typical Performance Characteristics section.
ADE7754
TIMING CHARACTERISTICS1, 2(AVDD = DVDD = 5 V � 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz XTAL,
TMIN to TMAX = –40�C to +85�C, unless otherwise noted.)Read Timing
NOTESSample tested during initial release and after any redesign or process change
that may affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.See timing diagrams below and Serial Interface section of this data sheet.Minimum time between read command and data read for all registers except
wavmode register, which is t9 = 500 ns min.Measured with the load circuit in Figure 1 and defined as the time required for
the output to cross 0.8 V or 2.4 V.Derived from the measured time taken by the data outputs to change 0.5 V
when loaded with the circuit in Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF
capacitor. The time quoted in the timing characteristics is the true bus relin-
quish time of the part and is independent of the bus loading.
Figure 1. Load Circuit for Timing Specifications
Figure 2.Serial Write Timing
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADE7754 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C, unless otherwise noted.)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 Vto +0.3 V
Analog Input Voltage to AGND
IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP, VCP, VN . . –6 V to +6 V
Reference Input Voltage to AGND . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . –0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
PIN CONFIGURATION
ORDERING GUIDE*RW = Small Outline (Wide Body Package in Tubes)
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
24-Lead SOIC, Power Dissipation . . . . . . . . . . . . . . . 88 mW
�JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . 53°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN FUNCTION DESCRIPTIONS
ADE7754
PIN FUNCTION DESCRIPTIONS (continued)4AVDD
5, 6;
7, 8;
9, 10
13, 14;
CURRENT (% fs)
PERCENT ERROR
0.010.1110100TPC 1. Real Power Error as a Percentage of
Reading with Gain = 1 and Internal Reference
(WYE Connection)
CURRENT (% fs)
PERCENT ERROR
0.010.1110100TPC 2. Real Power Error as a Percentage of
Reading over Power Factor with Internal
Reference (DELTA Connection)
CURRENT (% fs)
PERCENT ERROR
0.80TPC 3. Real Power Error as a Percentage of Reading
CURRENT INPUT (% fs)
PERCENT ERROR
0.80TPC 4. Current RMS Error as a Percentage of
Reading with Internal Reference (Gain = 1)
VOLTAGE INPUT (% fs)
PERCENT ERROR
0.40TPC 5. Voltage RMS Error as a Percentage of
Reading with Internal Reference (Gain = 1)
VOLTAGE INPUT (% fs)
PERCENT ERROR
0.40TPC 6. Real Power Error as a Percentage of Reading
ADE7754TPC 7. Real Power Error as a Percentage of Read-
ing over Input Frequency with Internal Reference
PERCENT ERROR
CURRENT INPUT (% fs)TPC 8. Real Power Error as a Percentage of Read-
ing over Power Supply with External Reference
(Gain = 1)
PERCENT ERROR
CURRENT INPUT (% fs)100
0.20TPC 9. Real Power Error as a Percentage of Reading
TPC 10. Test Circuit for Performance Curves
CH_I PhA OFFSET (mV)
PERCENT ERROR
–15–10–505101520TPC 11. Current Channel Offset Distribution (Gain = 1)
TERMINOLOGY
Measurement ErrorThe error associated with the energy measurement made by the
ADE7754 is defined by the formula
Phase Error Between ChannelsThe HPF (high-pass filter) in the current channel has a phase
lead response. To offset this phase response and equalize the
phase response between channels, a phase correction network is
placed in the current channel. The phase correction network
ensures a phase match between the current channels and voltage
channels to within ±0.1° over a range of 45 Hz to 65 Hz and0.2° over a range of 40 Hz to 1 kHz. This phase mismatch
between the voltage and the current channels can be reduced
further with the phase calibration register in each phase.
Power Supply RejectionThis quantifies the ADE7754 measurement error as a percentage
of reading when power supplies are varied. For the ac PSR mea-
surement, a reading at nominal supplies (5 V) is taken. A second
reading is obtained using the same input signal levels when an ac
(175 mV rms/100 Hz) signal is introduced onto the supplies. Any
error introduced by this ac signal is expressed as a percentage of
reading. See the Measurement Error definition above.
For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. A second reading is obtained using the same
input signal levels when the power supplies are varied ±5%. Any
error introduced is again expressed as a percentage of reading.
ADC Offset ErrorThis refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND, the ADCs still see a dc analog input signal. The magni-
tude of the offset depends on the gain and input range selection
(see the TPCs). However, when HPFs are switched on, the
offset is removed from the current channels and the power
calculation is unaffected by this offset.
Gain ErrorThe gain error in the ADE7754 ADCs is defined as the differ-
ence between the measured ADC output code (minus the
offset) and the ideal output code. See the Current Channel
ADC and the Voltage Channel ADC sections. The difference is
expressed as a percentage of the ideal code.
Gain Error MatchGain error match is defined as the gain error (minus the offset)
obtained when switching between a gain of 1, 2, or 4. It is
expressed as a percentage of the output ADC code obtained
under a gain of 1.
POWER SUPPLY MONITORThe ADE7754 contains an on-chip power supply monitor. The
analog supply (AVDD) is continuously monitored by the ADE7754.
If the supply is less than 4 V ± 5%, the ADE7754 goes into an
inactive state (i.e., no energy is accumulated when the supply
voltage is below 4 V). This is useful to ensure correct device
STATUS REGISTERFigure 4. On-Chip Power Supply Monitoring
The RESET bit in the interrupt status register is set to Logic 1
when AVDD drops below 4 V ± 5%. The RESET flag is always
masked by the interrupt enable register and cannot cause the
IRQ pin to go low. The power supply and decoupling for the
part should ensure that the ripple at AVDD does not exceed 5 V
± 5% as specified for normal operation.
ANALOG INPUTSThe ADE7754 has six analog inputs, divisible into two chan-
nels: current and voltage. The current channel consists of three
pairs of fully differential voltage inputs: IAP, IAN; IBP, IBN; and
ICP, ICN. The fully differential voltage input pairs have a maxi-
mum differential voltage of ±0.5 V. The voltage channel has
three single-ended voltage inputs: VAP, VBP, and VCP. These
single-ended voltage inputs have a maximum input voltage of
±0.5 V with respect to VN. Both the current channel and the
voltage channel have a PGA (programmable gain amplifier) with
possible gain selections of 1, 2, or 4. The same gain is applied to
all the inputs of each channel.
The gain selections are made by writing to the gain register. Bits 0
and 1 select the gain for the PGA in the fully differential current
channel. The gain selection for the PGA in the single-ended volt-
age channel is made via Bits 5 and 6. Figure 5 shows how a gain
selection for the current channel is made using the gain register.
Figure 5. PGA in Current Channel
ADE7754Figure 6 shows how the gain settings in PGA 1 (current channel)
and PGA 2 (voltage channel) are selected by various bits in the
gain register. The no-load threshold and sum of the absolute
value can also be selected in the gain register. See Table X.
6543210
RESERVED = 0
PGA 2 GAIN SELECT
00 = �1
01 = �2
10 = �4
PGA 1 GAIN SELECT
00 = �1
01 = �2
10 = �4
NO LOAD
ABS
GAIN REGISTER*
CURRENT AND VOLTAGE CHANNEL PGA CONTROL
*REGISTER CONTENTS SHOW POWER-ON DEFAULTS
ADDR: 18hFigure 6.Analog Gain Register
ANALOG-TO-DIGITAL CONVERSIONThe ADE7754 carries out analog-to-digital conversion using
second order Σ-∆ ADCs. The block diagram in Figure 7 shows a
first order (for simplicity) Σ-∆ ADC. The converter is made up of
two parts, the Σ-∆ modulator and the digital low-pass filter.
Figure 7. First Order (�-�) ADC
A Σ-∆ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7754, the sampling clock is equal to CLKIN/12.
The 1-bit DAC in the feedback loop is driven by the serial data
stream. The DAC output is subtracted from the input signal.
If the loop gain is high enough, the average value of the DAC
output (and therefore the bit stream) will approach that of the
input signal level. For any given input value in a single sampling
interval, the data from the 1-bit ADC is virtually meaningless. Only
when a large number of samples are averaged will a meaningful
result be obtained. This averaging is carried out in the second part
of the ADC, the digital low-pass filter. Averaging a large number of
bits from the modulator, the low-pass filter can produce 24-bit
data-words that are proportional to the input signal level.
The Σ-∆ converter uses two techniques to achieve high resolu-
tion from what is essentially a 1-bit conversion technique. The
first is oversampling; the signal is sampled at a rate (frequency)
many times higher than the bandwidth of interest. For example,
the sampling rate in the ADE7754 is CLKIN/12 (833 kHz),
and the band of interest is 40 Hz to 2 kHz. Oversampling
spreads the quantization noise (noise due to sampling) over a
wider bandwidth. With the noise spread more thinly over a
wider bandwidth, the quantization noise in the band of interest
is lowered. See Figure 8.
Oversampling alone is not an efficient enough method to
improve the signal to noise ratio (SNR) in the band of interest.
For example, an oversampling ratio of 4 is required to increase
the SNR by only 6 dB (1 bit). To keep the oversampling ratio at
a reasonable level, the quantization noise can be shaped so that
most of the noise lies at the higher frequencies. In the Σ-∆
modulator, the noise is shaped by the integrator, which has a
high-pass type of response for the quantization noise. The result
is that most of the noise is at the higher frequencies, where it
can be removed by the digital low-pass filter. This noise shaping
is shown in Figure 8.
FREQUENCY (kHz)
ANTIALIAS FILTER (RC)
SIGNAL
SIGNAL
FREQUENCY (kHz)Figure 8. Noise Reduction Due to Oversampling
and Noise Shaping in the Analog Modulator
Antialias FilterFigure 7 shows an analog low-pass filter (RC) on the input to
the modulator. This filter is used to prevent aliasing, an artifact
of all sampled systems. Frequency components in the input
signal to the ADC that are higher than half the sampling rate of
the ADC appear in the sampled signal at a frequency below half
the sampling rate. Figure 9 illustrates the effect; frequency com-
ponents (arrows shown in black) above half the sampling
frequency (also known as the Nyquist frequency), i.e., 417 kHz,
get imaged or folded back down below 417 kHz (arrows shown
in gray). This happens with all ADCs, regardless of the archi-
tecture. In the example shown, only frequencies near the sampling
frequency, i.e., 833 kHz, will move into the band of interest for
metering, i.e., 40 Hz to 2 kHz. This allows use of a very simple
LPF (low-pass filter) to attenuate these high frequencies (near
900 kHz) and thus prevent distortion in the band of interest. A
simple RC filter (single pole) with a corner frequency of 10 kHz
produces an attenuation of approximately 40 dBs at 833 kHz.
See Figure 9. This is sufficient to eliminate the effects of aliasing.
Figure 9. ADC and Signal Processing in Current
Channel or Voltage Channel
CURRENT CHANNEL ADCFigure 10 shows the ADC and signal processing chain for the
input IA of the current channels (which are the same for IB and
IC). In waveform sampling mode, the ADC outputs are signed
twos complement 24-bit data-word at a maximum of 26 kSPS
(kilo samples per second). The output of the ADC can be
scaled by ±50% by using the APGAINs register. While the
ADC outputs are 24-bit twos complement value, the maximum
full-scale positive value from the ADC is limited to 400000h
(+4,194,304d). The maximum full-scale negative value is lim-
ited to C00000h (–4,194,304d). If the analog inputs are
overranged, the ADC output code clamps at these values. With
the specified full-scale analog input signal of ±0.5 V, the ADC
produces an output code between D70A3Eh (–2,684,354) and
28F5C2h (+2,684,354), as illustrated in Figure 10, which also
shows a full-scale voltage signal being applied to the differential
inputs IAP and IAN.
Current Channel ADC Gain AdjustThe ADC gain in each phase of the current channel can be
adjusted using the multiplier and active power gain register
(AAPGAIN[11:0], BAPGAIN, and CAPGAIN). The gain of the
ADC is adjusted by writing a twos complement 12-bit word to
the active power gain register. The following expression shows
how the gain adjustment is related to the contents of that register:
For example, when 7FFh is written to the active power gain
register, the ADC output is scaled up by 50%: 7FFh = 2047d,
2047/212 = 0.5. Similarly, 800h = –2047d (signed twos comple-
ment) and ADC output is scaled by –50%. These two examples
are illustrated in Figure 10.
Current Channel SamplingThe waveform samples of the current channel inputs may also
be routed to the waveform register (wavmode register to select
the speed and the phase) to be read by the system master
(MCU). The active energy and apparent energy calculation remains
uninterrupted during waveform sampling.
When in waveform sample mode, one of four output sample
rates may be chosen using Bits 3 and 4 of the WAVMODE
register (DTRT[1:0] mnemonic). The output sample rate
may be 26.0 kSPS, 13.0 kSPS, 6.5 kSPS, or 3.3 kSPS. See the
Waveform Mode Register section. By setting the WSMP bit in
the interrupt enable register to Logic 1, the interrupt request
output IRQ will go active low when a sample is available. The
timing is shown in Figure 11. The 24-bit waveform samples are
transferred from the ADE7754 one byte (eight bits) at a time,
with the most significant byte shifted out first.
Figure 11. Waveform Sampling Current Channel
The interrupt request output IRQ stays low until the interrupt
routine reads the reset status register. See the Interrupt section.
Note that if the WSMP bit in the interrupt enable register is not
set to Logic 1, no data is available in the waveform register.
IAP
IAN
AAPGAIN[11:0]
VIN
000000h
400000h
28F5C2h
D70A3Eh
00000h
28F5C2hD70A3Eh
3D70A3h
147AE1h
EB851Fh
C28F5Dh
AAPGAIN[11:0]
ANALOG
INPUT
RANGE
CHANNEL 1
ACTIVE AND REACTIVE
POWER CALCULATION
WAVEFORM SAMPLE
REGISTER
MULTIPLIERDIGITAL LPF�1, �2, �4
CURRENT RMS
CALCULATION
VIN
ADE7754
VOLTAGE CHANNEL ADCFigure 12 shows the ADC and signal processing chain for the
input VA in voltage channel (which is the same for VB and VC).
VAP�1, �2, �4
ANALOG
INPUT RANGE
TO ACTIVE AND
REACTIVE ENERGY
CALCULATION
27E9h
D817h
LPF OUTPUT
WORD RANGE
TO VOLTAGE RMS AND
WAVEFORM SAMPLING
2838h
D7C8hFigure 12. ADC and Signal Processing in Voltage Channel
For energy measurements, the output of the ADC (one bit) is
passed directly to the multiplier and is not filtered. This solution
avoids a wide-bits multiplier and does not affect the accuracy of
the measurement. An HPF is not required to remove any dc
offset since it is only required to remove the offset from one
channel to eliminate errors in the power calculation.
In the voltage channel, the samples may also be routed to the
WFORM register (WAVMODE to select VA, VB, or VC and
sampling frequency). However, before being passed to the wave-
form register, the ADC output is passed through a single-pole,
low-pass filter with a cutoff frequency of 260 Hz. The plots in
Figure 13 show the magnitude and phase response of this filter.
The filter output code of any inputs of the voltage channel
swings between D70Bh (–10,485d) and 28F5h (+10,485d) for
full-scale sine wave inputs. This has the effect of attenuating the
signal. For example, if the line frequency is 60 Hz, the signal at
the output of LPF1 will be attenuated by 3%.
Note that LPF1 does not affect the power calculation because it
is used only in the waveform sample mode and rms calculation.
In waveform sample mode, one of four output sample rates
can be chosen by using Bits 3 and 4 of the WAVMODE regis-
ter. The available output sample rates are 26 kSPS, 13.5 kSPS,
6.5 kSPS, or 3.3 kSPS. The interrupt request output IRQ
signals a new sample availability by going active low. The
voltage waveform register is a twos complement 16-bit register.
Because the waveform register is a 24-bit signed register, the
waveform data from the voltage input is located in the 16 LSB of
the waveform register. The sign of the 16-bit voltage input value
is not extended to the upper byte of the waveform register. The
upper byte is instead filled with zeros. 24-bit waveform samples
are transferred from the ADE7754 one byte (eight bits) at a time,
with the most significant byte shifted out first. The timing is the
same as that for the current channels and is shown in Figure 11.
ZERO-CROSSING DETECTIONThe ADE7754 has rising edge zero-crossing detection circuits
for each of voltage channels (VAP, VBP, and VCP). Figure 14
shows how the zero-cross signal is generated from the output of
the ADC of the voltage channel.
Figure 14. Zero-Crossing Detection on Voltage Channel
The zero-crossing interrupt is generated from the output of
LPF1, which has a single pole at 260 Hz (CLKIN = 10 MHz).
As a result, there is a phase lag between the analog input signal
of the voltage channel and the output of LPF1. The phase
response of this filter is shown in the Voltage Channel ADC
section. The phase lag response of LPF1 results in a time delay
of approximately 0.6 ms (@ 60 Hz) between the zero crossing
on the analog inputs of voltage channel and the falling of IRQ.
When one phase crosses zero from negative to positive values
(rising edge), the corresponding flag in the interrupt status
register (Bits 7 to 9) is set Logic 1. An active low in the IRQ
output also appears if the corresponding ZX bit in the interrupt
enable register is set to Logic 1.
The flag in the interrupt status register is reset to 0 when the inter-
In addition to the enable bits, the zero-crossing detection interrupt
of each phase is enabled/disabled by setting the ZXSEL bits of the
MMODE register (Address 0Bh) to Logic 1 or 0, respectively.
Zero-Crossing TimeoutEach zero-crossing detection has an associated internal timeout
register (not accessible to the user). This unsigned, 16-bit regis-
ter is decremented (1 LSB) every 384/CLKIN seconds. The
registers are reset to a common user programmed value (i.e.,
zero cross timeout register—ZXTOUT, Address 12h) every
time a zero crossing is detected on its associated input. The
default value of ZXTOUT is FFFFh. If the internal register
decrements to zero before a zero crossing at the corresponding
input is detected, it indicates an absence of a zero crossing in
the time determined by the ZXTOUT. The ZXTO detection
bit of the corresponding phase in the interrupt status register is
then switched on (Bits 4 to 6). An active low on the IRQ output
also appears if the SAG enable bit for the corresponding phase
in the interrupt enable register is set to Logic 1.
In addition to the enable bits, the zero-crossing timeout detec-
tion interrupt of each phase is enabled/disabled by setting the
ZXSEL bits of the MMODE register (Address 0Bh) to Logic 1
or Logic 0, respectively. When the zero-crossing timeout detection
is disabled by this method, the ZXTO flag of the corresponding
phase is switched on all the time.
Figure 15 shows the mechanism of the zero-crossing timeout
detection when the line voltage A stays at a fixed dc level for
more than CLKIN/384 � ZXTOUT seconds.
Figure 15. Zero-Crossing Timeout Detection
PERIOD MEASUREMENTThe ADE7754 also provides the period measurement of the
line voltage. The period is measured on the phase specified by
Bits 0 to 1 of the MMODE register. The period register is an
unsigned 15-bit register and is updated every period of the
selected phase. Bits 0 and 1 and Bits 4 to 6 of the MMODE
register select the phase for the period measurement; both
selections should indicate the same phase. The ZXSEL bits of
the MMODE register (Bits 4 to 6) enable the phases on which
the period measurement can be done. The PERDSEL bits
select the phase for period measurement within the phases
The resolution of this register is 2.4 µs/LSB when CLKIN =
10 MHz, which is 0.014% when the line frequency is 60 Hz.
When the line frequency is 60 Hz, the value of the period regis-
ter is approximately 6944d. The length of the register enables
the measurement of line frequencies as low as 12.7 Hz.
LINE VOLTAGE SAG DETECTIONThe ADE7754 can be programmed to detect when the absolute
value of the line voltage of any phase drops below a certain peak
value for a number of half cycles. All phases of the voltage chan-
nel are controlled simultaneously. This condition is illustrated
in Figure 16.
SAGLVL[7:0]
FULL SCALE
SAG INTERRUPT
FLAG (BIT 1 TO
BIT 3 OF STATUS
REGISTER)
READ
RSTATUS
REGISTER
VAP, VBP, OR VCPFigure 16.SAG Detection
Figure 16 shows a line voltage falling below a threshold set in
the SAG level register (SAGLVL[7:0]) for nine half cycles.
Since the SAG cycle register indicates a six half-cycle thresh-
old (SAGCYC[7:0]=06h), the SAG event is recorded at the
end of the sixth half-cycle by setting the SAG flag of the corre-
sponding phase in the interrupt status register (Bits 1 to 3 in the
interrupt status register). If the SAG enable bit is set to Logic 1
for this phase (Bits 1 to 3 in the interrupt enable register), the
IRQ logic output goes active low. See the Interrupts section. All
the phases are compared to the same parameters defined in the
SAGLVL and SAGCYC registers.
SAG Level SetThe content of the SAG level register (one byte) is compared to
the absolute value of the most significant byte output from the
voltage channel ADC. Thus, for example, the nominal maximum
code from the voltage channel ADC with a full-scale signal is
28F5h. See the Voltage Channel ADC section.
Therefore, writing 28h to the SAG level register puts the SAG
detection level at full scale and sets the SAG detection to its
most sensitive value.
Writing 00h puts the SAG detection level at 0. The detection of
a decrease of an input voltage is in this case hardly possible.
The detection is made when the content of the SAGLVL
register is greater than the incoming sample.
PEAK DETECTIONThe ADE7754 also can be programmed to detect when the
absolute value of the voltage or the current channel of one phase
ADE7754
VPEAK[7:0]
PKV INTERRUPT
FLAG (BIT C OF
STATUS REGISTER)
PKV RESET
LOW WHEN
RSTATUS
REGISTER
IS READ
READ
RSTATUS
REGISTER
VAP, VBP, OR VCPFigure 17.Peak Detection
Bits 2 and 3 of the measurement mode register define the phase
supporting the peak detection. Current and voltage of this phase
can be monitored at the same time. Figure 17 shows a line
voltage exceeding a threshold set in the voltage peak register
(VPEAK[7:0]). The voltage peak event is recorded by setting
the PKV flag in the interrupt status register. If the PKV enable
bit is set to Logic 1 in the interrupt enable register, the IRQ
logic output goes active low. See the Interrupts section.
Peak Level SetThe contents of the VPEAK and IPEAK registers compare to
the absolute value of the most significant byte output of the
selected voltage and current channels, respectively. Thus, for
example, the nominal maximum code from the current channel
ADC with a full-scale signal is 28F5C2h. See the Current
Channel Sampling section. Therefore, writing 28h to the
IPEAK register will put the current channel peak detection level
at full scale and set the current peak detection to its least sensi-
tive value. Writing 00h puts the current channel detection level at
zero. The detection is done when the content of the IPEAK
register is smaller than the incoming current channel sample.
TEMPERATURE MEASUREMENTThe ADE7754 also includes an on-chip temperature sensor. A
temperature measurement is made every 4/CLKIN seconds.
The output from the temperature sensing circuit is connected
to an ADC for digitizing. The resulting code is processed and
placed into the temperature register (TEMP[7:0]) which can
be read by the user and has an address of 08h. See the Serial
Interface section. The contents of the temperature register are
signed (twos complement) with a resolution of 4°C/LSB. The
temperature register produces a code of 00h when the ambient
temperature is approximately 129°C. The value of the register is
temperature register = (temperature (°C) – 129)/4. The tempera-
ture in the ADE7754 has an offset tolerance of approximately5°C. The error can be easily calibrated out by an MCU.
PHASE COMPENSATIONWhen the HPFs are disabled, the phase difference between the
current channel (IA, IB, and IC) and the voltage channel (VA,
VB, and VC) is zero from dc to 3.3 kHz. When the HPFs are
enabled, the current channels have a phase response as shown in
Figure 18a and 18b. The magnitude response of the filter is
Figure 18a. Phase Response of the HPF and
Phase Compensation (10 Hz to 1 kHz)
FREQUENCY (Hz)
PHASE (Degrees)
–0.002Figure 18b. Phase Response of the HPF and
Phase Compensation (40 Hz to 70 Hz)
FREQUENCY (Hz)
PHASE (Degrees)
–0.002Figure 18c. Gain Response of HPF and Phase Com-
pensation (Deviation of Gain as % of Gain at 54 Hz)
Despite being internally phase compensated, the ADE7754 must
work with transducers that may have inherent phase errors. For
are particularly noticeable at low power factors. The ADE7754
provides a means of digitally calibrating these small phase
errors. The ADE7754 allows a small time delay or time advance
to be introduced into the signal processing chain to compensate
for small phase errors. Because the compensation is in time, this
technique should be used only for small phase errors in the
range of 0.1° to 0.5°. Correcting large phase errors using a
time shift technique can introduce significant phase errors at
higher harmonics.
The phase calibration registers (APHCAL, BPHCAL, and
CPHCAL) are twos complement, 5-bit signed registers that
can vary the time delay in the voltage channel signal path from
–19.2 µs to +19.2 µs (CLKIN = 10 MHz). One LSB is equiva-
lent to 1.2 µs. With a line frequency of 50 Hz, this gives a
phase resolution of 0.022° at the fundamental (i.e., 360° �
1.2 µs � 50 Hz).
Figure 19 illustrates how the phase compensation is used to
remove a 0.091° phase lead in IA of the current channel caused
by an external transducer. In order to cancel the lead (0.091°)
in IA of the current channel, a phase lead must also be intro-
duced into VA of the voltage channel. The resolution of the
phase adjustment allows the introduction of a phase lead of
0.086°. The phase lead is achieved by introducing a time advance
into VA. A time advance of 4.8 µs is made by writing –4 (1Ch)
to the time delay block (APHCAL[4:0]), thus reducing the
amount of time delay by 4.8 µs. See the Calibration of a 3-Phase
Meter Based on the ADE7754 Application Note AN-624.
Figure 19. Phase Calibration
ROOT MEAN SQUARE MEASUREMENTRoot Mean Square (rms) is a fundamental measurement of the
magnitude of an ac signal. Its definition can be practical or
mathematical. Defined practically, the rms value assigned to an
ac signal is the amount of dc required to produce an equivalent
amount of heat in the same load. Mathematically the rms value
of a continuous signal f(t) is defined as
For time sampling signals, rms calculation involves squaring the
signal, taking the average, and obtaining the square root:(2)
The method used to calculate the rms value in the ADE7754 is
to low-pass filter the square of the input signal (LPF3) and take
the square root of the result.
With
then
The rms calculation is simultaneously processed on the six analog
input channels. Each result is available on separate registers.
Current RMS CalculationFigure 20 shows the detail of the signal processing chain for the
rms calculation on one of the phases of the current channel.
The current channel rms value is processed from the samples
used in the current channel waveform sampling mode. Note
that the APGAIN adjustment affects the result of the rms calcu-
lation. See the Current RMS Gain Adjust section. The current
rms values are stored in unsigned 24-bit registers (AIRMS,
BIRMS, and CIRMS). One LSB of the current rms register is
equivalent to 1 LSB of a current waveform sample. The update
rate of the current rms measurement is CLKIN/12. With the
specified full-scale analog input signal of 0.5 V, the ADC produces
an output code which is approximately ±2,684,354d. See the
Current Channel ADC section. The equivalent rms values of a
full-scale ac signal is 1,898,124d. With offset calibration, the
current rms measurement provided in the ADE7754 is accurate
within ±2% for signal input between full scale and full scale/100.
ADE7754pattern. Current rms measurements of Phase A are corrupted by
the signal on the Phase C current input, current rms measure-
ments of Phase B are corrupted by the signal on the Phase A
current input, and current rms measurements of Phase C are
corrupted by the signal on the Phase B current input. This
crosstalk is present only on the current rms measurements and
does not affect the regular active power measurements. The
level of the crosstalk is dependent on the level of the noise
source and the phase angle between the noise source and the
corrupted signal. The level of the crosstalk can be reduced by
writing 01F7h to the address 3Dh. This 16-bit register is
reserved for factory operation and should not be written to any
other value. When the current inputs are 120° out of phase and
the register 3Dh is set to 01F7h, the level of the current rms
crosstalk is below 2%.
Current RMS Gain AdjustThe active power gain registers (AAPGAIN[11:0], BAPGAIN,
and CAPGAIN) affect the active power and current rms values.
Calibrating the current rms measurements with these registers is
not recommended. The conversion of the current rms registers
values to amperes has to be done in an external microcontroller
with a specific ampere/LSB constant for each phase. See the Cali-
bration of a 3-Phase Meter Based on the ADE7754 Application
Note AN-624. Due to gain mismatches between phases, the cali-
bration of the ampere/LSB constant has to be done separately for
each phase. One-point calibration is sufficient for this calibration.
The active power gain registers ease the calibration of the active
energy calculation in MODE 1 and 2 of the WATMODE register.
If the APGAIN registers are used for active power calibration
(WATMOD bits in WATMode register = 1 or 2), the current
rms values are changed by the active power gain register value
as described in the expression
For example, when 7FFh is written to the active power gain
register, the ADC output is scaled up by 22.5%. Similarly, 800h
= –2047d (signed twos complement) and ADC output is scaled
by 29.3%. These two examples are illustrated in Figure 20.
Current RMS Offset CompensationThe ADE7754 incorporates a current rms offset compensation
for each phase (AIRMSOS, BIRMSOS, and CIRMSOS). These
are 12-bit twos complement signed registers that can be used to
remove offsets in the current rms calculations. An offset may
exist in the rms calculation due to input noises that are inte-
grated in the dc component of V2(t). The offset calibration will
allow the contents of the IRMS registers to be maintained at zero
when no current is being consumed.
n LSB of the current rms offset are equivalent to 32768 � n LSB
of the square of the current rms register. Assuming that the
maximum value from the current rms calculation is 1,898,124
decimal with full-scale ac inputs, then 1 LSB of the current rms
offset represents 0.0058% of measurement error at –40 dB
below full scale.
done close to full scale and the other at approximately full scale/
100. The current offset compensation can then be derived using
these measurements. See the Calibration of a 3-Phase Meter Based
on the ADE7754 Application Note AN-624.
Voltage RMS CalculationFigure 21 shows the details of the signal processing chain for the
rms calculation on one of the phases of the voltage channel. The
voltage channel rms value is processed from the samples used in
the voltage channel waveform sampling mode. The output of
the voltage channel ADC can be scaled by ±50% by changing
VGAIN registers to perform an overall apparent power calibra-
tion. See the Apparent Power Calculation section. The VGAIN
adjustment affects the rms calculation because it is done before
the rms signal processing. The voltage rms values are stored in
unsigned 24-bit registers (AVRMS, BVRMS, and CVRMS).
256 LSB of the voltage rms register is approximately equivalent
to one LSB of a voltage waveform sample. The update rate of
the voltage rms measurement is CLKIN/12.
With the specified full-scale ac analog input signal of 0.5 V, the
LPF1 produces an output code that is approximately ±10,217
decimal at 60 Hz. See the Voltage Channel ADC section. The
equivalent rms value of a full-scale ac signal is approximately
7,221d (1C35h), which gives a voltage rms value of 1,848,772d
(1C35C4h) in the VRMS register. With offset calibration, the
voltage rms measurement provided in the ADE7754 is accurate
within ±0.5% for signal input between full scale and full scale/20.
VOLTAGE
SIGNAL – v(t)
VOLTAGE
CHANNEL (rms)
0000h
1C35C4hE3CA3Ch
2A50A6h
E1AE2h
F1E51Eh
D5AF5Ah
AVGAIN[11:0]
00000h
4000h
C000h
28F5h
D70Ah
ADC OUTPUT
WORD RANGE
VRMSOS[11:0]+
AVGAIN[11:0]
VOLTAGE SIGNAL – V(t)Figure 21. Voltage RMS Signal Processing
Voltage RMS Gain AdjustThe voltage gain registers (AVGAIN[11:0], BVGAIN, and
CVGAIN) affect the apparent power and voltage rms values.
Calibrating the voltage rms measurements with these registers is
not recommended. The conversion of the voltage rms registers
values to volts has to be done in an external microcontroller
with a specific volt/LSB constant for each phase. See the Cali-
bration of a 3-Phase Meter Based on the ADE7754 Application
Note AN-624. Due to gain mismatches between phases, the cali-
bration of the volt/LSB constant has to be done separately for
If the VGAIN registers are used for apparent power calibration
(WATMOD bits in VAMODE register = 1 or 2), the voltage
rms values are changed by voltage gain register value as described
in the expression
For example, when 7FFh is written to the voltage gain register,
the ADC output is scaled up by +50%. 7FFh = 2047d, 2047/12 = 0.5. Similarly, 800h = –2047d (signed twos complement)
and ADC output is scaled by –50%. These two examples are
illustrated in Figure 21.
Voltage RMS Offset CompensationThe ADE7754 incorporates a voltage rms offset compensation
for each phase (AVRMSOS, BVRMSOS, and CVRMSOS).
These are 12-bit twos complement signed registers that can be
used to remove offsets in the voltage rms calculations. An offset
may exist in the rms calculation due to input noises and offsets
in the input samples. The offset calibration allows the contents
of the VRMS registers to be maintained at zero when no voltage
is applied.
n LSB of the voltage rms offset are equivalent to 64 � n LSB of
the voltage rms register. Assuming that the maximum value from
the voltage rms calculation is 1,898,124 decimal with full-scale
ac inputs, then 1 LSB of the voltage rms offset represents 0.07%
of measurement error at –26 dB below full scale.
where Vrmso is the rms measurement without offset correction.
The voltage rms offset compensation should be done by testing
the rms results at two non-zero input levels. One measurement
can be done close to full scale and the other at approximately
full scale/10. The voltage offset compensation can then be derived
from these measurements. See the Calibration of a 3-Phase
Meter Based on the ADE7754 Application Note AN-624.
ACTIVE POWER CALCULATIONElectrical power is defined as the rate of energy flow from source
to load. It is given by the product of the voltage and current
waveforms. The resulting waveform is called the instantaneous
power signal and it is equal to the rate of energy flow at every
instant of time. The unit of power is the watt or joules/sec. Equa-
tion 5 gives an expression for the instantaneous power signal in
an ac system.(3)(4)
where V = rms voltage and I = rms current.(5)
The average power over an integral number of line cycles (n) is
given by the expression in Equation 6.
where T is the line cycle period. P is referred to as the active or
real power. Note that the active power is equal to the dc compo-
nent of the instantaneous power signal p(t) in Equation 5 (i.e.,
VI). This is the relationship used to calculate active power in the
ADE7754 for each phase. The instantaneous power signal p(t)
is generated by multiplying the current and voltage signals in
each phase. The dc component of the instantaneous power signal
in each phase (A, B, and C) is then extracted by LPF2 (low-pass
filter) to obtain the active power information on each phase. This
process is illustrated in Figure 22. In a polyphase system, the total
electrical power is simply the sum of the real power in all active
phases. The solutions available to process the total active power
are discussed in the following section.
V. I.
D1B717h
00000h
1A36E2EhFigure 22. Active Power Calculation
Since LPF2 does not have an ideal brick wall frequency
response (see Figure 23), the active power signal has some
ripple due to the instantaneous power signal. This ripple is
sinusoidal and has a frequency equal to twice the line frequency.
Since the ripple is sinusoidal in nature, it is removed when the
active power signal is integrated to calculate the energy. See the
Energy Calculation section.
Figure 23. Frequency Response of the LPF Used
ADE7754Figure 24 shows the signal processing in each phase for the
active power in the ADE7754.
Figure 25 shows the maximum code (hexadecimal) output
range of the active power signal (after AWG). Note that the
output range changes depending on the contents of the active
power gain and watt gain registers. See the Current Channel
ADC section. The minimum output range is given when the
active power gain and watt gain registers contents are equal to
800h, and the maximum range is given by writing 7FFh to the
active power gain and watt gain registers. These can be used to
calibrate the active power (or energy) calculation in the
ADE7754 for each phase and the total active energy. See the
Total Active Power Calculation section.
0000000h
D1B717h2E48E9h
13A92A4h
68DB8Ch
972474h
EC56D5Ch
AAPGAIN[11:0] OR AWGAIN[11:0]
ACTIVE
POWER
CURRENT CHANNEL � 0.5V/GAIN1
VOLTAGE CHANNEL � 0.5V/GAIN2Figure 25. Active Power Calculation Output Range
Power Offset CalibrationThe ADE7754 also incorporates an active offset register on each
phase (AAPOS, BAPOS, and CAPOS). These are signed twos
complement 12-bit registers that can be used to remove offsets
in the active power calculations. An offset may exist in the
power calculation because of crosstalk between channels on the
PCB or in the IC itself. The offset calibration allows the con-
tents of the active power register to be maintained at zero when
no power is being consumed.
One LSB in the active power offset register is equivalent to one
LSB in the 28-bit energy bus displayed in Figure 24. Each
time power is added to the internal active energy register, the
content of the active power offset register is added. See the
Total Active Power Calculation section. Assuming the average
value from LPF2 is 8637BCh (8,796,092d) with full ac scale
Figure 24. Active Power Signal Processing
Reverse Power InformationThe ADE7754 detects when the current and voltage channels
of any of the three phase inputs have a phase difference greater
than 90° (i.e., |�A| or |�B| or |�C| > 90°). This mechanism
can detect wrong connection of the meter or generation of
active energy.
The reverse power information is available for Phase A, Phase B,
and Phase C, respectively, by reading Bits 12 to 14 of the CFNUM
register. See Table XI. The state of these bits represents the
sign of the active power of the corresponding phase. Logic 1
corresponds to negative active power.
The AENERGY phase selection bits (WATSEL bits of the
WATMode register) enable the negative power detection per
phase. If Phase A is enabled in the AENERGY accumulation,
Bit 5 of WATMode register sets to Logic 1 and the negative
power detection for Phase A—Bit 12 of CFNUM register—
indicates the direction of the active energy. If Phase A is
disabled in the AENERGY register, the negative power bit for
Phase A is set to Logic 0.
TOTAL ACTIVE POWER CALCULATIONThe sum of the active powers coming from each phase provides
the total active power consumption. Different combinations of
the three phases can be selected in the sum by setting Bits 7 and
6 of the WATMode register (mnemonic WATMOD[1:0]).
Figure 26 demonstrates the calculation of the total active power,
which depends on the configuration of the WATMOD bits in
the WATMode register. Each term of the formula can be disabled
or enabled by setting WATSEL bits respectively to Logic 0 or
Logic 1 in the WATMode register. The different configurations
are described in Table I.
Table I. Total Active Power Calculation
Figure 26. Total Active Power Consumption Calculation
For example, for WATMOD = 1, when all the gains and offsets
corrections are taken into consideration, the formula that is
used to process the active power is
Depending on the polyphase meter service, an appropriate for-
mula should be chosen to calculate the active power. The
American ANSI C12.10 standard defines the different configu-
rations of the meter. Table II describes which mode should be
chosen for each configuration.
Table II. Meter Form ConfigurationDifferent gain calibration parameters are offered in the ADE7754
to cover the calibration of the meter in different configurations.
Note that in Mode 0, the APGAIN and WGAIN registers have
the same effect on the end result. In this case, APGAIN regis-
ters should be set at their default value and the gain adjustment
ENERGY CALCULATIONAs stated earlier, power is defined as the rate of energy flow.
This relationship can be expressed mathematically as(7)
where P = power and E = energy.
Conversely energy is given as the integral of power.(8)
The ADE7754 achieves the integration of the active power
signal by continuously accumulating the active power signal in
an internal non readable 54-bit energy register. The active
energy register (AENERGY[23:0]) represents the upper 24 bits
of this internal register. This discrete time accumulation or
summation is equivalent to integration in continuous time.
Equation 9 expresses the relationship(9)
where n is the discrete time sample number and T is the
sample period.
ADE7754The discrete time sample period (T) for the accumulation
register in the ADE7754 is 0.4 µs (4/10 MHz). In addition to
calculating the energy, this integration removes any sinusoidal
component that may be in the active power signal. Figure 27
shows a graphical representation of this discrete time integration
or accumulation. The active power signal is continuously added
to the internal energy register. Because this addition is a signed
addition, negative energy will be subtracted from the active
energy contents.
TOTAL ACTIVE POWER
00000h
26667h
TOTAL ACTIVE POWER IS
ACTIVE POWER
SIGNAL (P)
AENERGY[23:0]0+Figure 27.Active Energy Calculation
The 54-bit value of the internal energy register is divided by
WDIV. If the value in the WDIV register is 0, then the internal
active energy register is divided by 1. WDIV is an 8-bit unsigned
register. The upper 24-bits of the result of the division are then
available in the 24-bit active energy register. The AENERGY
and RAENERGY registers read the same internal active energy
register. They differ by the state in which they are leaving the
internal active energy register after a read. Two operations are
held when reading the RAENERGY register: read and reset to 0
the internal active energy register. Only one operation is held
when reading the AENERGY register: read the internal active
energy register.
Figure 28 shows the energy accumulation for full-scale (sinusoidal)
signals on the analog inputs. The three displayed curves illustrate
the minimum time it takes the energy register to roll over when
the individual watt gain registers contents are all equal to 3FFh,
000h, and 800h. The watt gain registers are used to carry out a
power calibration in the ADE7754. As shown, the fastest
integration time occurs when the watt gain registers are set to
maximum full scale, i.e., 3FFh.
00,0000h
7F,FFFFh
80,0000h
3F,FFFFh
40,0000h
AENERGY[23:0]
TIME (sec)Figure 28. Energy Register Roll-Over Time for Full-
Scale Power (Minimum and Maximum Power Gain)
Note that the active energy register contents roll over to full-
scale negative (80,0000h) and continue increasing in value
when the power or energy flow is positive. See Figure 28.
Conversely, if the power is negative, the energy register would
underflow to full scale positive (7F,FFFFh) and continue
decreasing in value.
By using the interrupt enable register, the ADE7754 can be
configured to issue an interrupt (IRQ) when the active energy
register is half full (positive or negative).
Integration Times Under Steady LoadAs mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 0.4 µs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
watt gain registers set to 000h, the average word value from
each LPF2 is D1B717h. See Figures 22 and 24. The maximum
value that can be stored in the active energy register before it
overflows is 223 – 1 or 7F,FFFFh. As the average word value is
added to the internal register, which can store 253 – 1 or
1F,FFFF,FFFF,FFFFh before it overflows, the integration time
under these conditions with WDIV = 0 is calculated as follows:
When WDIV is set to a value different from 0, the integration
time varies as shown in Equation 10.(10)
The WDIV register can be used to increase the time before the
active energy register overflows, thereby reducing the communi-
cation needs with the ADE7754.
Energy to Frequency ConversionThe ADE7754 also provides energy-to-frequency conversion
for calibration purposes. After initial calibration at manufac-
ture, the manufacturer or the customer will often verify the
energy meter calibration. One convenient way to verify the
meter calibration is for the manufacturer to provide an output
frequency proportional to the energy or active power under
steady load conditions. This output frequency can provide a
simple single-wire, optically isolated interface to external cali-
bration equipment. Figure 29 illustrates the energy to frequency
conversion in the ADE7754.
ACTIVE POWER
PHASE B
ACTIVE POWER
PHASE A
ACTIVE POWER
PHASE C�
CF
CFNUM[11:0]0
CFDEN[11:0]0+
TOTAL ACTIVE
POWER0Figure 29.ADE7754 Energy to Frequency Conversion
A digital to frequency converter (DFC) is used to generate the
CF pulsed output. The DFC generates a pulse each time one
LSB in the active energy register is accumulated. An output
pulse is generated when CFDEN/CFNUM pulses are generated
at the DFC output. Under steady load conditions, the output
frequency is proportional to the active power. The maximum
output frequency (CFNUM = 00h and CFDEN = 00h) with
full scale ac signals on the three phases (i.e., current channel
and voltage channel is approximately 96 kHz).
The ADE7754 incorporates two registers to set the frequency of
CF (CFNUM[11:0] and CFDEN[11:0]). These are unsigned
12-bit registers that can be used to adjust the frequency of CF
to a wide range of values. These frequency scaling registers are
12-bit registers that can scale the output frequency by 1/212 to 1
with a step of 1/212.
If the value 0 is written to any of these registers, the value 1
would be applied to the register. The ratio CFNUM/CFDEN
should be smaller than 1 to ensure proper operation. If the ratio
of the registers CFNUM/CFDEN is greater than 1, the CF
frequency can no longer be guaranteed to be a consistent value.
For example, if the output frequency is 18.744 kHz and the
contents of CFDEN are zero (000h), then the output frequency
can be set to 6.103 Hz by writing BFFh to the CFDEN register.
The output frequency will have a slight ripple at a frequency
equal to twice the line frequency because of imperfect filtering
of the instantaneous power signal used to generate the active
power signal. See the Active Power Calculation section. Equa-
tion 5 gives an expression for the instantaneous power signal.
This is filtered by LPF2, which has a magnitude response given
by Equation 11.(11)
The active power signal (output of the LPF2) can be rewritten as
(12)
where fl is the line frequency (e.g., 60 Hz).
From Equation 8
(13)
Equation 13 shows that there is a small ripple in the energy
calculation due to a sin(2�t) component. This is graphically
displayed in Figure 30. The ripple becomes larger as a percentage
of the frequency at larger loads and higher output frequencies.
Choosing a lower output frequency at CF for calibration can
significantly reduce the ripple. Also, averaging the output fre-
quency by using a longer gate time for the counter achieves the
same results.
Figure 30. Output Frequency Ripple
No Load ThresholdThe ADE7754 includes a selectable “no load threshold” or
“startup current” feature that eliminates any creep effects in the
active energy measurement of the meter. When enabled, this
function is independently applied on each phase’s active power
calculation. This mode is selected by default and can be disabled
ADE7754by setting to Logic 1 Bit 3 of the gain register (Address 18h). See
Table X. Any load generating an active power amplitude lower
than the minimum amplitude specified will not be taken into
account when accumulating the active power from this phase.
The minimum instantaneous active power allowed in this mode
is 0.005% of the full-scale amplitude. Because the maximum
active power value is 13,743,895d with full-scale analog input,
the no-load threshold is 687d. For example, an energy meter
with maximum inputs of 220 V and 40 A and Ib = 10 A, the
maximum instantaneous active power is 3,435,974d, assuming
that both inputs represent half of the analog input full scale. As
the no-load threshold represents 687d, the start-up current
represents 8 mA or 0.08% of Ib.
Mode Selection of the Sum of the Three Active EnergiesThe ADE7754 can be configured to execute the arithmetic sum
of the three active energies, Wh = Wh�A + Wh�B + Wh�C, or the
sum of the absolute value of these energies, Wh = |Wh�A| +
|Wh�B| + |Wh�C|. The selection between the two modes can
be made by setting Bit 2 of the gain register (Address 18h). See
Table X. Logic high and logic low of this bit correspond to the
sum of absolute values and the arithmetic sum, respectively.
This selection affects the active energy accumulation in the
AENERGY, RAENERGY, and LAENERGY registers as well
as the CF frequency output.
When the sum of the absolute values is selected, the active
energy from each phase is always counted positive in the total
active energy. It is particularly useful in a 3-phase, 4-wire instal-
lation where the sign of the active power should always be the
same. If the meter is misconnected to the power lines (e.g., CT
is connected in the wrong direction), the total active energy
recorded without this solution can be reduced by two thirds. The
sum of the absolute values ensures that the active energy recorded
represents the actual active energy delivered. In this mode, the
reverse power information available in the CFNUM register is
still detecting when negative active power is present on any of
the three phase inputs.
LINE ENERGY ACCUMULATIONThe ADE7754 is designed with a special energy accumulation
mode that simplifies the calibration process. By using the on-
chip zero-crossing detection, the ADE7754 accumulates the
active power signal in the LAENERGY register for an integer
number of half cycles, as shown in Figure 31. The line active
energy accumulation mode is always active.
Using this mode with only one phase selected is recommended.
If several phases are selected, the amount accumulated may be
smaller than it should be.
Each one of three phases zero-crossing detection can contribute
to the accumulation of the half line cycles. Phase A, B, and C
zero crossings, respectively, are taken into account when count-
ing the number of half line cycles by setting Bits 4 to 6 of the
MMODE register to Logic 1. Selecting phases for the zero-
crossing counting also has the effect of enabling the zero-cross-
ing detection, zero-crossing timeout and period measurement
for the corresponding phase as described in the zero-crossing
detection paragraph.
The number of half line cycles is specified in the LINCYC
register. LINCYC is an unsigned 16-bit register. The ADE7754
can accumulate active power for up to 65535 combined half
cycles. Because the active power is integrated on an integer
number of line cycles, the sinusoidal component is reduced to
zero. This eliminates any ripple in the energy calculation. Energy
is calculated more accurately because of this precise timing
control. At the end of an energy calibration cycle, the LINCYC
flag in the interrupt status register is set. If the LINCYC enable
bit in the interrupt enable register is set to Logic 1, the IRQ
output also goes active low.
Figure 31.Active Energy Calibration
