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ADE7752AR
Three Phase Energy Metering IC with Pulse Output
REV.PrB 08/01
PRELIMINARY TECHNICAL DATA
Three Phase Energy Metering IC
with Pulse Output
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High Accuracy, Supports 50 Hz/60 Hz IEC 687/1036
Less than 0.1% Error Over a Dynamic Range of
500 to 1
Compatible with 3-phase/3-wire and 3-phase/4-wire
configurations
The ADE7752 Supplies Average Real Power on the
Frequency Outputs F1 and F2
The High Frequency Output CF Is Intended for
Calibration and Supplies Instantaneous Real Power
The Logic Output REVP indicates a Potential Miswiring or
Negative Power for each phase
Direct Drive for Electromechanical Counters and
Two Phase Stepper Motors (F1 and F2)
Proprietary ADCs and DSP Provide High Accuracy over
Large Variations in Environmental Conditions and
Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V ± 8% (30 ppm/8C Typical)
with External Overdrive Capability
Single 5 V Supply, Low Power (15 mW Typical)
Low Cost CMOS Process*Patents pending
GENERAL DESCRIPTIONThe ADE7752 is a high accuracy three phase electrical
energy measurement IC. The part specifications surpass the
accuracy requirements as quoted in the IEC1036 standard.
The only analog circuitry used in the ADE7752 is in the
ADCs and reference circuit. All other signal processing (e.g.,
multiplication, filtering and summation) is carried out in the
digital domain. This approach provides superior stability and
accuracy over extremes in environmental conditions and over
time.
The ADE7752 supplies average real power information on
the low frequency outputs F1 and F2. These logic outputs
may be used to directly drive an electromechanical counter or
interface with an MCU. The CF logic output gives instan-
taneous real power information. This output is intended to be
used for calibration purposes, or as interface with an MCU.
The ADE7752 includes a power supply monitoring circuit
on the AVDD supply pin. The ADE7752 will remain inactive
until the supply voltage on VDD reaches 4V. If the supply falls
below 4V, the ADE7752 will also be reset and no pulses will
be issued on F1, F2 and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched. An internal no-load
threshold ensures that the ADE7752 does not exhibit any
creep when there is no load.
The ADE7752 is available in 24-lead SOIC packages.
PRELIMINARY TECHNICAL DATA
ADE7752–SPECIFICATIONS
(VDD = 5 V � 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10MHz,
TMIN to TMAX = –40�C to +85�C)Output Frequency Variation (CF)
LOGIC INPUTS
LOGIC OUTPUTS
NOTES
PRELIMINARY TECHNICAL DATA
ADE7752
TIMING CHARACTERISTICS1, 2NOTES
1Sample tested during initial release and after any redesign or process change that may affect this parameter.
2See Figure 1.
3The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs Section.
4The CF pulse is always 1 µs in the high frequency mode. See Frequency Outputs section and Table IV.
Specifications subject to change without notice.
(VDD = 5 V � 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz,
TMIN to TMAX = –40�C to +85�C)Figure 1.Timing Diagram for Frequency Outputs
PRELIMINARY TECHNICAL DATA
ADE7752
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND
VAP, VBP, VCP, VN, IAP, IAN, . . . . . . . . . . . . . . . . . .
IBP, IBN, ICP and ICN . . . . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADE7752 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
24-Lead SOIC, Power Dissipation . . . . . . . . . TBD mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . .250 °C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
TERMINOLOGY
MEASUREMENT ERRORThe error associated with the energy measurement made by
the ADE7752 is defined by the following formula:100EnergyTrue–ADE7752thebyRegisteredEnergy×=EnergyTrueErrorPercentage
PHASE ERROR BETWEEN CHANNELSThe HPF (High Pass Filter) in the current channel has a
phase lead response. To offset this phase response and
equalize the phase response between channels a phase correc-
tion network is also placed in the current channel. The phase
correction network ensures a phase match between the
current channels and voltage channels to within ±0.1° over a
range of 45Hz to 65Hz and ±0.2° over a range 40Hz to 1kHz.
This phase mismatch between the voltage and the current
channels can be further reduced with the phase calibration
register in each phase.
See Figures 18 and 19.
POWER SUPPLY REJECTIONThis quantifies the ADE7752 measurement error as a per-
centage of reading when the power supplies are varied.
For the ac PSR measurement a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then
introduced onto the supplies and a second reading obtained
under the same input signal levels. Any error introduced is
expressed as a percentage of reading—see Measurement Error
definition.
For the dc PSR measurement a reading at nominal supplies
(5 V) is taken. The supply is then varied ±5% and a second
reading is obtained with the same input signal levels. Any
error introduced is again expressed as a percentage of
ADC OFFSET ERRORThis refers to the dc offset associated with the analog inputs
to the ADCs. It means that with the analog inputs connected
to AGND the ADCs still see an analog input signal of 1 mV
to 10mV, depending on gain setting. However, as the HPF
is always present, the offset is removed from the current
channel and the power calculation is not affected by this
offset.
GAIN ERRORThe gain error of the ADE7752 is defined as the difference
between the measured output frequency (minus the offset) and
the ideal output frequency. The difference is expressed as a
percentage of the ideal frequency. The ideal frequency is
obtained from the ADE7752 transfer function—see Transfer
Function section.
PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTION
PRELIMINARY TECHNICAL DATA
ADE7752
PIN CONFIGURATIONSOIC Package
