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ADE7752
Polyphase Energy Metering IC with Pulse Output
REV.0
Polyphase Energy Metering IC
with Pulse Output
FUNCTIONAL BLOCK DIAGRAM
CLKOUT
CLKIN
DGNDS1F1F2S0SCFNEGP
REFIN/OUTAGND
IBP
IBN
VBP
ICP
ICN
VCP
IAP
IAN
VAP
VDD12418212223241
ABS
FEATURES
High Accuracy, Supports 50 Hz/60 Hz IEC 687/61036
Less than 0.1% Error over a Dynamic Range of
500 to 1
Compatible with 3-Phase/3-Wire Delta and 3-Phase/
4-Wire Wye Configurations
ADE7752 Supplies Average Real Power on the
Frequency Outputs F1 and F2
High Frequency Output CF Is Intended for Calibration
and Supplies Instantaneous Real Power
Logic Output NEGP Indicates a Potential Miswiring or
Negative Power for Each Phase
Direct Drive for Electromechanical Counters and
2-Phase Stepper Motors (F1 and F2)
Proprietary ADCs and DSP Provide High Accuracy over
Large Variations in Environmental Conditions
and Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.4 V � 8% (20 ppm/�C, Typical)
with External Overdrive Capability
Single 5 V Supply, Low Power (60 mW, Typical)
Low Cost CMOS Process
GENERAL DESCRIPTIONThe ADE7752 is a high accuracy polyphase electrical energy
measurement IC. The part specifications surpass the accuracy
requirements as quoted in the IEC61036 standard. The only
analog circuitry used in the ADE7752 is in the ADCs and refer-
ence circuit. All other signal processing (e.g., multiplication,
filtering, and summation) is carried out in the digital domain.
This approach provides superior stability and accuracy over
extremes in environmental conditions and over time.
The ADE7752 supplies average real power information on the
low frequency outputs F1 and F2. These logic outputs may be
used to directly drive an electromechanical counter or interface
with an MCU. The CF logic output gives instantaneous real
power information. This output is intended to be used for cali-
bration purposes.
The ADE7752 includes a power supply monitoring circuit on
the VDD supply pin. The ADE7752 will remain inactive until the
supply voltage on VDD reaches 4V. If the supply falls below 4V,
the ADE7752 will also be reset and no pulses will be issued on
F1, F2, and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched. An internal no-load thresh-
old ensures that the ADE7752 does not exhibit any creep when
there is no load.
The ADE7752 is available in 24-lead SOIC packages.
*Patent pending.
ADE7752–SPECIFICATIONS
(VDD = 5 V � 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz, TMIN to
TMAX = –40�C to +85�C.)REFERENCE INPUT
POWER SUPPLY
NOTESSee Terminology section for explanation of specifications.See plots in Typical Performance Characteristics graphs.
ADE7752
TIMING CHARACTERISTICS1, 2Figure 1.Timing Diagram for Frequency Outputs
NOTESSample tested during initial release and after any redesign or process change that may affect this parameter.See Figure 1.The pulsewidths of F1, F2, and CF are not fixed for higher output frequencies. See Frequency Outputs section.CF is not synchronous to F1 or F2 frequency outputs.The CF pulse is always 1 µs in the high frequency mode. See Frequency Outputs section and Table IV.
Specifications subject to change without notice.
(VDD = 5 V � 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz,
TMIN to TMAX = –40�C to +85�C)
ADE7752
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C, unless otherwise noted.)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
Analog Input Voltage to AGND
VAP, VBP, VCP, VN, IAP, IAN, IBP, IBN, ICP, and ICN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V to +6 V
Reference Input Voltage to AGND . . . .–0.3 V to VDD + 0.3V
Digital Input Voltage to DGND . . . . . .–0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
24-Lead SOIC, Power Dissipation . . . . . . . . . . . . . . . 88 mW
�JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .250°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
TERMINOLOGY
Measurement ErrorThe error associated with the energy measurement made by the
ADE7752 is defined by the following formula:
Error between ChannelsThe HPF (high-pass filter) in the current channel has a phase
lead response. To offset this phase response and equalize the
phase response between channels, a phase correction network is
also placed in the current channel. The phase correction net-
work ensures a phase match between the current channels and
voltage channels to within ±0.1° over a range of 45 Hz to 65 Hz
and ±0.2° over a range of 40 Hz to 1 kHz. See Figures 12 and 13.
Power Supply RejectionThis quantifies the ADE7752 measurement error as a percentage
of reading when the power supplies are varied.
For the ac PSR measurement, a reading at nominal supply (5 V) is
taken. A 200 mV rms/100 Hz signal is then introduced onto the
supply and a second reading is obtained under the same input
signal levels. Any error introduced is expressed as a percentage of
reading. See Measurement Error, above.
For the dc PSR measurement, a reading at nominal supplies (5 V)
is taken. The supply is then varied ±5% and a second reading is
obtained with the same input signal levels. Any error introduced is
again expressed as a percentage of reading.
ADC Offset ErrorThis refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND, the ADCs still see an analog input signal offset.
However, as the HPF is always present, the offset is removed
from the current channel and the power calculation is not
affected by this offset.
Gain ErrorThe gain error of the ADE7752 is defined as the difference
between the measured output frequency (minus the offset) and the
ideal output frequency. The difference is expressed as a percentage
of the ideal frequency. The ideal frequency is obtained from the
ADE7752 transfer function. See the Transfer Function section.
PIN CONFIGURATION
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADE7752 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ORDERING GUIDE*RW = Small Outline - Wide Body Package in Tubes
PIN FUNCTION DESCRIPTIONADE7752–Typical Performance CharacteristicsTPC 1.Error as a Percent of Reading with Internal
Reference (Wye Connection)
TPC 2.Error as a Percent of Reading over Power
Factor with Internal Reference (Wye Connection)
CURRENT CHANNEL – % of Full Scale
ERROR – % of ReadingTPC 3.Error as a Percent of Reading over Power
Factor with External Reference (Wye Connection)
CURRENT CHANNEL – % of Full Scale
ERROR – % of ReadingTPC 4.Error as a Percent of Reading over Temperature
with Internal Reference (Wye Connection)
TPC 5.Error as a Percent of Reading over Power
Factor with Internal Reference (Delta Connection)
TPC 6.Error as a Percent of Reading over Temperature
with External Reference (Wye Connection)
TPC 7.Error as a Percent of Reading over Frequency
with an Internal Reference (Wye Connection)
TPC 8.Error as a Percent of Reading over Power
Supply with External Reference (Wye Connection)
TPC 9.Channel 1 Offset Distribution
TPC 10.Error as a Percent of Reading over Power
Supply with Internal Reference (Wye Connection)
TEST CIRCUIT
ADE7752
THEORY OF OPERATIONThe six voltage signals from the current and voltage transducers
are digitized with ADCs. These ADCs are 16-bit second order
sigma-delta with an oversampling rate of 833kHz. This analog
input structure greatly simplifies transducer interface by provid-
ing a wide dynamic range for direct connection to the transducer
and also simplifying the antialiasing filter design. A high-pass
filter in the current channel removes the dc component from the
current signal. This eliminates any inaccuracies in the real power
calculation due to offsets in the voltage or current signals—see
HPF and Offset Effects section.
The real power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals of each
phase. In order to extract the real power component (i.e., the dc
component), the instantaneous power signal is low-pass filtered
on each phase. Figure 2 illustrates the inst antaneous real power
signal and shows how the real power information can be extracted
by low-pass filtering the instantaneous power signal. This
method is used to extract the real power information on each
phase of the polyphase system. The total real power information
is then obtained by adding the individual phase real power. This
scheme correctly calculates real power for nonsinusoidal current
and voltage waveforms at all power factors. All signal processing
is carried out in the digital domain for superior stability over
temperature and time.
The low frequency output of the ADE7752 is generated by
accumulating the total real power information. This low fre-
quency inherently means a long accumulation time between
output pulses. The output frequency is therefore proportional to
the average real power. This average real power information
can, in turn, be accumulated (e.g., by a counter) to generate
real energy information. Because of its high output frequency
and therefore, shorter integration time, the CF output is pro-
portional to the instantaneous real power. This pulse is useful
for system calibration purposes that would take place under
steady load conditions.
Power Factor ConsiderationsThe method used to extract the real power information from the
individual instantaneous power signal (i.e., by low-pass filtering)
is still valid when the voltage and current signals of each phase
are not in phase. Figure 3 displays the unity power factor condi-
tion and a DPF (displacement power factor) = 0.5, i.e., current
signal lagging the voltage by 60°, for one phase of the polyphase.
If we assume the voltage and current waveforms are sinusoidal,
the real power component of the instantaneous power signal
(i.e., the dc term) is given by:
Figure 2.Signal Processing Block Diagram
