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ADVFC32KN ,Voltage-to-Frequency and Frequency-to-Voltage Converterspecifications are guaranteed,although only those shown in boldface are tested on all production un ..
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ADE3700SX-ADE3700X-ADE3700XT
Analog LCD Display Engine for XGA and SXGA Resolutions
TARGET SPECIFICATION
ADE3700Analog LCD Display Engine for XGA and SXGA Resolutions
Feature Overview Programmable Context Sensitive™ Scaling High-quality Up-scaling and Down-scaling Integrated 9-bit ADC/PLL IQSync™ AutoSetup Integrated programmable Timing Controller Integrated Pattern Generator Perfect Picture™ Technology sRGB 3D Color Warp Integrated OSD Advanced EMI reduction features Framelock operation with Safety Mode™ Serial I²C interface Low power 0.18 μm process technology
General DescriptionADE3700 devices are a family of highly-integrated
display engine ICs, enabling the most advanced,
flexible, and cost-effective system-on-chip solutions
for analog-only input LCD display applications.
The ADE3700 covers the full range of XGA and
SXGA analog-only applications including Smart
Panel designs.
The ADE3700 family is pin-to-pin compatible and
comes in a low-cost, 128-pin LQFP package.
ADE3700 devices use the same software platform
and are backward-compatible with the previous
generation of ADE3xxx Scaling Engines.
LCD Scaler Product Selector Analog
Video
LCD
Panel
RGB
Signals
To TFT
ADE3700
Third Generation Context Sensitive™ Scaler Sharper text with Edge Enhancement RAM based coefficients for unique
customization 5:1 Upscale and 2:1 Downscale Independent X - Y axis zoom and shrink
Analog RGB input 140 MHz 9-bit ADC Ultra low jitter digital Line Lock PLL Composite Sync and Sync on Green support
IQsync™ AutoSetup AutoSetup configures phase, clock, level, and
position Supports continuous calibration for reduced
user intervention Automatically detects activity on input Compatible with all standard VESA and GTF
modes
Perfect Picture™ Technology Programmable 3D Color Warp Digital brightness, contrast, hue, and
saturation gamma controls for all inputs Simple white point control Compatible with sRGB standard Video & Picture windowing Supports up to 7 different windows Independent window controls for contrast
brightness, saturation, hue and gamma
Perfect Color™ Technology True color dithering for 12- and 18-bit panels Temporal and spatial dithering 30-bit programmable gamma table
OSD Engine 256 RAM based 12x18 characters 1- and 4-bit per pixel color characters Bordering, shadowing, transparency, fade-in,
and fade-out effects Supports font rotation Up to 4 sub windows 32-entry TrueColor LUT
Programmable Timing Controller (TCON) Highly programmable support for XGA
SmartPanels Dual-function LVCMOS and RSDS outputs Supports 18-, 24-, 36-, and 48-bit RSDS
outputs Advanced Flicker Detection and Reduction 12 programmable timing signals for row/
column control Wide range of drivers & TCON compatibility Simulation tools for easy programming Supports complex polarity generation for IPS
panels
Advanced EMI Reduction Features Flexible data inversion / transition
minimization, single, dual, and separate Per pin delay, 0 to 6ns in 0.4ns increments Adaptive Slew Rate control outputs Differential clock Spread spectrum -programmable digital FM
modulation of the output clock with no
external components
Output Format Supports resolutions up to SXGA @ 75Hz Supports 6- or 8-bit Panels Supports double or single pixel wide formats
ADE3700 able of Contents
Chapter 1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51.1 Pin Descriptions ..................................................................................................................7
Chapter 2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112.1 Global Control ....................................................................................................................11
2.2 FM Frequency Synthesizer ................................................................................................16
2.3 Analog-to-Digital Converter (ADC) .....................................................................................17
2.4 Line Lock PLL ....................................................................................................................18
2.5 Sync Retiming (SRT) .........................................................................................................23
2.6 Sync Measurement ............................................................................................................25
2.7 Sync Multiplexer (SMUX) ...................................................................................................32
2.7.1 Functional Description .......................................................................................................................33
2.7.2 Example .............................................................................................................................................34
2.8 Data Multiplexer .................................................................................................................37
2.9 Data Measurement (DMEAS) ............................................................................................38
2.9.1 Edge Intensity ....................................................................................................................................38
2.9.2 Pixel Sum ...........................................................................................................................................38
2.9.3 Minimum/Maximum Pixel ...................................................................................................................38
2.9.4 Pixel Cumulative Distribution (PCD) ..................................................................................................39
2.9.5 Horizontal Position .............................................................................................................................39
2.9.6 Vertical Position .................................................................................................................................39
2.9.7 DE Size ..............................................................................................................................................40
2.10 LCD Scaler .........................................................................................................................42
2.11 Output Sequencer ..............................................................................................................45
2.11.1 Frame Synchronization ......................................................................................................................45
2.11.2 Timing Unit .........................................................................................................................................45
2.11.3 Signal Generation ..............................................................................................................................45
2.12 Timing Controller (TCON) ..................................................................................................48
2.13 Pattern Generator ..............................................................................................................54
2.13.1 Screen Split .......................................................................................................................................54
2.13.2 Pattern Engine ...................................................................................................................................55
2.13.3 Borders ..............................................................................................................................................55
2.14 sRGB ..................................................................................................................................60
2.14.1 Parametric Gamma, Digital Contrast / Brightness on Multiple Windows ...........................................60
2.14.2 Color Space Warp ..............................................................................................................................60
2.15 On-Screen Display (OSD) ..................................................................................................62
2.15.1 OSD Access via I2C ..........................................................................................................................62
ADE37002.17 Gamma ...............................................................................................................................70
2.18 APC ....................................................................................................................................71
2.19 Output Multiplexer ..............................................................................................................72
2.19.1 Sub Block Function ...........................................................................................................................73
2.19.2 RSDS ................................................................................................................................................76
2.19.3 Per Pin Delay ....................................................................................................................................77
2.20 Pulse Width Modulation (PWM) ..........................................................................................80
2.21 DFT Block ...........................................................................................................................81
2.22 I²C RAM Addresses ...........................................................................................................83
Chapter 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843.1 Absolute Maximum Ratings ................................................................................................84
3.2 Power Consumption Matrices .............................................................................................84
3.3 Nominal Operating Conditions ............................................................................................85
3.4 Preliminary Thermal Data ...................................................................................................85
3.5 Preliminary DC Specifications ............................................................................................85
3.5.1 LVTTL 5 Volt Tolerant Inputs With Hysteresis ...................................................................................85
3.5.2 LVTTL 5 Volt Tolerant Inputs .............................................................................................................85
3.5.3 LVTTL 5 Volt Tolerant I/O With Hysteresis ........................................................................................86
3.5.4 LVTTL Outputs ..................................................................................................................................86
3.6 Preliminary AC Specifications ...........................................................................................86
Chapter 4 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Chapter 5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ADE3700 General InformationThe ADE3700 family of devices is capable of implementing all of the advanced features of today’s
LCD monitor products. For maximum flexibility, an external microcontroller (MCU) is used for
controlling the ADE3700 and other monitor functions.
The ADE3700 architecture unburdens the MCU from all data-intensive pixel manipulations,
providing an optimal blend of features and code customizing without incurring the cost of a 16-bit
processor or memory. The key interactions between the monitor MCU and the ADE3700 can be
broken down into the features shown in the table below.
Figure 1: ADE3700 Block Diagram
Table 1: ADE3700 Features (Sheet 1 of 2)
ADE3700
Table 1: ADE3700 Features (Sheet 2 of 2)
ADE3700 Pin Descriptions
1.1 Pin Descriptions
Table 2: Pinout (Sheet 1 of 4)
Pin Descriptions ADE3700
Table 2: Pinout (Sheet 2 of 4)
ADE3700 Pin Descriptions
Table 2: Pinout (Sheet 3 of 4)
Pin Descriptions ADE3700
Table 2: Pinout (Sheet 4 of 4)
ADE3700 Global Control Functional Description
2.1 Global Control The global control block is responsible for: selecting clock sources power control I²C control SCLK frequency synthesizer control block by block synchronous reset generation
The global control block runs on the XCLK clock domain which is required to be active for
programming. The clock domains of all other blocks are set in the Global Control Block. For I²C
access, the requested block must be driven with a valid clock frequency greater than 10 MHz. Clock
domains are shown in Figure2.
To program the SCLK frequency synthesizer to a desired frequency (f OUT , in MHz), the following
equations apply.
Figure 2: Global Control Block Diagram
Table 3: SCLK Frequency Synthesizer Programmable Values (Sheet 1 of 2)
Global Control ADE3700MD = INT(f XCLK x (2 (6 + NDIV - SDIV) ) / f OUT)
PE = INT((215 ) x (MD + 1 - f XCLK x (2 (6 + NDIV - SDIV) ) / f OUT))
where fXCLK is the external crystal frequency in MHz (typically 27). The maximum SCLK frequency
generated by this block is f XTAL x 2 (2+NDIV).
For the lowest power operation, all clock sources should be set to the “zero” setting and the analog
power disables should be set. In this condition, only the crystal clock domain (XCLK) is running and
blocks in INCLK or DOTCLK domains may not be accessible through the I²C interface.
The following modules can have their clocks disabled to reduce power consumption when the chip
is in steady-state mode: FLK, OSD, PGEN, DFT, and DMEAS. Also, the clock to the TCON can be
disabled for non-Smart Panel applications. Note that the OSD module has a special power bypass
bit that must be enabled when the OSD clock is disabled.
Also, the clock to all I²C registers associated with modules in the INCLK and DOTCLK domains can
be disabled after the chip is configured to reduce power in steady-state mode. Note that during chip
configuration, all I²C clocks must be enabled.
An asynchronous clock enable override signal must be disabled to allow control of individual
module clock signals.
Table 3: SCLK Frequency Synthesizer Programmable Values (Sheet 2 of 2)
ADE3700 Global Control
Table 4: Global Registers (Sheet 1 of 4)
Global Control ADE3700
Table 4: Global Registers (Sheet 2 of 4)
ADE3700 Global Control
Table 4: Global Registers (Sheet 3 of 4)
FM Frequency Synthesizer ADE3700
2.2 FM Frequency Synthesizer The FM Frequency Synthesizer can create a clock up to eight times the crystal input clock using a
digital frequency synthesizer. The modulation period and amplitude are directly controlled by I2C
registers. The I2C interface runs in the LLK_CTRL clock domain, which must be active for access.
The relationship of the output frequency (f OUT ) to the 32-bit phase_rate value and the crystal
frequency (f XCLK ) is: OUT = f XCLK * 2 27+NDIV / phase_rate
where f OUT and f XCLK are in MHz.
The maximum output frequency of the FM frequency synthesizer is f XTAL x 2 (2+NDIV).
Note that native duty cycle of the FM frequency synthesizer is not 50/50, so it is recommended to
either enable the divide-by-two in the fm synthesizer block for frequencies up to f XCLK x 2 (1+NDIV)
(typically 108 MHz) or set the output mux to a double wide output mode for pixel clocks above XCLK x2 (1+NDIV) . This will ensure a 50% duty clock on the output.
Table 4: Global Registers (Sheet 4 of 4)
ADE3700 Analog-to-Digital Converter (ADC)
2.3 Analog-to-Digital Converter (ADC)The analog port consists of three 9-bit RGB ADCs with preamp, gain/offset adjustment and digital
filtering. The I2C interface for the ADC block is in the INCLK clock domain which must be active for
programming.
The relationship of input voltage, gain and offset register settings to output code is approximately as
follows:
output_code_8b = 457 x offset / 28 + 181 x gain x input_mV / 216 - 125 x gain x offset / 216 - 219
Table 5: FM Frequency Synthesizer Registers
Table 6: ADC Registers (Sheet 1 of 2)
Line Lock PLL ADE3700
2.4 Line Lock PLL The Line Lock PLL recovers a sample clock from an incoming hsync source. The response
characteristics of the line lock PLL can be adjusted for optimum response time and jitter filtering.
The phase of the sample clock can be digitally adjusted in steps of 289 ps (with a 27-MHz crystal).
The I2C interface of the line lock PLL is in the LLK_CTRL clock domain which must be active for
programming.
The PLL filter has three ranges with independent filter parameters. When the phase detector error
stays below a programmable threshold for a programmable number of input lines, the PLL filter
coefficients are changed. Any phase detector error above the programmed threshold will return the
filter to the appropriate level in one line. The operation is shown in Figure3.
The digital loop filter is controlled by three parameters: MFACTOR, A and B. M_FACTOR is the
desired number of clocks per input line. The A and B parameters control the response of the 2nd
order digital filter. A and B are composed of a linear and exponential component designated by the
L and E suffix, respectively. The relationship of these numbers to the classic 2nd order damping and
natural frequency are as follows:
Damping = AL x 2 (AE-12) x SQRT(5 x M_FACTOR / (BL x 2BE))
Natural Frequency = SQRT(M_FACTOR x 5 x BL x 2 (BE-34))
Figure 3: Line Lock PLL
Table 6: ADC Registers (Sheet 2 of 2)
ADE3700 Line Lock PLL
Table 7: Line Lock PLL Registers (Sheet 1 of 4)
Line Lock PLL ADE3700
Table 7: Line Lock PLL Registers (Sheet 2 of 4)
ADE3700 Line Lock PLL
Table 7: Line Lock PLL Registers (Sheet 3 of 4)
Line Lock PLL ADE3700
Table 7: Line Lock PLL Registers (Sheet 4 of 4)
ADE3700 Sync Retiming (SRT)
2.5 Sync Retiming (SRT)The Sync Retiming (SRT) block retimes incoming synchronization signals (H Sync, V Sync, etc) into
the XCLK and INCLK domains.
For the XCLK domain, the SRT has the following functions: Retimes all sync signals going to SMEAS into the XCLK domain. Extracts the vertical sync signal from composite sync signals (AHSYNC and ACSYNC pins) Divides clocks by 1024 for activity detection purposes. Generates a delay-filtered version of vertical sync from a mux-selectable vertical sync source. Generates a coast signal in the XCLK domain for the LLPLL.
Table 8: Sync Retiming Registers (Sheet 1 of 2)
Sync Retiming (SRT) ADE3700
Table 8: Sync Retiming Registers (Sheet 2 of 2)
ADE3700 Sync Measurement
2.6 Sync Measurement The Input Sync Measurement (SMEAS) block continuously detects activity from all video sources.
The module can measure the characteristics of the sync signals on any input port. The sync
measurement module reports the results of the measurements to the system microcontroller.
This portion of the sync measurement is fully synchronous on the crystal clock (XCLK). Another
block, the Sync Retiming Block (SRT), handles the asynchronous signal transfer of the incoming
sync signals.
Input Sync Functions: Activity Detection Sync Management Measurement
Table 9: Sync Measurement (Sheet 1 of 8)
Sync Measurement ADE3700
Table 9: Sync Measurement (Sheet 2 of 8)
ADE3700 Sync Measurement
Table 9: Sync Measurement (Sheet 3 of 8)
Sync Measurement ADE3700
Table 9: Sync Measurement (Sheet 4 of 8)
ADE3700 Sync Measurement
Table 9: Sync Measurement (Sheet 5 of 8)
Sync Measurement ADE3700
Table 9: Sync Measurement (Sheet 6 of 8)
ADE3700 Sync Measurement
Table 9: Sync Measurement (Sheet 7 of 8)
Sync Multiplexer (SMUX) ADE3700
2.7 Sync Multiplexer (SMUX)The Synchronization Multiplexer (SMUX) selects a set of sync signals from the input sources and
provides them to the scaler. It generates signals that are missing, depending on the capability. The
MCU can select the output sync signals between the input sources and the generated signals.
Figure 4: Sync Multiplexer Block Diagram
Table 9: Sync Measurement (Sheet 8 of 8)
ADE3700 Sync Multiplexer (SMUX)
2.7.1 Functional DescriptionThe internal signal selector selects which of the input sources are to be used for the internal hsync,
vsync and enab signals and is controlled by I2C register SMUX_CTRL0.
The signal generator contains a horizontal and a vertical counter that are resynced using a
horizontal and vertical reference signals respectively. The selection of the H/V references and the
resync edge (either rising or falling) are programmed via SMUX_CTRL1[3:0]. The signal generator
requires both references to be defined, or else the counters will not run properly and the generated
signals (other than venab) will be invalid.
The output signal selector can be programmed to output any of the internal syncs, bypassed signals
such as odd and data_valid, or the generated versions of all the signals (hsync, vsync, enab, odd,
valid). Vertical enable (venab) and clamp are always generated.
The following table summarizes programming for typical modes.
Other sources (such as composite sync) are simple variations on these basic configurations.
The programmed timing values of the generated signals (such as clamp) are relative to the
reference signal and edge selected. For example, if the LLK_HSYNC falling edge is selected as the
horizontal reference, then all horizontal programming values are relative to it.
Three signals are generated using programmable set/reset values: clamp and the two components
that make up the input enable signal (horizontal and vertical enables). The henab and venab signals
define the video window that the scaler operates on. The difference between the reset and set
quantities is the number of pixels (h) or lines (v) in the input image. Clean wraparound is supported:
the henab_set can be greater than the henab_rst.
The clamp pulse should be located outside the active video area, i.e. both programmed values
should be in the horizontal blanking region, typically in backporch of the incoming sync.
All set/reset programming values for clamp and henab must be less than the input horizontal total.
Both set/reset programming values for venab must be less than the input vertical total. The updates
for the enable registers can occur in four modes: No Shadowing Simple Shadowing: updates occur when the upper byte of _rst is written Shadowing + Blank Update: updates occur only in the next blanking region after rst_u is written Shadowing + Vblank Update: updates occur in the next vblank region after rst_u is written.
This mode also advances or retards the frame trigger to the scaler to prevent glitches. It takes
one frame to write H and two frames to write the V-position. With large position changes, a
glitch will show up. For small changes (e.g. ±1) no glitch is created.
The written position values are instantly available by read back, independent of shadow mode. The
actual values being used by the hardware at a given time can also be read back using separate I²C
Table 10: Sync Multiplexer Programming Table
Sync Multiplexer (SMUX) ADE3700When hsync and/or vsync is generated (e.g. when enab is the only input), the relative position of the
generated pulse can be set either before or after the reference edge between -128 and +127 pixels
per line.
2.7.2 ExampleADC input using line lock clock:
omux_ctrl0 = 0x09 // select llk hsync and vsync
omux_ctrl1 = 0x0F // choose incoming hsync and vsync as references, choose rising edges
omux_ctrl2 = 0x0C // select the original hsyncs and vsyncs, along with the generated
// enab and valid signals
henab_set = hsync_width + hback_porch
henab_rst = hsync_width + hback_porch + in_hpixel
venab_set = vsync_width + vback_porch
venab_rst = vsync_width + vback_porch + in_vpixel
clamp_set = hsync_width + hback_porch + in_hpixel + 4 // clamp is turned on 4 after last pixel
clamp_rst = hsync_width + hback_porch -4 // clamp is turned off 4 pixels before the 1st pixel
Table 11: Sync Multiplexer Registers (Sheet 1 of 4)
ADE3700 Sync Multiplexer (SMUX)
Table 11: Sync Multiplexer Registers (Sheet 2 of 4)
Sync Multiplexer (SMUX) ADE3700
Table 11: Sync Multiplexer Registers (Sheet 3 of 4)
ADE3700 Data Multiplexer
2.8 Data Multiplexer The Data Multiplexer provides the following functions: Debug modes (e.g. bit order swap, color swap)
Table 12: Data Mux Registers
Table 11: Sync Multiplexer Registers (Sheet 4 of 4)
Data Measurement (DMEAS) ADE3700
2.9 Data Measurement (DMEAS)The Data Measurement (DMEAS) module measures several characteristics of the data and sync
signals. Data measurements are taken over a programmable window as defined by an upper left
(mix_x, min_y) and a lower right (max_x, max_y), which may be the whole frame. Measurements
are programmable either per color channel or over all color channels.
This module computes all measurements of sync and data format that are done in the INCLK
domain. The Sync Measurement module does measurements in the XCLK domain. The INCLKS
per DE measurement does not use the window feature. It measures the number of INCLK per DE
and returns the result for every line.
All unused or reserved bits will return as zero.
Windows are relative to Sync pulses. A window defined from (0,0) - (0xFFF , 0xFFF) would go from
sync to sync. The reference edge to use, rising or falling, is also programmable per X and Y
coordinates. SMUX should be configured to provide a positive polarity sync to the DMEAS block. All
window enables are reset to 0 and will always be reset on the rising or falling edge of the sync
pulse.
Most algorithms can be run over separate or all color channels. Most algorithms also contain a
threshold value to zero out noise and/or amplify edges. Algorithm, Color, Threshold, or Window
Control changes are accepted at the end of a valid measurement so that they do not affect the
current measurement in progress.
Software can request measurements in one of two ways: All measurements, except DE_Size, are performed in One-shot mode, which is synchronous in
respect the microcontroller. The DE_Size measurement can be set either to One-shot or Free-running modes. Free-
running mode is asynchronous in respect to the microcontroller.
In One-shot mode, the block should indicate that the measurement is valid through an auto clear of
the start condition.
In Free-running mode, the block should indicate that the measurement is valid through a polling
bit. In Free-running mode, a Freeze bit is provided to freeze the results. Measurements still continue
with the polling bit active, however, they are not updated if the Freeze bit is set.
2.9.1 Edge IntensityThe Edge Intensity measurement is the sum of the absolute value of the delta between adjacent
pixels. A programmable threshold is applied to zero out noise and amplify edges. Equation:
Delta_val = abs(pixelA - pixelB) - threshold;
Delta_val = Delta_val < 0 0: Delta_val;
Sum += Delta_val;
For all 3 color channels: Sum += Delta_val on Red channel + Delta_val on Green channel +
Delta_val on Blue channel
2.9.2 Pixel SumThe Pixel Sum is the sum of all selected pixels for either a specific color channel or all color
channels within the window specified.
2.9.3 Minimum/Maximum PixelThis function reports the minimum and maximum pixel found within the specified window.
ADE3700 Data Measurement (DMEAS)
2.9.4 Pixel Cumulative Distribution (PCD)The Pixel Cumulative Distribution (PCD) function reports the total number of pixels greater than (or
less than) a programmable threshold.
To switch between pixels greater than or pixels less than the threshold, a control bit is provided in
the DMM_Mode register when requesting a measurement.
2.9.5 Horizontal Position The Horizontal Position measures the start and end of video data in INCLKS clock cycles relative to
the posedge of hsync.
The Data Horizontal Start is defined as the number of INCLKS clock cycles between posedge of
hsync and the “first data pixel”.
First data pixel is either: First pixel greater than the programmable threshold value First pixel with the absolute value (current pixel - previous pixel) is greater than the
programmable threshold value
The Data Horizontal End is defined as the number of INCLKS clock cycles between posedge of
hsync and the “last data pixel plus one”. The search for the last pixels ends at the end of a window.
Last data pixel plus one is either: Pixel after the last pixel that is greater than the programmable threshold value Last pixel with the absolute value (current pixel - previous pixel) is greater than the
programmable threshold value
To switch between the two threshold methods used in the first and last pixel, a control bit is provided
in the DMM_Mode register when requesting a measurement.
The first and last pixels are measured for each line, and the earliest first and latest last for the
selected pixel area are reported out at the end of the measurement. The intention is for “last data
pixel plus one” minus “first data pixel” is to equal the horizontal width of the video format.
2.9.6 Vertical PositionThe Vertical Position measures the start and end of video data in hsyncs relative to the posedge of
vsync.
The Data Vertical Start is defined as the number of hsyncs signals between the positive edge of the
vsync signal and the “first data pixel line”.
First data pixel line definition is the first line with at least one pixel that is greater then the
programmable threshold.
The Data Vertical End is defined as the number of hsyncs between posedge of vsync and the “first
blanking line after data plus one”. The first blanking line is detected then confirmed that each
subsequent line contains no data pixels. The confirmation of the first blanking line measurement
ends at the posedge of vsync.
The first blanking line after data definition is the row after the last row with at least one pixel greater
than the programmable threshold.
The first and last data pixel lines are measured within a frame and the earliest first and latest last for
the selected pixel area are reported out at the end of the measurement. The intention is for “data
vertical end plus one” minus “data vertical start” is to equal the vertical height of the video format.
Data Measurement (DMEAS) ADE3700
2.9.7 DE SizeThe DE Size measures the number of INCLKS clock cycles per data enable. It is useful for DVI
inputs to exactly measure the input image horizontal size.
At the end of the measurement (DE falling edge), the measured value is compared to a
programmed expected value ± a programmed threshold. If the expected value is within the
threshold, the DE_size_mismatch flag is not set. If the measured size is outside of the threshold,
the DE_size_mismatch flag is set.
In Free-running mode, the results are updated every line. The DE_size_mismatch flag is set at DE
falling edge and reset at DE rising edge.
In One-shot mode, the results are updated once and stay that way until they are cleared by
software. The DE_size_mismatch flag can only be cleared when the reset flag bit is set by software.
Table 13: DMEAS Output Register Mapping
Table 14: Data Measurement Registers (Sheet 1 of 3)
ADE3700 Data Measurement (DMEAS)
Table 14: Data Measurement Registers (Sheet 2 of 3)
LCD Scaler ADE3700
2.10 LCD Scaler The LCD Scaler module resizes images from one resolution to another. It employs a 3x3 non-
separable scaling filter which performs a dot product of the input pixel values with a weighting
vector that is computed from the chosen filtering function. To sharpen text without introducing
excessive artifacts, the output pixel’s contrast level is adjusted based on the context value
measured over a 3x3 grid in the relevant area of the source image.
For proper scaler operation, the SCLK frequency must be set greater than the max of DCLK and
IN_HPIXEL x DCLK_FREQ / (DEST_HPIXEL x PIXEL_AVG).
Table 15: LCD Scaler Registers (Sheet 1 of 3)
Table 14: Data Measurement Registers (Sheet 3 of 3)
ADE3700 LCD Scaler
Table 15: LCD Scaler Registers (Sheet 2 of 3)
LCD Scaler ADE3700
Table 15: LCD Scaler Registers (Sheet 3 of 3)
ADE3700 Output Sequencer
2.11 Output Sequencer The Output Sequencer module synchronizes timing for the output video interface. It allows sufficient
flexibility to support a broad range of Smart Panel applications as well using the Output Timing
Controller (TCON) module, refer to Section 2.12 for more details. The timing unit is based on
horizontal and vertical counters, which are locked with the input video stream.
2.11.1 Frame SynchronizationDue to the limited pixel memory of the chip, the output active video needs to be perfectly
synchronized with the input active video. This mode of operation is called Frame Lock.
2.11.2 Timing UnitThe Timing Unit consists of a 12-bit horizontal and 12-bit vertical counter. It is synchronized with the
input video stream.
2.11.3 Signal GenerationThe Signal Generation unit can generate all fixed control signals like hsync, vsync and data enable
as well as those required to run the internal data path. The fixed control signals appear on the
Figure 5: Output Sequencer and Timing Controller Block Diagram
Figure 6: Frame Lock Operation
