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ADE3700SX ,Analog LCD Display Engine for XGA and SXGA Resolutionsfeaturesgeneration of ADE3xxx Scaling Engines.■ Framelock operation with Safety Mode™■ Serial I²C i ..
ADE3700X ,Analog LCD Display Engine for XGA and SXGA ResolutionsFeaturessaturation gamma controls for all inputs● Flexible data inversion / transition ● Simple whi ..
ADE3700XT ,Analog LCD Display Engine for XGA and SXGA ResolutionsFunctional Description ..332.7.2 Example ......342.8 Data Multiplexer ..... 372.9 Data Measurement ..
ADE3800SXL ,Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS TransmittersGeneral Description■ IQSync™ AutoSetupADE3800 devices are a family of highly-integrated ■ Integrate ..
ADE3800XL ,Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS TransmittersLVDSRSDSProgrammableOutput Formatter30-bit Programmable Gamma Table® ADE3800Analog LCD Display Engi ..
ADV7842KBCZ-5 , Dual HDMI Fast Switching Receiver with 12-Bit, 170 MHz Video and Graphics Digitizer and 3D Comb Filter Decoder
ADV7842KBCZ-5P , Dual HDMI Fast Switching Receiver with 12-Bit, 170 MHz Video and Graphics Digitizer and 3D Comb Filter Decoder
ADV7850KBCZ-5 , Complete AV Front End
ADVFC32KN ,Voltage-to-Frequency and Frequency-to-Voltage Converterspecifications are guaranteed,although only those shown in boldface are tested on all production un ..
ADVFC32SH ,Voltage-to-Frequency and Frequency-to-Voltage ConverterSpecifications shown in boldface are tested on all production units atfinal electrical test. Result ..
ADVFC32SH ,Voltage-to-Frequency and Frequency-to-Voltage Converterspecifications.out affecting linearity or temperature drift.REV. AInformation furnished by Analog D ..
ADE3000-ADE3000SX-ADE3000T-ADE3100-ADE3300
LCD DISPLAY ENGINES WITH INTEGRATED DVI, ADC AND YUV PORTS
ADE3000 ADE3050 ADE3100
ADE3200 ADE3250 ADE3300LCD Display Engines
with Integrated DVI, ADC and YUV Ports
The ADE3xxx is a family of highly integrated display engine ICs, enabling the most advanced, flexible, and
cost-effective system-on-chip solutions for LCD display applications. The ADE3xxx line-up covers the full
range of applications from XGA analog only to dual SXGA Smart Panel designs. All twelve ADE3xxx
devices are pin-to-pin compatible and use a common software platform.
Feature Overview Programmable Context Sensitive™ Scaling High-quality up-scaling and down-scaling Dual Input: DVI / VGA Integrated 9-bit ADC/PLL Integrated DVI-Rx IQSync™ AutoSetup Integrated programmable timing controller Integrated Pattern generator Perfect Picture™ Technology sRGB 3D Color Warp Integrated OSD Advanced EMI reduction features Framelock operation with Safety Mode™ Serial I²C interface Low power 0.18 μm process technology
Product Selector
ADE3XXX
Third Generation Context Sensitive™ Scaler Sharper text with Edge Enhancement RAM based coefficients for unique
customization 5:1 upscale and 2:1 downscale Independent X - Y axis zoom and shrink Bob de-interlacing eliminates jaggies and
motion artifacts
Analog RGB input 140MHz 9-bit ADC Ultra low jitter digital linelock PLL Composite Sync and Sync on Green support
Secure DVI™ Receiver Single Link DVI receiver Input Pixel Rate from 25 to140 MHz Low power mode with activity detection Compatibility with all DVI compliant
transmitters
Digital TV Video Input VESA VIP 1.1, 2.0 and CCIR656 compliant 25 to 75 MHz input clock
IQsync™ AutoSetup AutoSetup configures phase, clock, level, and
position Supports continuous calibration for reduced
user intervention Detects activity on all inputs and selects the
active source Compatible with all standard VESA and GTF
modes
Perfect Picture™ Technology Video & Picture highlight zoning Supports up to 7 different windows Independent window controls for contrast
brightness, sharpness, and color
Perfect Color™ Technology Programmable 3D color warp Digital brightness, contrast, hue, and
saturation gamma controls for all inputs Simple white point control Compatible with sRGB standard True color dithering for 12- and 18-bit panelsT emporal and spatial dithering 30-bit programmable gamma table
OSD Engine 256 RAM based 12x18 characters 1 and 4-bit per pixel color characters Bordering, shadowing, transparency, fade-in,
and fade-out Supports font rotation Up to 4 sub windows 32 entry TrueColor LUT
Programmable Timing Controller (TCON) Highly-programmable support for XGA, TTL
and RSDS SmartPanels Dual function TTL and RSDS outputs Advanced flicker detection and reduction 12 programmable timing signals for row/
column control Wide range of drivers & TCON compatibility Simulation tools for easy programming Supports complex polarity generation for IPS
panels
Advanced EMI Reduction Features Flexible data inversion / transition
minimization, single, dual, and separate Per pin delay, 0 to 6ns in 0.4ns increments Adaptive Slew Rate control outputs Supports 18/24/36/48-bit RSDS outputs Differential clock Spread spectrum -programmable digital FM
modulation of the output clock with no
external components
Output Format Supports resolutions up to SXGA @ 75Hz Supports 6 or 8-bit Panels
ADE3XXX able of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51.1 Pin Description ....................................................................................................................6
Chapter 2 ADE3XXX Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132.1 Global Control Block ..........................................................................................................13
2.2 FM Frequency Synthesizer ................................................................................................17
2.3 ADC Block ..........................................................................................................................18
2.4 Line Lock PLL Block ...........................................................................................................19
2.5 Digital Video Input (DVI) .....................................................................................................22
2.6 HDCP Block .......................................................................................................................27
2.7 YUV Block ..........................................................................................................................29
2.8 Sync Retiming Block ..........................................................................................................30
2.9 Sync Measurement Block ..................................................................................................32
2.10 Sync Mux Block ..................................................................................................................40
2.11 Data Mux Block ..................................................................................................................42
2.12 Data Measurement Block ...................................................................................................42
2.12.1 Edge Intensity ....................................................................................................................................43
2.12.2 Pixel Sum ...........................................................................................................................................43
2.12.3 Min / Max ...........................................................................................................................................43
2.12.4 PCD ...................................................................................................................................................43
2.12.5 H Position Min / Max ..........................................................................................................................43
2.12.6 V Position Min / Max ..........................................................................................................................44
2.12.7 DE Size ..............................................................................................................................................44
2.13 Programmable Nonlinearity Block ......................................................................................48
2.14 Scaler Block .......................................................................................................................49
2.15 Output Sequencer Block ....................................................................................................52
Frame Synchronization .......................................................................................................................................52
Timing Unit ..........................................................................................................................................................52
Signal Generation ...............................................................................................................................................52
2.16 Timing Controller (TCON) Block ........................................................................................55
2.17 Pattern Generator Block .....................................................................................................60
Screen Split ........................................................................................................................................................60
Pattern Engine ....................................................................................................................................................61
Borders ...............................................................................................................................................................61
ADE3XXX2.18 SRGB Block ........................................................................................................................64
2.18.1 Parametric Gamma Correction and Digital Contrast/Brightness Control ..........................................64
2.18.2 Color Space Warp .............................................................................................................................64
2.19 OSD Block ..........................................................................................................................66
2.20 Flicker Block .......................................................................................................................72
2.21 Gamma Block .....................................................................................................................74
2.22 APC Block ..........................................................................................................................74
2.23 Output Mux Block ...............................................................................................................75
2.24 Pulse Width Modulation (PWM) Block ................................................................................77
2.25 DFT Block ...........................................................................................................................79
2.26 I²C RAM Addresses ...........................................................................................................80
Chapter 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823.1 Absolute Maximum Ratings ................................................................................................82
3.2 Power Consumption Matrices .............................................................................................82
3.3 Nominal Operating Conditions ............................................................................................83
3.4 Preliminary Thermal Data ...................................................................................................84
3.5 Preliminary DC Specifications ............................................................................................84
3.5.1 LVTTL 5 Volt Tolerant Inputs With Hysteresis ...................................................................................84
3.5.2 LVTTL 5 Volt Tolerant Inputs .............................................................................................................84
3.5.3 LVTTL 5 Volt Tolerant I/O With Hysteresis ........................................................................................84
3.5.4 LVTTL Outputs ..................................................................................................................................84
3.6 Preliminary AC Specifications ...........................................................................................85
Chapter 4 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Chapter 5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ADE3XXX General Description The ADE3XXX family of devices is capable of implementing all of the advanced features of today’s
LCD monitor products. For maximum flexibility, an external microcontroller (MCU) is used for
controlling the ADE3XXX and other monitor functions.
The ADE3XXX architecture unburdens the MCU from all data-intensive pixel manipulations,
providing an optimal blend of feature and code customization without incurring the cost of a 16-bit
processor or memory. The key interactions between the monitor MCU and the ADE3XXX can be
broken down into the features shown in the table below.
Figure 1: ADE3XXX Block Diagram
Table 1: ADE3xxx Features (Sheet 1 of 2)
Pin Description ADE3XXX
1.1 Pin Description
Table 2: Pin Description (Sheet 1 of 7)
Table 1: ADE3xxx Features (Sheet 2 of 2)
ADE3XXX Pin Description
Table 2: Pin Description (Sheet 2 of 7)
Pin Description ADE3XXX
Table 2: Pin Description (Sheet 3 of 7)
ADE3XXX Pin Description
Table 2: Pin Description (Sheet 4 of 7)
Pin Description ADE3XXX
Table 2: Pin Description (Sheet 5 of 7)
ADE3XXX Pin Description
Table 2: Pin Description (Sheet 6 of 7)
Pin Description ADE3XXX
Table 2: Pin Description (Sheet 7 of 7)
ADE3XXX Global Control Block ADE3XXX Functional Description
2.1 Global Control BlockThe global control block is responsible for: Selecting Clock Sources Power Control I²C Control SCLK Frequency Synthesizer Control Block-by-Block Synchronous Reset Generation
The global control block runs on the XCLK clock domain which is required to be active for
programming. The clock domains of all other blocks are set in the Global Control Block. For I²C
access, the requested block must be driven with a valid clock above 10 MHz. Clock domains are
shown in Figure 2.
To program the SCLK frequency synthesizer to a desired frequency (fout, in MHz), the following
equations apply:
Figure 2: Clock Domains
Table 3: SCLK Frequency Ranges
Global Control Block ADE3XXXMD = INT(f XCLK x (2 (6 + NDIV - SDIV) ) / f OUT)
PE = INT((215 ) x (MD + 1 - f XCLK x (2 (6 + NDIV - SDIV) ) / f OUT))
where f XCLK is the external crystal frequency in MHz (typically 27). The maximum SCLK frequency
generated by this block is f XTAL x 2 (2+NDIV).
For lower power operation, set all clock sources to the “zero” setting and also set the analog power
disables. In this condition, only the crystal clock domain (XCLK) runs and blocks in INCLK or
DOTCLK domains are not accessible by I2C. o detect a DVI plug event and wake from a low power state, program the DVI detection clock
source select to the DVI detect clock and enable the analog power control for the DVI detect clock.
All other clock sources are set to zero.
Table 4: Global Registers (Sheet 1 of 4)
Table 3: SCLK Frequency Ranges (Continued)
ADE3XXX Global Control Block
Table 4: Global Registers (Sheet 2 of 4)
Global Control Block ADE3XXX
Table 4: Global Registers (Sheet 3 of 4)
ADE3XXX FM Frequency Synthesizer
2.2 FM Frequency Synthesizer The FM frequency synthesizer creates a clock equivalent to up to eight times the crystal input clock,
using a digital frequency synthesizer. The modulation period and amplitude are directly controlled
by I2C registers. The I2C interface runs in the LLK_CTRL clock domain, which must be active for
access.
The output frequency (f OUT ) is related to the 32-bit PHASE_RATE and crystal frequency (f XCLK ) as
follows: OUT = f XCLK x 2 27+NDIV / PHASE_RATE
Table 4: Global Registers (Sheet 4 of 4)
ADC Block ADE3XXXwhere f OUT and f XCLK are in MHz.
The maximum output frequency of the fm frequency synthesizer is f XTAL x 2 (2+NDIV).
Note that native duty cycle of the fm frequency synthesizer is not 50/50. We recommend to either
enable the divide-by-two in the fm synthesizer block for frequencies up to f XCLK x 2 (1+NDIV) (typically
108 MHz) or set the output mux to a double wide output mode for pixel clocks above f XCLK x (1+NDIV) . This will ensure a 50% duty clock on the output.
2.3 ADC BlockThe analog port consists of three 9-bit RGB ADCs with preamp, gain/offset adjustment and digital
filtering. The I2C interface for the ADC block is in the INCLK clock domain which must be active for
programming.
Input voltage, gain and offset register settings are approximately related to the output code. In this
equation, the output code (OUTPUT_CODE_8B) is equal to:
457 x offset / 28 + 181 x gain x input_mV / 216 - 125 x gain x offset / 216 - 219
Table 5: FM Frequency Synthesizer Registers
Table 6: ADC Registers
ADE3XXX Line Lock PLL Block
2.4 Line Lock PLL BlockThe line lock PLL recovers a sample clock from an incoming hsync source. The response
characteristics of the line lock PLL are adjustable for optimimum response time and jitter filtering.
The phase of the sample clock is digitally adjustable by steps of 289 ps (with a 27-MHz crystal). The
I2C interface of the line lock PLL is in the LLK_CTRL clock domain which must be active for
programming.
The PLL loop filter has three ranges with independent filter parameters. When the phase detector
error remains below a programmable threshold for a programmable number of input lines, the loop
filter coefficients change. Any phase detector error above the programmed threshold reverts the
filter to the appropriate level in one line. The operation is represented in Figure 3.
The digital loop filter is controlled by three parameters: MFACTOR, A and B. M_FACTOR is the
desired number of clocks per input line. The A and B parameters control the response of the 2nd
order digital filter. A and B are composed of a linear and exponential component designated by the
L and E suffix, respectively. These numbers are related to the classic 2nd order damping and
natural frequency as follows:
Damping = AL x 2 (AE-12) x SQRT(5 x M_FACTOR / (BL x 2BE))
Natural Frequency = SQRT(M_FACTOR x 5 x BL x 2 (BE-34))
Figure 3: Line Lock PLL State Diagram
Table 7: Line Lock PLL Registers (Sheet 1 of 4)
Line Lock PLL Block ADE3XXX
Table 7: Line Lock PLL Registers (Sheet 2 of 4)
ADE3XXX Line Lock PLL Block
Table 7: Line Lock PLL Registers (Sheet 3 of 4)
Digital Video Input (DVI) ADE3XXX
2.5 Digital Video Input (DVI)The DVI receiver has the following features: compatible with all DVI complaint transmitters up to 140 MHz pixel clock on chip termination adjustable by I2C and/or one (~10X) external reference resistor HDCP and standby / power down supported decoder digitally corrects for skew errors of at least ±1 pixel in reference to any other channel bitstream can be decoded and measured without the presence of horizontal and vertical sync
Table 7: Line Lock PLL Registers (Sheet 4 of 4)
ADE3XXX Digital Video Input (DVI)Recommended values for best receiver quality are given in the following table:
Table 8: Recommended DVI Values
Table 9: DVI Registers (Sheet 1 of 5)
Digital Video Input (DVI) ADE3XXX
Table 9: DVI Registers (Sheet 2 of 5)
ADE3XXX Digital Video Input (DVI)
Table 9: DVI Registers (Sheet 3 of 5)
Digital Video Input (DVI) ADE3XXX
Table 9: DVI Registers (Sheet 4 of 5)
ADE3XXX HDCP Block
2.6 HDCP BlockThe HDCP block implements the datapath decryption block of the HDCP content protection scheme
of DVI. Please refer to the HDCP Specification 1.0 for details. The state machines of the HDCP
specification are split between the external microcontroller and this block. Only the high speed and
data intensive cryptographic functions are implemented in this block to maintain maximum system
level flexibility.
Table 9: DVI Registers (Sheet 5 of 5)
HDCP Block ADE3XXX
Table 10: HDCP Registers
ADE3XXX YUV Block
2.7 YUV BlockThe TV video input module is used to interface external TV video decoder chip. It handles VESA
Video Interface Port(VIP) 8-bit/16-bit YCBCR , VMI/ ITU-R Recommendation 656 (CCIR656) YCBCR
and double clock edge input RGB data formats. It extracts embedded sync timing and converts data
into RGB color space. All the functions in this module are controlled by the system microcontroller
through I2C registers.
The following table describes the different pin configurations for YUV/RGB digital input.
X = don’t care
Table 11: YUV Registers (Sheet 1 of 2)
Sync Retiming Block ADE3XXX
2.8 Sync Retiming BlockThe Sync Retiming (SRT) block retimes incoming synchronization signals (H Sync, V Sync, etc) into
the XCLK and INCLK domains.
For the XCLK domain, SRT has the following functionality: Retimes all sync signals going to SMEAS into the XCLK domain. Extracts vertical sync from composite sync signals (ahsync and acsync pins) Divides clocks by 1024 for activity detection purposes. Generates a delay-filtered version of vertical sync from a mux-selectable vertical sync source. Generates a coast signal in the XCLK domain for the LLPLL.
Table 12: Sync Retiming Registers (Sheet 1 of 2)
Table 11: YUV Registers (Sheet 2 of 2)
ADE3XXX Sync Retiming Block
Table 12: Sync Retiming Registers (Sheet 2 of 2)
Sync Measurement Block ADE3XXX
2.9 Sync Measurement BlockThe Input Sync Measurement Block (SMEAS) continuously detects activity from all video sources.
The module can measure the characteristics of the sync signals on any input port. The sync
measurement module reports the results of the measurements to the system microcontroller.
This portion of the sync measurement is fully synchronous on the crystal clock (XCLK). Another
block, the Sync Retiming Block (SRT), handles the asynchronous signal transfer of the incoming
sync signals.
Input Sync Functions: Activity detection Sync management Measurement
Table 13: Sync Measurement Registers (Sheet 1 of 8)
ADE3XXX Sync Measurement Block
Table 13: Sync Measurement Registers (Sheet 2 of 8)
Sync Measurement Block ADE3XXX
Table 13: Sync Measurement Registers (Sheet 3 of 8)
ADE3XXX Sync Measurement Block
Table 13: Sync Measurement Registers (Sheet 4 of 8)
Sync Measurement Block ADE3XXX
Table 13: Sync Measurement Registers (Sheet 5 of 8)
ADE3XXX Sync Measurement Block
Table 13: Sync Measurement Registers (Sheet 6 of 8)
Sync Measurement Block ADE3XXX
Table 13: Sync Measurement Registers (Sheet 7 of 8)
ADE3XXX Sync Measurement Block
Table 13: Sync Measurement Registers (Sheet 8 of 8)
Sync Mux Block ADE3XXX
2.10 Sync Mux BlockThe Sync Mux (SMUX) block provides the following functions: selects between all possible sync signals generates missing sync signals selects between original and generated signals for output generates the clamp signal for the ADC
Table 14: Sync Mux Registers (Sheet 1 of 2)
ADE3XXX Sync Mux Block
Table 14: Sync Mux Registers (Sheet 2 of 2)
Data Mux Block ADE3XXX
2.11 Data Mux BlockData mux provides the following functions: selection of one among three data sources debug modes (e.g. bit order swap, color swap)
2.12 Data Measurement BlockThe Data Measurement module measures several characteristics of the data and sync signals.
Data measurements are taken over a programmable window as defined by an upper left (mix_x,
min_y) and a lower right (max_x, max_y), which may be the whole frame. Measurements are
programmable either per color channel or over all color channels.
This module computes all measurements of sync and data format that are done in the INCLK
domain. The Sync Measurement module does measurements in the XCLK domain. The INCLKs
per DE measurement does not use the window feature. It measures the number of INCLK per DE
and returns the result for every line.
All unused or reserved bits return as zero.
Windows are relative to Sync pulses. A window defined from (0,0) - (0xFFF, 0xFFF) goes from sync
to sync. The reference edge to use, rising or falling, is also programmable per X and Y coordinates.
Configure SMUX to provide a positive polarity sync to the DMEAS block. All window enables reset
at 0 and always reset on the rising or falling edge of sync.
See the description of the specific PHM and DMM measurements performed within DMEAS here
below. Most algorithms are run over separate or all color channels. Most algorithms also contain a
threshold value to zero out noise and/ or amplify edges. Algorithm, Color, Threshold, or Window
Control changes are accepted at the end of a valid measurement, the current measurement in
progress is not affected.
Software requests measurements in one of two ways: One shot - synchronous with respect to the microcontroller.
Table 15: Data Mux Registers
ADE3XXX Data Measurement BlockIn One-shot mode, the block indicates that measurement is valid through an auto-clear of start
condition.
In Free-running mode, the block indicates that measurement is valid through a polling bit. In Free-
running mode, a freeze bit is provided to freeze the results. Measurements continue with the polling
bit active, but they are not updated if the Freeze bit is set.
2.12.1 Edge IntensityThe Edge Intensity measurement is the sum of the absolute value of the delta between adjacent
pixels. A programmable threshold is applied to zero out noise and amplify edges.
Equation:
Delta_val = abs(pixelA - pixelB) - threshold;
Delta_val = Delta_val < 0 0: Delta_val;
Sum += Delta_val;
For all 3 color channels:
Sum += Delta_val on Red channel + Delta_val on Green channel + Delta_val on Blue channel
2.12.2 Pixel SumThe Pixel Sum is the sum of all selected pixels for either a specific color channel or all color
channels within the window specified.
2.12.3 Min / MaxThe Min / Max reports the minimum and maximum pixel found withing the window specified.
2.12.4 PCDPixel cumulative distribution function reports the total number of pixels greater than (or less than) a
programmable threshold.
To switch between pixels greater than or pixel less than the threshold, a control bit is provided in the
DMM_Mode register when requesting a measurement.
2.12.5 H Position Min / MaxHorizontal position measures the start and end of video data in INCLKs relative to the posedge of
hsync.
Data horizontal start is defined as the number of INCLKs between posedge of hsync and the "first
data pixel".
First data pixel is either: first pixel greater than the programmable threshold value, or first pixel with the absolute value (current pixel - previous pixel) is greater than the
programmable threshold value
Data horizontal end is defined as the number of INCLKs between posedge of hsync and the "last
data pixel plus one". The search for the last pixels ends at the end of a window.
Last data pixel plus one is either: pixel after the last pixel that is greater than the programmable threshold value,or last pixel with the absolute value(current pixel - previous pixel) is greater than the
programmable threshold value.
When measurement is required, a control bit in the DMM_Mode register is used to switch between
Data Measurement Block ADE3XXXThe first and last pixels are measured for each line, and the earliest first and latest last for the
selected pixel area are reported out at the end of the measurement. The intention is that "last data
pixel plus one" minus "first data pixel" is equal to the horizontal width of the video format.
2.12.6 V Position Min / MaxVertical position measures the start and end of video data in hsyncs relative to the posedge of
vsync.
Data vertical start is defined as the number of hsyncs between posedge of vsync and the "first data
pixel line".
First data pixel line definition is the first line with at least one pixel greater then the programmable
threshold.
Data vertical end is defined as the number of hsyncs between posedge of vsync and the "first
blanking line after data plus one". The first blanking line is detected and confirms that each
subsequent line contains no data pixels. The confirmation of the first blanking line measurement
ends at the posedge of vsync.
First blanking line after data definition is the row after the last row with at least one pixel greater than
the programmable threshold.
The first and last data pixel lines are measured within a frame. The earliest first and latest last data
pixels corresponding to the selected pixel area are reported out at the end of the measurement. The
intention is that "data vertical end plus one" minus "data vertical start" is equal to the vertical height
of the video format.
2.12.7 DE SizeDE Size measures the number of INCLKs per data enable. DVI input measures precisely the input
image horizontal size.
At the end of the measurement (DE falling edge), the measured value is compared to a
programmed expected value +/- a programmed threshold. If the expected value is within the
threshold, the DE_size_mismatch flag is not set. If the measued size is outside the threshold, the
DE_size_mismatch flag is set.
In Free-running mode, results are updated at every line. The DE_size_mismatch flag is set at DE
falling edge and reset at DE rising edge.
In One-shot mode, results are updated once and kept until they are cleared by software. The
DE_size_mismatch flag can only be cleared when the reset flag bit is set by software.
Table 16: Data Measurement Registers (Sheet 1 of 5)
