ADD3701CCN ,3 3/4 DIGIT DVM WITH MULTIPLEXED 7-SEGMENT OUTPUTElectrical Characteristics
4.75V svcc s 5.25V, - 40'C STAS + 85°C, unless otherwise specified.
..
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ADD3701CCN
3 3/4 DIGIT DVM WITH MULTIPLEXED 7-SEGMENT OUTPUT
ADD3701
National
[ Semiconductor
ADD3701 3% Digit DVM with Multiplexed 7-Segment
Output
General Description
The ADD3701 (MM74C936-1) monolithic DVM circuit is
manufactured using standard complementary MOS (CMOS)
technology. A pulse modulation analog-to-digital conversion
technique is used and requires no external precision Com-
ponents. In addition, this technique allows the use of a refer-
ence voltage that is the same polarity as the input voltage.
One 5V (TTL) power supply is required. Operating with an
isolated supply allows the conversion of positive as well as
negative voltages. The sign of the input voltage is automati-
cally determined and output on the sign pin. If the power
supply is not isolated, only one polarity of voltage may be
converted.
The conversion rate is set by an internal oscillator. The fre-
quency of the oscillator can be set by an external RC net-
work or the oscillator can be driven from an external fre-
quency source. When using the external RC network, a
square wave output is available. It is important to note that
great care has been taken to synchronize digit multiplexing
with the AID conversion timing to eliminate noise due to
power supply transients.
The ADD3701 has been designed to drive 7-segment multi-
plexed LED displays directly with the aid of external digit
buffers and segment resistors. Under condition of over-
range, the overflow output will go high and the display will
read +OFL or -OFL, depending on whether the input volt-
age is positive or negative. In addition to this, the most sig-
nificant digit is blanked when zero.
A start conversion input and a conversion complete output
are included.
Features
I Operates from single 5V supply
I! Converts 0 to 13999 counts
n Multiplexed 7-segment
II Drives segments directly
I: No external precision components necessary
I: Accuracy specified over temperature
a Medium speed - 400 ms/conversion
1: Internal clock set with RC network or driven externally
n Overrange indicated by +OFL or --OFL display read-
ing and OFLO output
" Analog inputs in applications shown can withstand
1200 Volts
u ADD3701 equivalent to MM740936-1
Applications
1: Low cost digital power supply readouts
II Low cost digital multimeters
II Low cost digital panel meters
u Eliminate analog multiplexing by using remote A/D con-
verters
Convert analog transducers (temperature, pressure, dis-
placement, etc.) to digital transducers
u Indicators and displays requiring readout up to 3999
counts
Connection Diagram
let:- I
Aimee tttat-- t
St-' 5
one --i 1
cnuvsnssou court": - '
sum couvznswu - '
SIGN - III
Vritrgte-_ tt
1ripil-)--1 "
Iles)--- 13
ADD3701
u --s.
" "-Sf
" '-GMI
" '-0ttltTt (mo)
" -tltttir ,
" -lritltT a
21 -tumTqtLt0)
" -t0UT
" -rttt
u "-1ftttF
" -ilm
n --sw2
u '-A0Ltttl nun
TL/Fi/5682-t
Order Number ADD37tMCCN
See NS Package Number N288
Absolute Maximum Ratings (Note1)
" MllltarylAerospaoe specified devices are required, Operating Temperature Range (T A)
please contact the National Semiconductor Sales Package Dissipation at T A-- 25'C
11','t1f,'l1rrlt'vuli,',1', tor atvallablllty and spttttWtatlttns. Operating Voc R an g e
'i'l'lrg',tnQh'i,''n' excep -0.3Y to vcc+o.3v Ahsolutts Maximum YOC
Voltage at Start Conversion - 0.3V to + 15.0v Lead Temp. (Sokioring, IO seconds)
esp Susceptibility (Note 5) TBDV Storage Temperature Range
Electrical Characteristics
4.75V g Vcc S 5.25V, - 40'C STAS + 85''C, unless otherwise specified.
- 4tPC to + 85'C
4.5V to 6.0V
-65'C to + 150°C
Parameter Conditions Mln Typ2 Max Units
Vem; Logical "I " Input Voltage Vcc - 1.5 V
VIN(O) Logical "0" Input Voltage 1.5 V
Vouno) Logical "0" Output Voltage lo= 1.1 mA 0.4 V
(All Digital Outputs Except
Digital Outputs)
V0UT(0) Logical "O" Output Voltage lo = 0.7 mA 0.4 V
(Digit Outputs)
VOUT(1) Logical "1" Output Voltage IQ = 50 mA tt Tg = 25'C VCC= 5V Vcc -1.6 Vcc - 1 .3 [ V
(All Segment Outputs) lo = 30 mA g Tu = 100°C Vcc -1.6 Vcc --1.3 V
Voum) Logical "I" Output Voltage Io = 500 pA (Digit Outputs) Vcc - 0.4 V
(All Digital Outputs Except Io = 360 pA (Conv. Complete,
Segment Outputs) + / - . OFLO Outputs)
Isouncg Output Source Current VOUT = 1.0 V 2.0 mA
(Digital Outputs)
IIN(1) Logica1"1" Input Current " = 15V 1.0 pA
(Start Conversion)
'thO) Logical "o'' Input Current Vm = 0V - 1.0 pLA
(Start Conversion)
'00 Supply Current Segments and Digits Open 0.5 10 mA
fosc Oscillator Frequency 0.6/ RC kHz
1m Clock Frequency 100 640 kHz
tc Conversion Rate IlN/129.024 conv./sec
fMUX Digit Mux Rate lel 51 2 Hz
tBWK Inter Digit Blanking Time 1/(321Mux) seconds
gopw Start Conversion Pulse Width 200 DC ns
Noon It Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. 00 and " electinal specifications do not apply when operating
me device beyond its 8peeititsd operating conditions.
Note 2: All typicals given for a--- 25'0.
Note 3: Full scale= 4000 counts; therefore 0.025% of full scale =1 count and 0.05% of full scale=2 counts.
Ham 4: For 2.000 Volts full scale. 1 mV=2 counts.
Note s.. Human body model. 100 pF discharged through a 1.5 en resistor.
LOLSCIGV
ADD3701
Electrical Characteristics (Continued)
to = 2.5 conversions/second. 0°CSTA s + 70°C, unless otherwise specirmi.
Parameter Conditions Min Typ2 Max Unlts
Non-Linearity of Output " = 0 - 2V Full Scale -0.05 i 0.025 t 0.05 % full scale
Reading lhN---0-200 mV Full Scale -0.05 10.025 k0.05 (Note 3)
Quantization Error -1 + 0 counts
Offset Error, VIN =0V -0.5 + 1.5 + 3 mV (Note 4)
Rollover Error - 0 + 0 counts
Analog Input Current TA = 25°C - 5 i 1 + 5 nA
(V IN + , VIN -)
Block Diagram
ADD3701 3%-DIglt DVM
START 301W
DIGITAL nulls "
run "I AND cmn’nol.
DIGIT I tteSttl
IIISIT t
"IEO OUT ID!
DIG" 3
lllGlT CLAIR ttttttTer)
BUIPABATGR
TIIIIE
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GNP ."-ett
oan "t ovunow
cow corms"
Alllol lee
VIILTII
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TL/H/5682-2
Theory of Operation
A schematic for the analog loop is shown in Figure f. The
output of SW1 is either at VREF or zero volts, depending on
the state of the D tlip-flop. if Q is at a high level,
vom= VREF and if Q is at a low level VOUT=0V. This volt-
age is then applied to the low pass filter comprised of RI
and Cl. The output of this filter, VFB, is connected to the
negative input of the comparator, where it is compared to
the analog input voltage, VIN. The output of the comparator
is connected to the D input of the D flip-flop. Information is
then transferred from the D input to the Q and O outputs on
the positive edge of clock. This loop forms an oscillator
whose duty cycle is precisely related to the analog input
voltage, VIN-
An example will demonstrate this relationship. Assume the
input voltage is equal to 0.500 V. If the Q output of the D flip-
flop is high then VOUT will equal VREF (2.000 V) and VFB will
charge toward 2 V with a time constant equal to R101. At
some time VFB will exceed 0.500 V and the comparator
output will switch to 0V. At the next clock rising edge the t2
output of the D flip-flop will switch to ground, causing VOUT
to switch to 0V. At this time VFB will start discharging toward
ov with a time constant Roth. When VFB is less than 0.5 V
the comparator output will switch high. On the rising edge of
the next clock the 0 output of the D tlip-tlop will switch high
and the process will repeat. There exists at the output of
SW1 a square wave pulse train with positive amplitude VHEF
and negative amplitude 0V.
The DC value of this pulse train is:
VOUT = VREF = VREF (duty cycle)
t0N + ton:
Schematic Diagram
The lowpass filter will pass the DC value and than:
VFB = VREF (duty cycle)
Since the closed loop system will always force l/rm to equal
VIN. we can then say that:
VIN = VFe = VREF (duty cycle)
----- (duty cycle)
The duty cycle is logically ANDed with the input frequency
m. The resultant frequency f equals:
f=(duty cycle)>< (clock)
Frequency f is accumulated by counter no. 1 for a time de-
termined by counter no. 2. The count contained in counter
no. 1 is then:
_ = (duty cycle) x (clock)
(count) (clockv N (clock)/N
= - x N
For the ADD3701 N = 4000.
a sm Rs
.1. Wm
COUNTER no.1 (s N) RESET
VIN = VFB = VREF x (duty cycle)
f= (duty cycle) X th
TL/Hf5682-3
t d Is xt V
Countin Counter No.1--.,..u,Ldy.ty-T,t,)x-htc,)iN
FIGURE 1. Analog Loop Schematic Pulse Modulation AID Converter
IOLSGGV
ADD3701
General information
The timing diagram, shown in Figure a gives operation for
the tree running mode. Free running operation is obtained
by connecting the Start Conversion input to logic "I'' NCC).
In this mode the analog input is continuously converted and
the display is updated at a rate equal to 129,024 X Him.
The rising edge of the Conversion Complete output indi-
cates that new information has been transferred from the
internal counter to the display latch. This information will
remain in the display latch until the next low-to-high tran-
sition of the Conversion Complete output. A logic "I " will be
maintained on the Conversion Complete output for a time
equal to 128 M 1/IIN.
Figure 3 gives the operation using the Start Conversion in-
put. It is important to note that the Start Conversion input
and Conversion Complete output do not influence the actual
analog-to-digital conversion in any way.
Timing Waveforms
CONVERSION CYCLE
(INTERNAL SIGNAU
CONVERSION
"MN l mm
IZIJIDD a Illm -----_
tt8,M2 x Ilfm
Internally the ADD3701 is always continuously converting
the analog voltage present at its input. The Start Conversion
input is used to control the transfer of information from the
internal counter to the display latch.
An RS latch on the Start Conversion input allows a broad
range of input pulse widths to be used on this signal. As
shown in Figure s, the Conversion Complete output goes to
a logic "ty' on the rising edge of the Start Conversion pulse
and goes to a logic "I " some time later when the new con-
version is transferred from the internal counter to the dis-
play latch. Since the Start Conversion pulse can occur at
any time during the conversion cycle. the amount of time
from Start Conversion to Conversion Complete will way.
The maximum time is 129,024 x1/tm and the minimum time
is 512x 1 Ile.
- l-ttum:
COMPLETE
convansmu convznsmu
STARTS inns
TLfHf5682-4
FIGURE 2. Conversion Cycle Ttming Diagram for Free Running Operation
convznsmu CYCLE
(IHIEHNM smut) I I I I
r'"' II.
sum couvensuou I . I I '
couvmsmn '
compute - ----
TUH/5682-5
FIGURE 3. Conversion Cycle Tlmlng Diagram Operating wlth Start Converslon Input
Applications
SYSTEM DESIGN CONSIDERATIONS
Perhaps the most important thing to consider when design-
ing a system using the ADD37OI is power supply noise on
the Vcc and ground lines. Because a single power supply is
used and currents in the 300 mA range are being switched,
good circuit layout techniques cannot be overemphasized.
Great care has been exercised in the design of the
ADD3701 to minimize these problems but poor printed cir-
cuit layout can negate these features.
Figures 4, 5, and 6 show schematics of DVM systems. An
attempt has been made to show, on these schematics, the
proper distribution for ground and Vcc. To help isolate digi-
tal and analog portions of the circuit, the analog Vcc and
ground have been separated from the digital Vcc and
ground. Care must be taken to eliminate high current from
flowing in the analog Vcc and ground wires. The most effec-
tive method of accomplishing this is to use a single ground
point and a single Vcc point where all wires are brought
together. In addition to this the conductors must be of suffi-
cient size to prevent signiMant voltage drops.
To prevent switching noise from causing litter problems, a
voltage regulator with good high frequency response is tttNF
essary. The LM309 and the LM340-5 voltage regulators all
function well and are shown in Figures 4, 5, and 6. Adding
more filtering than is shown will in general increase the jitter
rather than decrease it.
The most important characteristics of transients on the V00
line is the duration of the transient and not its amplitude.
Figure 4 shows a DPM system which converts 0 to +3.999
counts operating from a non-isolated power supply. in this
configuration the sign output could be + (logic "1") or -
(logic "o") and it should be ignored. Higher voltages could
be converted by placing a fixed divider on the input; lower
voltages could be converted by placing a fixed divider on
the feedback, as shown in Figure 5.
Figures 5 and 6 show systems operating with an isolated
supply that will convert positive and negative inputs. 60 Hz
common mode input becomes a problem in this configura-
tion and a transformer with an electrostatic shield between
primary and secondary windings is shown, The necessity for
using a shielded transformer depends on the performance
requirements and the actual application.
The filter capacitors connected to VFB (pin 14) and VFLT
(pin 11) should be low leakage. in the application examples
shown every 1.0 M of leakage current will cause 0.1 mV
error (1.0x 10-9A X 100 kn----0.1 mV). If the leakage cur-
rent in both capacitors is exactly the same no error will re-
sult since the source impedances driving them are matched.
LOLSGGV
ADD3701
______ _‘
'____..
2V REFERENCE
“Ill ‘
ADD3701
COIV "
AIALDI tree "‘
Um“) -
.n Jto
CtllRPL ETE -
" ' um
1: mice
NOTES:
1. ALL HESISTORS 1/. WATT t 5% UNLESS OTHERWISE SPECIFIED
2. ALL CAPACITORS t 10%
3. LOW LEAKAGE CAPACITOR REQUIRED.
Figure 4. 3%-Dlgltal DPM, + 3.999 Count Full Scale
.—..— V: i a
R, + R2 R3 25
TL/H/5682—6
l— __________ —I
IV REFERENCE
r...,,'"-'-
Two: '1: ““E a
a . ! p-J
E, gems
gum >—_—J OFFSET
COMPLETE
DOIV C
tttttie'
ARAlOB Va; "
: n In In
4,51! 1,5“ 0
NOTES:
0" W ‘1'" 1 ALL RESISTORS 1 WATT 15% UNLESS OTHERWISE SPECIFIED
(um count) ' /‘
2. ALL CAPACITORS i 10%. TL/H/5682-7
a. Low LEAKAGE CAPACITOR REQUIRED.
R1 +H2
= Re i 250.
Flgure 5. 3%—Dlglt DPM, i 3.999 Counts Full Scale
l-OLSGCIV
ADD3701
,_ ___________
Lm zv n:nnuc: 1
[mAA AAA“
' - on |
i:+:>F Luau»: I
lulu ”a I
A m[ 232 : emu: fl
I 11 "II II III
1 22 ‘ 25 II 11
tt DIGIT l
ANALOG
DIEIT l
Hm I ms
L ----- -*‘ Annsm
GUARD >—-—
I "(I 21% [M
AIALOGV¢¢
COMPLETE
DFLO -
T6 ‘I—UU F
-f:I:§;c
NOTES:
g 1. ALL RESISTORS y. WATT i5% UNLESS OTHERWISE SPECIFIED
"" ' 2. ALL CAPACITORS $1099.
3.-LOW LEAKAGE CAPACITOR REQUIRED.
A R1 +92
4 = R3i250.
Figure 6. 3%-Dlglt DVM, Four Decade, 10.4v, 1 W, :t 40V, and :t 400V Full Scale
TL/H/5682-8
('==,',,=,=,,'i'f "o
DISPLAY
lbclufl
- DISPLAY 9.999 WHEN OVERFLOWED.
ALL DIGITS CAN ALSO BE BLANKED AT
OVERFLOW BY TYING OFL TO B1 ON THE
Figure 7. ADD3701 Driving quuld Crystal Display
TL/Hl5682-9
lOLEOGV
This datasheet has been :
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
ADD3701CCN - product/add3701ccn?HQS=TI-nu||-nu|l-dscataIog-df-pf-null-wwe
ADD3701CCN - product/add3701ccn?HQS=T|-nu||-nu|I-dscatalog-df—pf—nulI-wwe
ADD3701CCN - product/add3701ccn?HQS=T|-nu|I-nu|I-dscatalog-df—pf—nuII-wwe
