ADD3501CCN ,3 1/2 DIGIT DVM WITH MULTIPLEXED 7-SEGMENT OUTPUTElectrical Characteristics ADD3501
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ADD3501CCN
3 1/2 DIGIT DVM WITH MULTIPLEXED 7-SEGMENT OUTPUT
National
Semiconductor
ADD3501 314 Digit DVM with
Multiplexed 7-Segment Output
General Deseription
The ADD3501 monolithic DVM circuit is manufactured using
standard complementary MOS (CMOS) technology, A pulse
modulation analog-to-digital conversion technique is used
and requires no external precision components. In addition,
this technique allows the use of a reference voltage that is
the same polarity as the input voltage.
One 5V (TTL) power supply is required. Operating with an
isolated supply allows the conversion of positive as well as
negative voltages. The sign of the input voltage is automati-
cally determined and output on the sign pin. If the power
supply is not isolated. only one polarity of voltage may be
convened.
The conversion rate is set by an internal oscillator. The fre-
quency of the oscillator can be set by an external RC net-
work or the oscillator can be driven from an external fre-
quency source. When using the external RG network, a
square wave output is available. It is important to note that
great care has been taken to synchronize digit multiplexing
with the A/D conversion timing to eliminate noise due to
power supply transients.
The ADD350t has been designed to drive 7-segment multi-
plexed LED displays directly with the aid of external digit
buflers and segment resistors. Under condition of over-
range, the twttrtlow output will go high and the display will
read + OFL or -OFL, depending on whether the input volt-
age is positive or negative. In addition to this, the most sig-
nificant digit is blanked when zero.
A start conversion input and a conversion complete output
are included on all 4 versions of this product.
Features
I: Operates from single 5V supply
Converts 0V to 11.999V
Multiplexed 7-segment
Drives segments directly
No external precision component necessary
Accuracy specified over temperature
Medium speed - 200ms/conversion
Internal clock set with RC network or driven externally
Overrange Indicated by +0FL or -OFL display read-
ing and OFLO output
" Analog inputs in applications shown can withstand
i200 Volts
In ADD3501 equivalent to MM740935
Applications
II Low cost digital power supply readouts
:1 Low cost digital multimeters
'' Low cost digital panel meters
I: Eliminate analog multiplexing by using remote A/ D con-
verters
1: Convert analog transducers (temperature. pressure, dis-
placement, etc.) to digital transducers
Connection Diagram
Ilet - t " - Se
ANALOG Vcc - l " - St
k - a " -- k
Se -.- 4 " -- 6ND
Sb - 5 u - DIGITI (M50)
h - s " - DIG” 2
arm - , Aonasm " - DIGIT3
CINVERSION EDWLETE - ' tl - DIBITI ISO)
START CONVERSION - g " - tout
$ltrtg - m 19 - "I
VFILTER - 11 u - VREF
le-l - 12 17 - Sm
letl_1 " Iii - SW2
"e-a " 15 - ANALOG END
TL/Hf5681-1
Order Number ADD3501CCN
See NS Package Number N283
LOSSGOV
ADD3501
Absolute Maximum Ratings (Note1)
If Mllltary/Aerospace ttpetrified devlces are required,
please contact the National Semiconductor Sales
Package Dissipation at TA = 25"C
derate at 9JA(MAX)= 125°C/Watt
800 mW
4.5V to 6.0V
offlettmltttrittutttra for avaliabillty and apeteltltrationtr. above TA=25°C
Voltage at Any Pin -0.3V to Vcc + 0.3V Operating Voc Range
Operating Temperature Range (T A) -40t to + 85°C Absolute Maximum Vcc
ESD Susceptibility (Note 3) TBDV Lead Temp. (Soldering, 10 seconds)
Storage Temperature Range
Electrical Characteristics AD03501
4.75V S Vcc S 5.25V, -40'C s; TA 3 +85"C, unless otherwise specified.
-65°C to + 150°C
Symbol Parameter Conditions Mln Typ(2) Max Units
VIN“) Logical "I'' Input Voltage Vcc-- 1.5 V
VIN(O) Logical "o" Input Voltage 1.5 V
V0UT(0) Logical "0" Output Voltage lo = 1.1 mA
(All Digital Outputs except 0.4 V
Digit Outputs)
VOUT(0) Logical "o" Output Voltage IO = 0.7 mA o 4 V
(Digit Outputs) .
VOUT(1) Logical "I '' Output Voltage IO = 50 mA@TJ = 25'C Vcc = 5V Vcc -1.6 Vcc -1.3 V
(All Segment Outputs) lo= 30 rnA@Tu = 100°C VCC' 1.6 VCC-1.3 V
VOUT(1) Logical "I " Output Voltage lo = 500 WA (Digit Outputs)
(All Digital Outputs except lo = 360pA (Conv. Complete, Vcc - 0.4 V
Segment Outputs) + I -, Oflo Outputs)
[SOURCE Output Source Current VOUT= 1.0V 2 0 m A
(Digit Outputs) .
'IN(1) Logical 1 lnPut Current VIN = 1.5V 1.0 PA
(Start Conversion)
IMO) Logical 0 InRut Current V.” == 0V _ 1.0 " A
(Start Conversion)
ICC Supply Current Segments and Digits Open 0.5 10 mA
fosc Oscillator Frequency 0.6/80 kHz
fIN Clock Frequency 100 640 kHz
fc Conversion Rate fIN/64,512 conv./sec
fMUX Digit Mux Rate lel 256 Hz
tBLANK Inter Digit Blanking Time 1/(321MUX) sec
tscpw Start Conversion Pulse Width 200 DC ns
Not. 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may ocwr. DC and AC electrica! specifications do not apply when operating
the device beyond its tspecified operating conditions.
Note 2: All typicals given for TA = 25°C.
Note & Human body model, 100 pF discharged through a 1.5 kn resistor.
Electrical Characteristics ADD3501
tt = 5 conversions/second. tPC s; TA S 70°C, unless otherwise specified.
Parameter Conditions Mln Typ Max Units
Non-Linearity VIN = 0 - 2V Full Scale - 0.05 t 0.025 + 0.05 % of
Vm = 0 - 200mV Full Scale - 0.05 t 0.025 + 0.05 full scale
Quantization Error - 1 + 0 counts
Offset Error, VIN == 0V ', -0.5 + 1.5 + 3 mV
Rollover Error -0 + 0 counts
Analog Input Current TA = 25°C -5 l 0.5 + 5 M
(V IN + ' VIN -)
Block Diagram
ADDSSOI 3WDIglt DVM Block Diagram
JWMGIT
bhTCrt
81AM CDNV
DIGITAL TIMING
[nil II "tt EBNTRDL
tot MC"! MD!
, BIG" 2
mm MT ill! DIGIT I
mar! sun tmut I (LSD)
OVERFLW
"ti-ess
0mm "tt
CDIV CWKEY!
ANALOG Vc:
"tttttt
-y". Alum: cm
TLIH/5681-2
lOSECIClV
ADD3501
Theory of Operation
A schematic for the analog loop is shown in Figure h The
output of SW1 is either at VREF or zero volts, depending on
the state of the D flip-flop. It Q is at a high level
VOUT=VREF and if Q is at a low level Vour=0V. This volt-
age is then applied to the low pass filter comprised of R1
and C1. The output of this filter, VFB, is connected to the
negative input of the comparator, where it is compared to
the analog input voltage. VIN. The output of the comparator
is connected to the D input of the D flip-flop. Information is
then transferred from the D input to the Q and Q outputs on
the positive edge of clock. This loop forms an oscillator
whose duty cycle is precisely related to the analog input
voltage, VIN.
An example will demonstrate this relationship. Assume the
input voltage is equal to 0.500V. If the 0 output of the D flip-
flop is high then VOUT will equal VREF (2.000V) and VFB will
charge toward 2V with a time constant equal to R101. At
some time VFB will exceed 0.500V and the comparator out-
put will switch to 0V. At the next clock rising edge the 0
output of the D flip-tlop will switch to ground, causing Vow
to switch to 0V. At this time Vpg will start discharging toward
0V with a time constant Roth. When VFB is less than 0.5V
the comparator output will switch high. On the rising edge of
the next clock the 0 output of the D flip-tlop will switch high
and the process will repeat. There exists at the output of
SW1 a square wave pulse train with positive amplitude VREF
and negative amplitude 0V.
The DC value of this, pulse train is:
VOUT= VFtEFLr F)= VREF(duty cycle)
0~T+T0F
Schematic Diagram
The lowpass filter will pass the DC value and then:
VFB = VREF(duty cycle)
Since the closed loop system will always force VFB to equal
VIN. we can then say that:
VIN = VFe=VREF(dUW cycle)
i= (duty cycle)
The duty cycle is logically ANDed with the input frequency
tm. The resultant frequency f equals:
f-- (duty cycle) 8 (clock)
Frequency f is accumulated by counter no. 1 for a time de-
termined by counter no. 2. The count contained in counter
no. 1 is then:
f = (duty cycle) X (clock)
(clock)! N (clock)/ N
= - x N
For the ADD3501, N = 2000.
(oou nt) 1.=
swa tts
nor = VREF
COUNTER " I (+14) RESET
TL/H/5681-3
1hN--VFB--Vmirx(duty cycle)
t- (duty cycle) Xtm
(duty eytrle)xhn VIN X
Count In Counter Ntt.1----_-_'-l"''--_-'"
od N 'IN/ N VREF
Figure 1. Analog Loop Stthttmatitt
Pulse Modulation AID Converter
General Information
The timing diagram. shown in Figure 2, gives operation for
the free running mode. Free running operation is obtained
by connecting the Start Conversion input to logic "I" (Vcc).
In this mode the analog input is continuously converted and
the display is updated at a rate equal to 64,512 x trim.
The rising edge of the Conversion Complete output indi-
cates that new information has been transferred from the
internal counter to the display latch. This information will
remain in the display latch until the next Iow-to-high tram
sition of the Conversion Complete output A logic "1" will be
maintained on the Conversion Complete output for a time
equal to 64X 1/le.
Figure 3 gives the operation using the Start Conversion in-
put. It is important to note that the Start Conversion input
and Conversion Complete output do not influence the actual
analog-to-digital conversion in any way.
Timing Waveforms
flu Jllt
CONVERSION CYCLE
64,512 x Ilfm
84,000 it l/tm
Internally the ADDSSO1 is always continuously converting
the analog voltage present at its inputs. The Start Conver-
sion input is used to control the transfer of information tram
the internal counter to the display latch.
An RS latch on the Start Conversion input allows a broad
range of input pulse widths to be used on this signal. As
shown in Figure 3. the Conversion Complete output goes to
a logic "o" on the rising edge of the Start Conversion pulse
and goes to a logic "t" some time later when the new con-
version is transferred from the internal counter to the dis-
play latch. Since the Start Conversion pulse can occur at
any time during the conversion cycle. the amount of time
from Start Conversion to Conversion Complete will vary.
The maximum time is 64,512X1/tm and the minimum time
is 256X1/fm.
(INTERNAL SIGNAL)
----------- 54,258 lt 1/le
-- l-- Wm;
CONVERSION
COMPLETE I -
NEW CONVERSION
CONVERSION ENDS
STARTS l
TL/H/5681-4
Figure 2. Conversion Cycle Timing Diagram for Free Running Operation
CONVERSION CYCLE -
(INTERNAL SIGNAL) l I LI
r -1 I I .
START CONVERSION'. t , !
couveasiou I |""'"". I
COMPLETE - -- .... - -
TLIH/5881-5
Figure 3. Conversion Cycle Tlmlng Diagram Operating with Start Conversion Input
IOSSGOV
ADD3501
Applications
SYSTEM DESIGN CONSIDERATIONS
Perhaps the most important thing to consider when design-
ing a system using the ADD3501 is power supply noise on
the Vcc and ground lines. Because a single power supply is
used and currents in the 300 mA range are being switched,
good circuit layout techniques cannot be overemphasized.
Great care has been exercised in the design of the
ADD3501 to minimize these problems but poor printed cir-
cuit layout can negate these features.
Figures 4, ti, and 6 show schematics of DVM systems. An
attempt has been made to show, on these schematics, the
proper distribution for ground and Voc- To help isolate digi-
tal and analog portions of the circuit, the analog V00 and
ground have been separated from the digital VCC and
ground. Care must be taken to eliminate high current from
flowing in the analog I/cc and ground wires. The most effec-
tive method of accomplishing this is to use a single ground
point and a single Vcc point where all wires are brought
together. In addition to this the conductors must be of suffi-
cient size to prevent signifieant voltage drops.
To prevent switching noise from causing jitter problems, a
voltage regulator with good high frequency response is nec-
essary. The LM309 and the LM340-5 voltage regulators
both function well and are shown in Figures 4, 5, and 6.
Adding more filtering than is shown will in general increase
the litter rather than decrease it. The most important char-
acteristic of transients on the V00 line is the duration of the
transient and not its amplitude.
Figured shows a DPM system which converts 0V to 1.999V
operating from a non-isolated power supply. In this cortfigu-
ration the sign output could be + (logic "1") or - (logic
"ty') and it should be ignored. Higher voltages could be con-
verted by placing a fixed divider on the Input; lower vottages
could be converted by placing a fixed divider on the feed-
back, as shown in Figure 6.
Figures 5 and 6 show systems operating with an isolated
supply that will convert positive and negative inputs. 60 Hz
common mode input becomes a problem in this configure-
tion and a transformer with an electrostatic shield between
primary and secondary windings is shown. The necessity for
using a shielded transformer depends on the performance
requirements and the actual application.
The filter capacitors connected to VFB (pin 14) and VFLT
(pin 11) should be low leakage. In the application examples
shown every 1.0nA of leakage current will cause 0.1 mV er-
ror (1.0 X10-9Ax100k0 = 0.1mV). It the leakage current in
both capacitors is exactly the same no error witl result since
the source impedances driving them are matched.
"$353" I 430
_________ —fi
1V REFERENCE
II!“ In
mm 6ND
ADD3501
ADJUST (5)
SIGNAI
0 F L0
CONV -
COMPLEYE
ANALIIB Vee "
TAN', "
Itmt-l
TL/H/5681—6
NCTTES:
1. ALL RESISTORS ‘/. WATT 2t 5% UNLESS OTHERWISE
SPECIFIED.
2. ALL CAPACITORS i 10%.
3. LOW LEAKAGE CAPACITOR REQUIRED.
‘4‘ R1 + R2
Flgure 4. 3‘/3-Dlglt DPM, +1399 Volts Full Scale
= R3125n
IOEEGOV
ADD3501
IIEVAC
mm mm:
f— __________ —|
2V REFERENCE
DSIS‘IZ
sumo >-—
____..._-._l
ADJUST (5)
ANALOG
comur:
DIGIT J
OISIT 1
DIGIT I
Amunn Vcl:
n In I
COHV -
" ' 01h!
w m 21.99"
vl-) >
NOTES:
1. ALL RESISTORS V. WATT i 5% UNLESS OTHERWISE
SPECIFIED.
2. ALL CAPACITORS 110%.
3. LOW LEAKAGE CAPACITOR REQUIRED.
Figure 5. 31/2-Dlglt DPM, :t 1.999 Volts Full Scale
=n3125n
TL/H/5681 —7
mm ”5353"
l— —————————— _1
I IV nzrznsuc:
1 | umm r" _o
I A HI I
‘ i m m 2m: J mm A A A vs;
“2 I I
IMO" 11%|
IN!“ I10
IISVIC
200!) M
5 I5 n I: t! 20
26 21 In
IEUII 5m
DIGITJ
DIGIT C
- AIALDB
OFFSE1
ADJUSI
ADDBSO‘I
augnn >——_—.
Vcc q-
Amuoa Vcc "
COMPLETE -
swan =
1‘ J 11 II
III“ ‘ ‘OIX
NOTES:
INK 111% 1. ALL RESISTORS ‘/. WATT :t 5% UNLESS OTHERWISE
SPECIFIED.
y“ ; 2, ALL CAPACITORS 311096.
3. LOW LEAKAGE CAPACITOR REQUIRED.
' R1 + R2
Flgure 6. 3%-Dlglt DVM. Four Decade, : 0.2V, i 2V, 1 20V and 1; 200V Full Scale
TL/H/5881v8
'4 =Hai25n
IOSSGOV
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
ADD3501CCN - product/add3501ccn?HQS=TI-nu||-nu|l-dscataIog-df-pf-null-wwe
ADD3501CCN - product/add3501ccn?HQS=T|-nu||-nu|I-dscatalog-df—pf—nulI-wwe
ADD3501 - product/add3501?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
ADD3501 - product/add3501?HQS=T|-nu|I-null-dscatalog-df—pf—nuII—wwe
ADD3501 - product/add3501?HQS=T|-nu|I-null-dscatalog-df-pf-null-wwe
ADD3501CCN - product/add3501ccn?HQS=T|-nu||-nu|I-dscatalog-df—pf—nulI-wwe
