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ADCMP567BCPZ
Dual Ultrafast Voltage Comparator
Dual Ultrafast
Voltage Comparator
Rev. 0
FEATURES
250 ps propagation delay input to output
50 ps propagation delay dispersion
Differential PECL compatible outputs
Differential latch control
Robust input protection
Input common-mode range −2.0 V to +3.0 V
Input differential range ±5 V
ESD protection >3 kV HBM, >200 V MM
Power supply sensitivity >65 dB
200 ps minimum pulsewidth
5 GHz equivalent input rise time bandwidth
Typical output rise/fall of 165 ps
APPLICATIONS
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers and signal restoration
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Clock drivers
Automatic test equipment
FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
INPUT
INVERTING
INPUT
LATCH ENABLE
INPUT
INPUTFigure 1.
GENERAL DESCRIPTION The ADCMP567 is an ultrafast voltage comparator fabricated
on Analog Devices’ proprietary XFCB process. The device
features 250 ps propagation delay with less than 35 ps overdrive
dispersion. Overdrive dispersion, a particularly important
characteristic of high speed comparators, is a measure of the
difference in propagation delay under differing overdrive
conditions.
A fast, high precision differential input stage permits consis-
tent propagation delay with a wide variety of signals in the
common-mode range from −2.0 V to +3.0 V. Outputs are
complementary digital signals fully compatible with PECL 10 K
and 10 KH logic families. The outputs provide sufficient drive
current to directly drive transmission lines terminated in 50 Ω
to VDD − 2 V. A latch input is included, which permits tracking,
track-and-hold, or sample-and-hold modes of operation.
The ADCMP567 is available in a 32-lead LFCSP package.
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................5
Thermal Considerations..............................................................5
ESD Caution..................................................................................5
Pin Configuration and Function Descriptions.............................6
Timing Information.........................................................................8
Application Information..................................................................9
Clock Timing Recovery...............................................................9
Optimizing High Speed Performance........................................9
Comparator Propagation Delay Dispersion..............................9
Comparator Hysteresis..............................................................10
Minimum Input Slew Rate Requirement................................10
Typical Application Circuits.....................................................11
Typical Performance Characteristics...........................................12
Outline Dimensions.......................................................................14
Ordering Guide..........................................................................14
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS
Table 1. ADCMP567 ELECTRICAL CHARACTERISTICS (VCC = +5.0 V, VEE = −5.2 V, VDD = +3.3 V, TA = 25°C, unless otherwise noted.)
NOTE: Under no circumstances should the input voltages exceed the supply voltages. ABSOLUTE MAXIMUM RATINGS
Table 2. ADCMP567 Absolute Maximum Ratings Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
THERMAL CONSIDERATIONS The ADCMP567 LFCSP 32-lead package option has a θJA
(junction-to-ambient thermal resistance) of 27.2°C/W in
still air.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
VEE24NCVEEVCC
GND
–INA
+INAVCCVEENCVEE
GND
LEB
LEB14
VCC
VCC
+INB
–INB
GND
LEA
LEANC27
NC = NO CONNECT
ADCMP567
TOP VIEW
(Not to Scale)Figure 2. ADCMP567 Pin Configuration
Table 3. ADCMP567 Pin Descriptions
TIMING INFORMATION
50%
VREF± VOS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
Q OUTPUT
LATCH ENABLE
03633-0-003 Figure 3. System Timing Diagram
The timing diagram in Figure 3 shows the ADCMP567 compare
and latch features. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions APPLICATION INFORMATION The ADCMP567 comparators are very high speed devices.
Consequently, high speed design techniques must be employed
to achieve the best performance. The most critical aspect of any
ADCMP567 design is the use of a low impedance ground plane.
A ground plane, as part of a multilayer board, is recommended
for proper high speed performance. Using a continuous con-
ductive plane over the surface of the circuit board can create
this, allowing breaks in the plane only for necessary signal
paths. The ground plane provides a low inductance ground,
eliminating any potential differences at different ground points
throughout the circuit board caused by ground bounce. A
proper ground plane also minimizes the effects of stray
capacitance on the circuit board.
It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 µF electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors will reduce any potential
voltage ripples from the power supply. In addition, a 10 nF
ceramic capacitor should be placed as close as possible from the
power supply pins on the ADCMP567 to ground. These
capacitors act as a charge reservoir for the device during high
frequency switching.
The LATCH ENABLE input is active low (latched). If the
latching function is not used, the LATCH ENABLE input
should be attached to VDD (VDD is a PECL logic high), and the
complementary input, LATCH ENABLE, should be tied to
VDD − 2.0 V. This will disable the latching function.
Occasionally, one of the two comparator stages within the
ADCMP567 will not be used. The inputs of the unused
comparator should not be allowed to float. The high internal
gain may cause the output to oscillate (possibly affecting the
comparator that is being used) unless the output is forced into a
fixed state. This is easily accomplished by ensuring that the two
inputs are at least one diode drop apart, while also appropriately
connecting the LATCH ENABLE and LATCH ENABLE inputs
as described above.
The best performance is achieved with the use of proper PECL
terminations. The open emitter outputs of the ADCMP567 are
designed to be terminated through 50 Ω resistors to VDD −2.0 V,
or any other equivalent PECL termination. If high speed PECL
signals must be routed more than a centimeter, microstrip or
stripline techniques may be required to ensure proper transition
times and prevent output ringing.
CLOCK TIMING RECOVERY Comparators are often used in digital systems to recover clock
timing signals. High speed square waves transmitted over a
distance, even tens of centimeters, can become distorted due to
stray capacitance and inductance. Poor layout or improper
termination can also cause reflections on the transmission line,
further distorting the signal waveform. A high speed
comparator can be used to recover the distorted waveform
while maintaining a minimum of delay.
OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator amplifier, proper design and
layout techniques should be used to ensure optimal perform-
ance from the ADCMP567. The performance limits of high
speed circuitry can easily be a result of stray capacitance,
improper ground impedance, or other layout issues.
Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
ADCMP567. Source resistance in combination with equivalent
input capacitance could cause a lagged response at the input,
thus delaying the output. The input capacitance of the
ADCMP567 in combination with stray capacitance from an
input pin to ground could result in several picofarads of
equivalent capacitance. A combination of 3 kΩ source resistance
and 5 pF of input capacitance yields a time constant of 15 ns,
which is significantly slower than the sub 500 ps capability of
the ADCMP567. Source impedances should be significantly less
than 100 Ω for best performance.
Sockets should be avoided due to stray capacitance and induc-
tance. If proper high speed techniques are used, the ADCMP567
should be free from oscillation when the comparator input
signal passes through the switching threshold.
COMPARATOR PROPAGATION
DELAY DISPERSION The ADCMP567 has been specifically designed to reduce
propagation delay dispersion over an input overdrive range of
100 mV to 1 V. Propagation delay overdrive dispersion is the
change in propagation delay that results from a change in the
degree of overdrive (how far the switching point is exceeded by
the input). The overall result is a higher degree of timing
accuracy since the ADCMP567 is far less sensitive to input
variations than most comparator designs.
Propagation delay dispersion is a specification that is important
in critical timing applications such as ATE, bench instruments,
and nuclear instrumentation. Overdrive dispersion is defined
