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ADC912A
CMOS Microprocessor-Compatible 12-Bit A/D Converter
REV.B
CMOS Microprocessor-Compatible
12-Bit A/D Converter
FUNCTIONAL BLOCK DIAGRAMFigure 2.Transition Noise Cross Plot
FEATURES
Low Cost
Low Transition Noise between Code
12-Bit Accurate�1/2 LSB Nonlinearity Error over Temperature
No Missing Codes at All Temperatures
10 �s Conversion Time
Internal or External Clock
8- or 16-Bit Data Bus Compatible
Improved ESD Resistant Design
Latchup Resistant Epi-CMOS Processing
Low 95 mW Power Consumption
Space-Saving 24-Lead 0.3" DIP, or 24-Lead SOIC
APPLICATIONS
Data Acquisition Systems
DSP System Front End
Process Control Systems
Portable Instrumentation
GENERAL DESCRIPTIONThe ADC912A is a monolithic 12-bit accurate CMOS A/D
converter. It contains a complete successive-approximation A/D
converter built with a high-accuracy D/A converter, a precision
bipolar transistor high-speed comparator, and successive-
approximation logic including three-state bus interface for logic
compatibility. The accuracy of the ADC912A results from the
addition of precision bipolar transistors to Analog Devices’
advanced-oxide isolated silicon-gate CMOS process. Particular
attention was paid to the reduction of transition noise between
adjacent codes achieving a 1/6 LSB uncertainty. The low noise
design produces the same digital output for dc analog inputs
not located at a transition voltage, see Figures 1 and 2. NPN
digital output transistors provide excellent bus interface timing,
125 ns access and bus disconnect time which results in faster
data transfer without the need for wait states. An external
1.25 MHz clock provides a 10 µs conversion time.
In stand-alone applications an internal clock can be used with
external crystal.
An external negative five-volt reference sets the 0 V to 10 V
input range. Plus 5 V and minus 12 V power supplies result in
95 mW of total power consumption.
Figure 1.Code Repetition
ADC912A–SPECIFICATIONS(VDD = +5 V � 5%, VSS = –11.4 V to –15.75 V, VREFIN = –5 V, Analog Input O V to
10 V; External fCLK = 1.25 MHz; –40�C to +85�C applies to ADC912A/F unless otherwise noted.)NOTESGuaranteed by design.Converter inactive; CS, RD = High, AIN = 10 V.See Synchronizing Start Conversion information in Converter Operation Details. Typicals (typ) are median values measured at 25°C. See Typical Performance
Characteristics for additional information.
Specifications subject to change without notice.
3k�CL
DGND
DBN
A. HIGH-Z TO VOH (t3)
AND VOL TO VOH (t6)
3k�
DGND
DBN
B. HIGH-Z TO VOL (t3)
AND VOH TO VOL (t6)
Figure 3. Load Circuits for Access Time
3k�10pF
DGND
DBN
A. VOH TO HIGH-Z
10pF
3k�
DGND
DBN
B. VOL TO HIGH-Z Figure 4. Load Circuits for Output Float Delay
Figure 5.Parallel Read Timing Diagram, Slow-Memory
Mode (HBEN = LOW)
TIMING CHARACTERISTICS1, 2(VDD = +5 V � 5%, VSS = –11.4 V to –15.75 V, VREFIN = –5 V, Analog Input 0 V to 10 V;
External fCLK = 1.25 MHz; –40�C to +85�C applies to ADC912A/F unless otherwise noted. See Figures 5 to 8.)Data Access Time after READ
Read Pulsewidth
Bus Disconnect Time
NOTESGuaranteed by design.All input control signals are specified with tR = tF = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.t3, t4, and t6 are measured with the load circuits of Figure 3 and timed for and output to cross 0.8 V or 2.4 V.t7 is the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 4.
Specifications subject to change without notice.
TIMING DIAGRAMSFigure 7.Parallel Read Timing Diagram, ROM Mode
(HBEN = LOW)
ADC912A
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADC912A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS(TA = 25°C, unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
VREFIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .VSS to VDD
AGND to DGND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
Digital Input Voltage to DGND,
Pins 17, 19–21 . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND,
Pins 4–11, 13–16, 18, 22 . . . . . . . . .–0.3 V to VDD + 0.3 V
Table I. Analog Input to Digital Output Code Conversion*The symbol”φ” indicates a 0 or 1 with equal probability.
Operating Temperature Range
Extended Industrial: ADC912A/F . . . . . . .–40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .300°C
Maximum Junction Temperature (TJ max) . . . . . . . . . .150°C
Package Power Dissipation . . . . . . . . . . . . . .(TJ max–TA)/θJA
Thermal Resistance θJA
Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57°C/W
SOIC-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70°C
ORDERING GUIDE
WAFER TEST LIMITSNOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
(@ VDD = +5 V, VSS = –12 V or –15 V, VREF = –5 V, AIN = 0 V to 10 V, and TA = 25�C, unless otherwise noted.)C2C2C2C2
10V
–5V
+5V
–15V
R = 10�
C1 = 0.01�F
C2 = 4.7�F
NC = NO CONNECT
POWER SUPPLY SEQUENCE:
+5V, –15V, –5V, +10VFigure 9.Burn-In Circuit
ADC912A
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONFigure 10.Basic Connection Diagram
TPC 1.Nonlinearity Error vs. Digital
Output Code
TPC 4.Supply Current vs.
Temperature
TPC 7.Code Repetition
TPC 2.Offset Error vs. Temperature
TPC 5.Power Dissipation vs. CLK IN
Frequency
TPC 8.Transition Noise Cross Plot
TPC 3.Gain Error vs. Temperature
TPC 6.Digital Output Current vs.
Output Voltage
TPC 9.Linearity Error vs. Conversion
Time
ADC912A
CIRCUIT CHARACTERISTICSThe characteristic curves provide more complete static and
dynamic accuracy information necessary for repetitive sampling
applications often used in DSP processing. One of the impor-
tant characteristic curves provided displays integral nonlinearity
error (INL) versus output code with a typical value of ±1/4 LSB.
Another very important characteristic associated with INL is the
transition noise shown in the transition noise cross plot. The
ADC912A offers extremely small, ±1/6 LSB, transition noise
which maintains the system signal-to-noise ratio in DSP processing
applications. Code repetition plots show the precision internal
comparator of the ADC912A making the same decision every
time for dc input voltages. Code repetition along with no miss-
ing codes assures proper performance when the ADC912A is
used in servo-control systems.
CONVERTER OPERATION DETAILSThe CS, RD, and HBEN digital inputs control the start of
conversion. A high-to-low on both CS and RD initiate a conver-
sion sequence. The HBEN high-byte-enable input must be low
or coincident with the read RD input edge. The start of conver-
sion resets the internal successive approximation register (SAR)
and enables the three-state outputs. See Figure 11. The busy
line is active low during the conversion process.
Figure 11. Simplified Analog Input Circuitry of ADC912A
During conversion, the SAR sequences the internal voltage
output DAC from the most significant bit (MSB) to the least
significant bit (LSB). The analog input connects to the
comparator via a 5 kΩ resistor. The DAC, which has a 2.5 kΩ
output resistance, connects to the same comparator input.
The comparator, performing a zero crossing detection, tests the
addition of successively weighted bits from the DAC output
versus the analog input signal. The MSB decision occurs 200 ns
after the second positive edge of the CLK IN following conver-
sion initiation. The remaining 11-bit trials occur after the next
11 positive CLK IN edges. Once a conversion cycle is started it
cannot be stopped or restarted, without upsetting the remaining
bit decisions. Every conversion cycle must have 13 negative and
positive CLK IN edges. At the end of conversion the compara-
tor input voltage is zero. The SAR contains the 12-bit data
word representing the analog input voltage. The BUSY line
returns to logic high, signaling end of conversion. The SAR
transfers the new data to the 12-bit latch.
SYNCHRONIZING START CONVERSIONAligning the negative edge of RD with the rising edge of CLK
IN provides synchronization of the internal start conversion
signal to other system devices for sampling applications.
When the negative edge of RD is aligned with the positive edge
of CLK IN, the conversion will take 10.4 microseconds. The
minimum setup time between the negative edge of CLK IN and
the negative edge of RD is 180 ns. Without synchronization the
conversion time will vary from 12.5 to 13.5 clock cycles. See
Figure 12.
Figure 12.External Clock Input Synchronization
POWER ON INITIALIZATIONDuring system power-up the ADC912A comes up in a random
state. Once the clock is operating or an external clock is applied,
the first valid conversion begins with the application of a high-
to-low transition on both CS and RD. The next 13 negative
clock edges complete the first conversion, producing valid data
at the digital outputs. This is important in battery-operated
systems where power supplies are shut down between measure-
ment times.
DRIVING THE ANALOG INPUTDuring conversion, the internal DAC output current modulates
the analog input current at the CLK IN frequency of 1.25 MHz.
The analog input to the ADC912A must not change during the
conversion process. This requires an external buffer with low
output impedance at 1.25 MHz. Suitable devices meeting this
requirement include the OP27, OP42, and the SMP-11.
Figure 13.ADC912A Simplified Internal Clock Circuit
