ADC16DV160 ,Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs SNAS488H –AUGUST 2009–REVISED FEBRUARY 2013PIN DESCRIPTIONSPin(s) Name Type Function and Connectio ..
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ADC16DV160
Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs
ADC16DV160
www.ti.com SNAS488H –AUGUST 2009–REVISED FEBRUARY 2013
ADC16DV160 Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS
Outputs
Checkfor Samples: ADC16DV160
1FEATURES APPLICATIONS Low Power Consumption • Multi-carrier, Multi-standard Base Station
Receivers• On-Chip Precision Reference and Sample-and-
Hold Circuit – MC-GSM/EDGE, CDMA2000, UMTS, LTE
and WiMAX• On-Chip Automatic Calibration During Power- • HighIF Sampling Receivers Dual Data Rate LVDS Output Port • Diversity Channel Receivers Dual Supplies: 1.8V and 3.0V Operation • Test and Measurement Equipment Selectable Input Range: 2.4 and 2.0 VPP • Communications Instrumentation Sampling Edge Flipping with Clock Divider by • Portable Instrumentation Option
DESCRIPTION• Internal Clock Divide by1or2The ADC16DV160isa monolithic dual channel high
• On-Chip Low Jitter Duty-Cycle Stabilizer performance CMOS analog-to-digital converter
• Power-Down and Sleep Modes capableof converting analog input signals into 16-bit
Output Fixed Pattern Generation digital wordsat rates upto 160 Mega Samples Per
Second (MSPS). This converter usesa differential,
• Output Clock Position Adjustment pipelined architecture with digital error correction and
• 3-Wire SPI an on-chip sample-and-hold circuitto minimize power
• Offset Binaryor 2's Complement Data Format consumption and external component count while
providing excellent dynamic performance. Automatic
• 68-Pin VQFN Package (10x10x0.8, 0.5mm Pin- power-up calibration enables excellent dynamic
Pitch) performance and reduces part-to-part variation, and
the ADC16DV160 can be re-calibratedat any time
KEY SPECIFICATIONS through the 3-wire Serial Peripheral Interface (SPI).
Resolution:16 Bits An integrated low noise and stable voltage reference
and differential reference buffer amplifier eases board
• Conversion Rate: 160 MSPS level design. The on-chip duty cycle stabilizer with
• SNR (@FIN=30 MHz):78 dBFS (typ) low additive jitter allowsa wide rangeof input clock
76 dBFS (typ) duty cycles without compromising dynamic
performance.A unique sample-and-hold stage yields
(typ) a full-power bandwidth of 1.4 GHz. The interface
MHz):89 dBFS (typ) between the ADC16DV160 anda receiver block can
GHz optimized via fixed pattern clock position features. The
digitalis provided data rate LVDS outputs– making 10 mm VQFN The on dual power supplies of +1.8V anda
power-down featureto powerto
(-40°C~ 85°C) very low levels while fast full
operation.
