ADC1021CCJ-1 ,10-BIT uP COMPATIBLKE A/D CONVERTERSFeatures
I ADC1001 is pin compatible with ADC0801 series 8-bit
A/ D converters
I Compatible ..
ADC1025BCJ-1 ,10-BIT uP COMPATIBLE A/D CONVERTERSElectrical Characteristics The following specifications applyforVcc = SV, VREF = 5V, IGLK = 1.8 MHz ..
ADC1025CCJ-1 ,10-BIT uP COMPATIBLE A/D CONVERTERSFeatures I Linearity Error :1/2 LSB and 4cl LSB
I Easy interface to all microprocessors I Conversi ..
ADC10321CIVT ,10-Bit, 20MSPS, 98mW A/D Converter with Internal Sample and HoldGeneral Descriptionn Tri-State OutputsThe ADC10321 is a low power, high performance CMOSn TTL/CMOS ..
ADC1034 ,10-Bit Serial I/O A/D Converters with Analog Multiplexer and Track/Hold FunctionFeaturesY TMSerial I/O (MICROWIRE compatible)The ADC1031, ADC1034 and ADC1038 are 10-bit succes-Ysi ..
ADC1038CIN ,10-Bit Serial I/O A/D Converters with Analog Multiplexer and Track/hold FunctionElectrical Characteristics= = = =The following specifications apply for V +5.0V, V +4.6V, f 700 kHz ..
ADUC848BSZ8-5 , MicroConverter® Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
ADUM1100BRZ , iCoupler Digital Isolator
ADUM1100BRZ-RL7 , iCoupler Digital Isolator
ADUM1100UR ,iCoupler Digital IsolatorSPECIFICATIONSFor ADuM1100AR3Minimum Pulse Width PW 40 ns C = 15 pF, CMOS Signal LevelsL4Maximum Da ..
ADUM1100UR-RL7 ,iCoupler Digital Isolatorcharacteristics superior toLow Power Operation alternatives such as optocoupler devices.5 V Operati ..
ADUM1100URZ , iCoupler Digital Isolator
ADC1021CCJ-ADC1021CCJ-1
10-BIT uP COMPATIBLKE A/D CONVERTERS
ADC1001/ADC1021
National
Semiconductor
ADC'f001fADtM021 10-Bit MP Compatible AID Converters
General Description
The ADC1001 and ADC1021 are CMOS, 10-bit successive
approximation A/D converters. The 20-pin ADC1001 is pin
compatitole with the ADC0801 8-bit A/D family. The 10-bit
data word is read in two 8-bit bytes, formatted left justified
and high byte first. The six least significant bits of the sec-
ond byte are set to zero, as is proper for a 16-bit word.
The 24-pin ADC1021 outputs to bits parallel and is intended
for interface to a 16-bit data bus.
Differential inputs provide low frequency input common
mode rejection and allow offsetting the analog range of the
converter. In addition, the reference input can be adjusted
enabling the conversion of reduced analog ranges with 10-
bit resolution.
Features
a ADC1001 is pin compatible with ADC0801 series 8-bit
A/ D converters
l: Compatible with NSCBOO and 8080 p.P derivatives-no
interfacing logic needed
I: Easily interfaced to 6800 p.P derivatives with minimal
external logic
I: Differential analog voltage inputs
tt Logic inputs and outputs meet both MOS and TTL volt-
age level specifications
n Works with 2.5V (LM336) voltage reference
I: On-chip clock generator
I: 0V to 5V analog input voltage range with single 5V sup-
II Operates ratiometrically or with 5 VDC, 2.5 VDC, or ana-
log span adjusted voltage reference
a 0.3" standard width 20-pin DIP package or 24 pins with
10-bit parallel output
Key Specifications
" Resolution 10 bits
II Linearity error _ tl LSB
tt Conversion time 200;).5
Connection Diagrams
ADC1001 (for an 8-bit data bus)
Dual-ln-Llne Package
ADC1021 (for all 10-blt outputs In parallel)
Duai-In-Llne Package
- V - V
(3-1 20 "-vcc(0ft ver) 6- I 24 -vcc(on vets)
[tio-a 19 -cut R 'Ti-t 23 -cu< R
Fe-s 18- anz o Wt-s 12-o'
CLKiN-4 "- ans 0 CLK m-I. 2t--o'
m_rR-s 1s- arr4 o m-s 20-irt2
YW)- 6 15 - an 5 o vw)- s 19 -irf3
vm(-)- 7 14 - an s o hd-)- 7 18 r-BiT4
AGND-B Ist- BIT7 o AGND-B 17-8ff5
vesrf2-- 9 12 - an a an O(LSB) vm/z-d , 16 -8IT6
0 GND- 10 l1-(MSB)BIT ll BIT1-ID 15 -8IT7
123m 2&5“: (LsB)illT0-1t 14 -8it8
TL/H15675-11 i) GND- 12 13 -8IT9 (USB)
Top Vlew
TL/H/5675-12
Top View
'TRI-STATE output buffers which output t) during TO.
Ordering Information
Temperature Range 0°C to + Ttr'tt -40°c to + 85''tt
Order Number ADC1001CCJ-1 ADC1021CCJ-1 ADCtOO1CCJ ADC1021CCJ
Package Outline J20A J24A J20A J24A
Absolute Maximum Ratings (Noles1&2)
" MllttaryfAerosparm ttperemttd devices are required,
please contact the National Semiconductor Sales
offitxtfDitttrmutorrt for availability and spedflcatlons.
Supply Voltage (V00) (Note 3) 6.5V
Logic Control Inputs -0.3V to + 18V
Voltage at Other Inputs and Outputs - 0.3V to (Voc + 0.3V)
Storage Temperature Range -65''C to + 150'G
Package Dissipation at TA = 25'C 875 mW
Lead Temp. (Soldering, 10 seconds) 300'C
ESD Susceptibility (Note 10) 800V
Converter Characteristics
Operating Conditions (Notes1&2)
Temperature Range
ADC1001CCJ
ADC1021CCJ
ADC1001CCJ-1
ADC1021CCJ-1
Range of Vcc
TMiN STASTMAX
-40'CsTAs; + 85'C
0°CSTAS +70'C
4.5 VDC to 6.3 VDC
Converter Speretflttationr. Vcc--- 5 VDC, VREFIZ = 2.500 VDC, TWN sTA STMAX and ttxx = 410 kHz unless otherwise specified.
Parameter Conditions Mln Typ Max Unlts
ADC1001C, ADC1021C:
Linearity Error AI LSB
Zero Error t 2 LSB
FulM9eale Error , 2 LSB
Total Ladder Resistance (Note 9) Input Resistance at Pin 9 2.2 4.8 Kn
Analog Input Voltage Range (Note 4) V( +) or V( -) GND - 0.05 Vcc + 0.05 ' VDC
DC Common-Mode Error Over Analog Input Voltage Range i V. LSB
Power Supply Sensitivity Voc = 5 Voc d: 5% Over * V. LSB
Allowed VIN(+) and Vmd-)
Voltage Range (Note 4)
AC Electrical Characteristics
11mlng SpeeMttatlortst Voc= 5 VDC and TA=25"C unless otherwise specified.
Symbol Parameter Conditions Mln Typ Max Units
Te Conversion Time (Note 5) 80 90 1HCLK
fCLK=410 kHz 196 219 p8
fCLK Clock Frequency (Note 8) 100 1260 kHz
Clock Duty Cycle 40 60 %
CR Conversion Rate In Free-Running INT R tied to WA with 4600 conv/s
Mode tXr---0Vrxy {CLK=41O kHz
twtWA)c Width of iiim Input (Start Pulse tB----- 0 Voc (Note 6) 1 50 ns
Width)
tACC Access Time (Delay from CL = 100 pF 170 300 ns
Falling Edge of Am to Output
Data Valid)
t1”. tOH TRI-STATE'D Control (Delay CL == 10 pF, RL = 10k 125 200 ns
from Rising Edge of 'ro to (See TRI-STATE Test
Hi-Z State) Circuits)
ho tm Delay from Falling Edge 300 450 ns
of wrt" or T175 to Reset of INTR
hrs INTH to 1st Read Set-Up Time 550 400 ns
Cm Input Capacitance of Logic 5 7.5 pF
Control Inputs
Cour TRI-STATE Output 5 7.5 pF
Capacitance (Data Buffers)
lZOl-OGV/ l-OOl-OCIV
ADC1001/ADC1021
DC Electrical Characteristics
The following specifications apply for Vcc= 5 Voc and TMINSTAS TMAX, unless otherwise speeified.
Symbol I Parameter L Conditions I Min I Typ Max Units
CONTROL INPUTS [Nota: CLK IN is the input of a Schmitt trigger circuit and is therefore specified separatelyl
VIN (1 ) Logical "I " Input Voltage Vcc = 5.25 VDC 2.0 15 VDC
(Except CLK IN)
VIN (0) Logical "o" Input Voltage Vcc = 4.75 VDc 0.8 Vac
(Except CLK IN)
IIN (1) Logical "1" Input Current VIN: 5 VDC 0.005 1 psAtoto
(All Inputs)
IN (0) Logical 'T'' input Current VIN --- 0 Voc - 1 - 0.005 ”ADC
(All Inputs)
CLOCK IN
VT+ CLK IN Positive Going 2.7 3.1 3.5 V90
Threshold Voltage
VT- CLK IN Negative Going 1.5 1.8 2.1 VDG
Threshold Voltage
VH CLK IN Hysteresis 0.6 1.3 2.0 VDC
(VT + ) -- (VT - ,
OUTPUTS AND INTR
Vour(0) Logical "ty' Output Voltage tour = 1.6 mA, Vcc-- 4.75 VDC 0.4 VDC
VOUTU) Logical "t " Output Voltage lo = - 360 HA, Vcc = 4.75 VDC 2.4 VDc
lo= --10 pA,Vcc---4.75 VDC 4.5 VDC
IOUT TRI-STATE Disabled Output VOUT = 0.4 VDC 0.1 - 100 pADc
Leakage (All Data Buffers) VOUT = 5 VDC 0.1 3 MDC
ISOURCE VOUT Short to GND, TA= 25°C 4.5 6 mADC
lstNk VOUT Short to VCC. a--- 25°C 9.0 16 mADc
POWER SUPPLY
kx Supply Current (Includes fCLK = 410 kHz,
Ladder Current) VREF/2 = NC, TA = 25°C
and CS-- 1 2.5 5.0 mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise tspecified. The separate A GND point should always be wired to the D GND.
Note & A zener diode exists. internally, from Vcc to GND and has a typical breakdown voltage ot 7 VDC.
Note 4: For Wd-) VA+) the digital output code will be all zeros. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater than the Voc supply. Be careful. during testing at low Vcc levels (4.5V),
as high level analog inputs (5V) can cause this input diode to conttuth-espserally at elevated temperatures. and cause errors for analog Inputs near fullscale. The
spec allows so mV forward bias of either diode. This means that as long as the analog Vm does not exceed the supply voltage by more then 50 mV, the output
code will be correct, To achieve an absolute 0 VDc to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature
variations, initial tolerance and loading.
Note tk With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases ale proper to start the conversion process. The
start request is internally latched, see Figure t.
Note tk The cg input is assumed to bracket the W strobe input and therefore timing is dependent on the Wm pulse width. An arbitrarily wide pulse width will hold
the converter in a reset mode and the start of conversion is initiated by the low to high transition ot the W pulse (see Timing Diagrams).
Note 7: All typical values are for TA = 25°C.
Note 8.. Accuracy is guaranteed at tCLK=410 kHz. At higher clock frequencies accuracy can degrade.
Note tk The VREF/2 pin is the center point of a two resistor divider (each resistor is 2.4km connected from Vcc to ground. Total ladder input resistance is the sum
ot these two equal resistors.
Note 10: Human body model, 100 pF discharged through a 1.5 kn resistor.
Typical Performance Characteristics
Egay From Falling Edge of
RD to Output Data Valld
vs Load Capacitance
Loglc Input Threshold
' Voltage " Supply Voltage
ta' -ssot S YA . S
g 1.1 'd
3 " "ii >
t?, I a
g tS tH In
b- 9 g
ii'. F-
4.50 0.75 5.00 5.25 Mil 0 200 MO 000 MO 1000
vet -sVPNT1l0LTluiE (vac! lDAD WACITAHti IPF)
Output Current "
Temperature
tIATA 0
IUFFEBS
'snunce
Vour . tA Vac
OUTPUT CURRENT (MM
2 VOUT' " tttte
-M -25 , " " N 100 115
TA - AMBIENT TEMPERATURE (°C)
TRl-STATE Test Circuits and Waveforms
M _ MTA M
G ouvur
c= toe
aunu‘rs
TL/H/5675-3
vet Vee
Moe 7 l DATA
a ounu‘r
f l "ir-
TL/H/5675-5
CLK IN Schmlu Trip Levels
3 5 vs Supply Voltage
-M''t S TA §+125°C
4.50 4.15 5.00 5.25 5.50
let: -StlPf'LY VOLTAGE (vim)
TL/H15675-2
t1H, CL: 10 PF
- tr -.-...
Vcc w:
tmo 10%
VON 90%
TL/H15675-4
tr=20 ns
toro CL = " PF
TL/H/SBTS-S
IZOLOOV/ LOOLOGV
ADC1001/ADC1021
Timing Diagrams
COIVERQDI
tz-T,.....-.,.,--,,,,'''"
" -..jl
ttet _
- mmn _ ‘10:?"
a mu Is um m
um“. ummu. "
sum: or m: " "tlot BUSY N oumr umm
convtnrsn
-.-- t " I l tltrut INTERNAL Tc -
(um mm m nun)
(LAST DATA us not am» J mt ASSERTED
--e " Tux
TLIH/5875-1
Output Enable and Reset INTR
rim asset
a N - 'm N I
n m w 3 no no N /
mm mmm:Ga
aunu" -------- - --'-e'11f-----CiisrD---
- ‘IHI'OH
TLfHr5875-8
'The 24-pin ADC1021 outputs " 10 bits on each RD.
Note: All timing is measured from the 50% voltage points.
BYTE SEQUENCING FOR THE 20-PIN ADO1001
Byte a-Blt Data Bus Cttnttetttltttt
Order DB7 DB6 DBS DB4 DB3 DB2 DB1 080
Ist Bit9 Bit8 Bit? Bite Bits Bit4 Bita Bitt?
2nd Bit1Bit0 o o o o o o
Functional Description
The ADC1001, ADC1021 use an advanced potentiometric
resistive ladder network. The analog inputs, as well as the
taps of this ladder network, are switched into a weighted
capacitor array. The output of this capacitor array is the in-
put to a sampled data comparator. This comparator allows
the successive approximation logic to match the analog dif-
ference input voltage Ned+r-Vtrd-)l to taps on the R
network. The most significant bit is tested first and after 10
comparisons (80 clock cycles) a digital 10-bit binary code
(all “1"s=fulI-scale) is transferred to an output latch and
then an interrupt is asserted (W makes a high-to-low
transition). The device may be operated in the free-running
mode by connecting wTm to the W inut with t%---o. To
ensure start-up under all possible conditions. an external
CM pulse is required during the first power-up cycle. A con-
version in process can be interrupted by issuing a second
start command.
On the high-to-low transition of the WA input the internal
SAR latches and the shift register stages are reset. As long
as the c-s input and WR input remain low, the A/D will re-
main in a reset state. Conversion will start from t to 8 clock
periods after at Mast one of these inputs makes a Iow-to-
high transition.
A functional diagram of the A/D converter is shown in Fig-
ure t. All of the inputs and outputs are shown and the major
logic control paths are drawn in heavier weight lines.
The conversion is initialized by taking tts and WA simulta-
neously low. This sets the start tlip-flop (F/F) and the result-
ing "I '' level resets the 8-bit shift register, resets the Inter-
rupt (INTR) F/ F and inputs a "1 " to the D flop, F/F1. which
is at the input end of the 10-bit shift register. Internal clock
signals then transfer this "l" to the a output of F/F1. The
AND gate, GI, combines this "I " output with a clock signal
to provide a reset signal to the start F/F. It the set signal is
no longer present (either WA or tS is a "1") the start Fl F is
reset and the 10-bit shift register then can have the M"
511 Ile, - Vini+i
Anmom. nnmozt
10k 1liu-7
TL/H/5675-9
NOTE: Vmd-) should be biased so
that Vmd-)2t -0.05V when potentiometer
wiper is set at most negative
voltage position.
FIGURE 2. Zero Adjust Clrcult
clocked in, which allows the conversion process to contin-
ue If tho set signal were to still be present, this reset pulse
would have no effect and the 10-bit shift register would con-
tinue to be held in the reset mode. This logic therefore al-
lows for wide a and W signals and the converter will start
after at least one of these signals returns high and the inter-
nal clocks again provide a reset signal for the start F/F.
After the "I" is clocked through the 10-bit shift register
(which completes the SAR search) it causes the new digital
word to transfer to the TRI-STATE output latches. When
this XFER signal makes a high-to-low transition the one
shot fires, setting the lNTR FIF. An inverting buffer then
supplies the 'iRTrq output signal.
Note that this ff control of the INTR F/ F remains low tor
aproximately 400 ns. If the data output is continuously en-
abled ttrs and AO both held low), the "Nt-tA- output will still
signal the end of the conversion (by a high-to-low tran-
sition), because the tTCT input can control the t2 output of
the INTR Fl F even though the RESET input is constantly at
a "1" level. This W output will therefore stay low for the
duration of the 'E-T signal.
Men data is to be read, the combination of both Ug and
RD being tow will cause the INTR F/ F to be reset and the
TRI-STATE output latches will be enabled.
Zero and Full-Scale Adjustment
Zero error can be adjusted as shown in Figure P. VIN(+) is
forced to +2.5 mV (+1/2 LSB) and the potentiometer is
adjusted until the digital output code changes from 00 0000
0000 to 00 0000 0001.
Full-scale is adjusted as shown in Figure 3, with the VREF/2
input. With VIN (+) forced to the desired fuIl-scaie voltage
less 1% L883 NFS-ll/e LSBs), VREF/2 is adjusted until
the digital output code changes from 11 1111 1110 to 11
1 1 1 1 1 1 1 1.
(Vcci 5V
1k AWW. A001021
Vagr/Z
IN A M336
TL/H15675-10
FIGURE 3. Fuil-Scale Adjust
lZOLOOV/IOOLOGV
ADC1001/ADC1021
Typical Application
TRANSDUCER
nun moumnu
nvsn MW nwnso
mun: mm
ABCINI VII“) 1mLTME mm:
TL/H/5675-1
Block Diagram
mm momma
run Abb mm: mm
mrur m I
" "tttttttAt I , '
clncum a
nun " 3’" m
TL cm - t
G“ mm " tt
cu osc cu:
T 0 sun - - cu u
I; I v
Ittt ‘VBEF’G L uonm A A N
All! " "
A ", A sum couvsnsuon
, n nzcoom Af Q IF mn- '11"
= m = mn
"o C - t _ um A um R C
. (MTE tt L" mums "ttt
ip Q '
ttAtl - _ m a
“(mm " m r-N, tt
Irfio mu
VIN") "or
Ivrmuutuczn m: " 1
mm": -
VIN“, C cum" went:
Annm mm Ll
k-----------' _.I L
Almm um "tns
" mum comm MS"
"t'' - mmut mm:
mm l.. eg shown twice for clarity. TL/y06t06.-"
ttttte 2: SAR- Successive Approximation Register, FIGURE 1
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
ADC1021CCJ-1 - product/adc1021ccj-1?HQS=TI-nuIl-nulI-dscatalog-df-pf-nulI-wwe
ADC1021CCJ - product/adc1021ccj?HQS=T|-nu|I-nulI-dscatalog-df—pf-null-wwe
ADC1021CCJ-1 - product/adc1021ccj-1?HQS=T|—nuIl-nulI-dscatalog-df-pf-nulI-wwe
ADC1021CCJ - product/adc1021ccj?HQS=T|-nu|I-nuII-dscatalog-df—pf—nuIl-wwe
ADC1021CCJ-1 - product/adc1021ccj-1?HQS=TI-nuIl-nulI-dscatalog-df-pf-null-wwe
ADC1021CCJ - product/adc1021ccj?HQS=T|-nu|I-nulI-dscatalog-df—pf-null-wwe
