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ADC1005CCV-ADC1025BCJ-1-ADC1025CCJ-1
10-BIT uP COMPATIBLE A/D CONVERTERS
National '
Semiconductor
ADC1005/ADCt025 10-Bit MP Compatible A/ D Converters
General Description
The ADC1005 and ADC1025 are CMOS 10-bit successive
approximation A/D converters. The 20-pin ADC1005 out-
puts 10-bit data in a two-byte format for interface with 8-bit
microprocessors.
The 24-pin ADC1025 outputs 10 bits in parallel and is in-
tended for 16-bit data buses or stand-alone applications.
Both A-to-Ds have differential inputs to permit reiection of
common-mode signals, allow the analog input range to be
offset, and also to permit the conversion of signals not re-
ferred to ground. In addition, the reference voltage can be
adjusted, allowing smaller voltage spans to be measured
" Operates ratiometrically or with 5 VDc voltage refer-
ence or analog span adjusted voltage reference
a OV to 5V analog input voltage range with single
5V supply
a On-chip clock generator
I: TLL/MOS input/output compatbts
u tha'' standard width 20-pin DIP or 24-pin DIP with 10-
bit parallel output
I: Available in 20-pin or 28-pin molded chip carrier
package
with 10-bit resolution. Key Specifications
" Resolution 10 bits
Features a Linearity Error :1/2 LSB and :1 LSB
n Easy interface to all microprocessors n Conversion Time 50 M3
II Differential analog voltage inputs
Connection Diagrams
ADCIOOS (for an 8-bit data bus) ADC1025 (10-bit parallel outputs)
Dual-ln-Llne Package DuaMmLine Package
_ V - \J
CS- 1 cs- I 24 ,-h,
tTii- 2 'lj- 2 23 -cu
VTR- , FN- 3 22 -tf
cum- 1 uxm- 4 21 Lo.
R'fii-. 5 m- 5 20 -enz
Vmo)- s 'hm- s " -titt3
he)- 7 'K-p- 7 13 .-trt.
_ AGND-B "tm-l, 17-515
ht- s 'u- 9 " -ms
tMltl0-- 10 em- l0 1: -trr7
(Lsn)arro- 11 " '-irtt
TL/H/5261-t DGND- 12 IS -Bl19(MSB)
Top vlew TL/H/526t "
Top Vlew
ADC1005 Molded Chip Carrier Package ADc1025 Molded Chip Carrier Package
Q 2 2 Q Q . CH " " " "
g il, F, t't'i',, ii o il ti ti ti S ti
25 24 23 22 21 20 "
f " '-NC
cum -tlttr/t) cum 17 -lliT7
Vcc y-BlTB/BI'TMLSU) Vac " "-tliT8
ifs] C0isl0irt"/irrt1 Es " m-ttlt'
'S ‘MD 16 14 -oo11n
Mt Pym w 13 -tgro
cum 12 -an1
zlEcTE 5573911111
E 3 5 = TL/H15261-1B W L L I I I
, 2 - I D g B
Top View I 5 ' > TL/H/52151-2o
'TRI-STATE' output butters which output 0 during M Top VIBW
See Ordering Information
SZOLOGV/SOOLOOV
ADC1005/ADC1025
Absolute Maximum Ratings (Notes1&2)
If Mllltary/Aerospace tspelled devices are required,
please contact the Natlonal Semlttttndutttor Sales
OffltNr/Dltttrlbutttra for availability and specifications.
Supply Voltage (Vcc) 6.5V
Logic Control Inputs - 0.3V to +15V
Voltage at Other Inputs and Outputs - 0.3V to Vcc + 0.3V
Input Current Per Pin t 5 mA
Input Current Per Package i 20 mA
Storage Temperature Range - 65'C to + 150°C
Package Dissipation at TA = 25''C 875 mW
Lead Temperature
(Soldering, 10 seconds)
Dual-ln-Line Package (Plastic) 26ty'C
Dual-ln-Line Package (Ceramic) 300°C
Surface Mount Package
Vapor Phase (60 seconds) 21 tPC
Infrared (15 seconds) 220°C
ESD Susceptibility (Note 8) 800V
Operating Ratings (Notes1&2)
Supply Voltage (Vcc) 4.5V to 6.0V
Temperature Range TMN s TA sTMAx
ADC1005BJ, ADC10050J -55tscTAsc + 125°C
ADC1025BJ, ADC10250J _
ADC1005BCJ, ADC1OOSCCJ -4tPCscTAs; + MPC
ADC1025BCJ, ADC102500J
ADC1OOSBCJ-1, ADt91005tX1l-1 0°C STA s 70'C
ADC1025BCJ-1, ADC1 t125CCJ-1
ADC1005BCN, ADC1OOSCCN
ADC1025BCN, ADC1025CCN
ADC1005BCV, ADC1 OOSCCV
ADC1025BCV, ADC1025CCV
Electrical Characteristics The following specifications apply for Vcc = tN, VREF = 5V, tCLK = 1.8 MHz
unless otherwise specified. Boidface llmlts apply from Tum to TMAx: All other limits TA = T] = 25°C.
ADC10XSBJ, ADC10XSBCJ ADC10XSBCJ-1, ADC10X5tNhr1
ADC10X50J ADC10X560J ADC10XSBCN, ADC10X5CCH
P ar am at er c o n am 0 n s ADC10XSBCV, ADC10XSCCV li',',',',',
T Tested Design T Tested Design n ts
(N035) Llmlt Lltttit o'2' 5) Umlt Limit
(Note 6) (Note 7) (Note 6) (Note n
Converter Characteristics
Linearity Error (Note 3)
ADC10X58J. ADC10XSBCJ t 0.5 LSB
ADC10X5BCJ-1, BCN, BCV i 0.5 t 0.5 LSB
ADC10XSCJ. ADC10X5CCl t 1 LSB
ADC10XSCCJ-1, CCN, CCV * 1 i 1 LSB
Zero Error
ADC10X5BJ, ADC10XSBCJ l 0.5 LSB
ADC10XSBCJ-1, BCN, BCV 10.5 i 0.5 LSB
ADC10X50J, ADC10XSCCJ i 1 LSB
ADC10X5CX41, CCN, CCV t 1 i 1 LSB
Fullscale Error
ADC10XSBJ. ADC10XSBCJ , 0.5 LSB
ADC10XSBCJ-1, BCN, BCV i0.5 i 0.5 LSB
ADC10X5thl, ADC10XSCCJ i 1 LSB
ADC10X5Ctkl-t, CCN, CCV tl i 1 LSB
Reference MIN 4.8 2.2 4.8 2.4 2.2 kn
Input MAX 4.8 8.3 4.8 7.6 tha kn
Resistance
Common-Mode MIN V + V - Vcc + o.os Vcc+ 0.05 Vcc + 0.05 V
Input (Note 4) MAX trd ) or ed ) Gtltt- 0.05 GND-0.05 GHB-0.0S v
DC Common-Mode Over Common-Mode
Error Input Range l % l V. i % i1/4 i 'A LSB
P S l S iti . V = i "/
ower upp y ens: ivity V225: , 1fysis e i % i y. i % + Ya i V. LSB
Electrical Characteristics (Continued) The following tprtfifitaations apply for Vcc =-- 5V, VREF --- 5V, fCLK =
1.8 MHz unless otherwise specified. Boldface llmlta apply trom TMIN to Twut; All other limits TA = Ti = 25'C.
ADC1OXSBJ, ADC10XSBCJ ADC10X5BC,M, ADC10X5CCJ-1
ADC10X5BCN, ADC10X5CCN
ADC10X50J, ADC10XSCCJ ADC10XSBCV ADC10XSCCV len
Parameter Ctttttiltlontt ,
T Tested Design T Tested Design Unlta
(Nags) Limit Llmlt ("0:35) Llmit Llmlt
(Note 6) (Note n (Note 6) (Note 7)
Dc Characteristics
VIN“) Logical "I'' Input Vcc= 5.25V
Voltage MIN (except CLKIN) Rat 2.0 " V
vmm Logical "0" Input Vcc = 4.751/
Voltage MAX (Except CLKm ) ua, 0.8 tt.tt V
Ieot.ogical"1"lnput V|N=5.0V 1
Current M AX 0.005 1 0.005 1 p.A
lm. Logical "O" Input Ihr: = 0V - _ - - -
Current MAX 0.005 1 0.005 1 1 HA
VT+ (MINI, Minimum CLKIN
Positive going Threshold 3.1 2.7 3.1 2.7 2.7 V
Voltage
VT(MAX): Maximum CLKIN
Positive going Threshold 3.1 " 3.1 3.5 " V
Voltage
VT- (MIN), Minimum CLKIN
Negative going Threshold 1.8 1 .5 1.8 1.5 1 .5 V
Voltage
VT-tMAX), Maximum CLNN
Negative going Threshold 1.8 2. 1 1.8 2.1 2. 1 V
Voltage
VH(MIN): Minimum CLKm
Hysteresis (VT + "IT _) 1.3 0.6 1.3 0.6 0.6 V
VH(MAX): Maximum CLKIN
Hysteresis (VT+ AIT-) 1.3 2.0 1.3 2.0 2.0 v
Vourtly Logical "1 " Vcc--- 4.75V
Output Voltage MIN Iour-- -360 11A 2.4 2.8 2.4 V
Iour = - 10 MA 4.5 4.6 4.5 V
Vourtoy Logical "0" Vcc = 4.75V
Output Voltage MAX IOUT= 1.6 mA o.a 0.34 tha V
IOUT. TRI-STATE Output Vour = 0V - 0.01 - a - 0.01 - 0.3 - s PA
Current MAX Vour = 5V 0.01 3 0.01 0.3 a PA
'SOURCE' Output Source Vour = 0V - 14 - 6.5 - 14 - 7.5 - 0.5 tttA
Current MIN
fSINK. Output Sink VOUT= 5V 16 8.0 16 9.0 s.o mA
Current MIN
ICC, Supply Current fCLK = 1.8 MHz
1.5 1. 2.5
MAX Cg-- "I " 3 5 a mA
AC Electrical Characteristics The following speertications apply for Vcc = 5V, VREF = 5V,t, = tf = 20 ns
unless otherwise specified. Boldlaco limits apply from Tum to Ttsaw, All other limits TA -- T] = 25''C.
T Tested Design leit
Parameter Condltlons old',', leIt Umlt Unlts
(Note 6) (Note 7)
ttvo Clock FrequencyMlN 0.2 0.2 MHz
MAX 2.6 2.6 MHz
Clock Duty Cycle MIN 40 40 %
MAX 60 60 %
3-21 3
SZOlOGV/SOOI-OCIV
ADC‘IOOS/ADC1025
AC Electrical Characteristics The following specifications apply for Vcc = 5V, VREF = 5V,tr = tf = 20 ns
unless otherwise spsxrifiad. Boldface llmlts apply from TMIN to TMAX; All other limits TA = Ti = 25°C. (Continued)
Tested Design
Parameter Conditions Je 5) Limit lelt hm:
(Note 6) (Note T)
tty Conversion Time MIN 80 80 1/fCLK
MAX 90 90 1/fCLK
MIN fCLK=1.8 MHz 45 45 ’18
MAX tcut-- 1.8 MHz 50 50 p3
tmv-r-nc, Minimum W Pulse Width C-S--- 0 100 150 150 ns
tAcc, Access Time (Delay from falling ug = 0
edge of Am to Output Data Valid) CL-- 100 pF, RL = 2k 170 300 300 ns
t1H. tore, TRI-STATE Control (Delay RL-- 10k, CL-- 10 pF 125 200 ns
from Rising Edge of tTO to Hi-Z State) RL-- 2k, CL----- 100 pF 145 230 230 ns
twl, tm, Delay from Falling Edge of
ilffA or W to Reset of INTR 300 450 450 ns
tms, INTR to 1st Read Set-up Time 400 550 550 ns
Cm, Capacitance of Logic Inputs 5 7.5 pF
Cour, Capacitance of Logic Outputs 5 7.5 pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specificat'ons do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to ground.
Note 3: Linearity enor is defined as the deviation of the analog value, expressed in LSBs, trem the straight line which passes through the end points of the transfer
characteristic.
Note 4: For V,N(_)2V.N(+) the digital output code will be 00 0000 0000. Two on-chip diodes are tied to each analog Input which will forward conduct tor analog
input voltages one diode drop below gtound or one diode drop greater than Vcc supply. Be careful, during testing at low Voc levels (4.5V). as high level analog
inputs (5V) can cause this input diode to conduct, especially at elevated temperatures. and cause errors for analog inputs near full-scele. The spec allows 50 mV
forward bias of either diode. This means that as long as the analog Vm does not exceed the supply voltage by more than 50 mV, the output code will be correct. To
achieve an absolute o VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 hx; over temperature variations, initial tolerance
and loading.
Note s.. Typicals are at 25''C and represent most likely parametric norm.
Note 8: Tested and guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 7: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 8: Human body model, 100 pF discharged through a 1.5 kn resistor.
Functional Diagram
llllllllll
cu a cu m n
.i t- w
WNTIDL - m
ssuuma
OUTPUT
A "ll her D t0llt Vcc
mo BYTE
TUH/5261 -3
Typical Performance Characteristics
Delay from Falling Edge of
Loglc Input Threshold W) to Output Data Valid " CLK IN Schmltt Trip Levels
Voltage vs Supply Voltage Load Capacitance vs Supply Voltage
iE I son "
tf -sre f TR . F.
r- td 11
g, Mil b'
g if g L7
p, " 31n g
g g E 2.3
F, zoo g
" 1m "
'ar 5.15 5.00 5.25 s." a nu ma son um um 5.55 5.15 m E25 "
Vcc - sumv value: Wot) LOAD CAPACITANCE lpn Vcc - sumv vonAsE (vac)
Output Current vs Typical Linearity Error
Temperature vs Clock Frequency
' 1 v " "
7 It.. o 6 -55-c +125'c hrr "
R" DATA 'd ' .
5 Iurrsns I 0,4 tl
r, l i5 "
E i 333:5; It 'il',, 0
" = -o.2
' ' p, -o.4
a a -ihti
' "SINK h' -0.8
, Vuur . " Vnc - 1
-M -25 n 25 5a " 100 125 " 1.0 1.8 "
TA - AMBIENT TEMPERATURE Cir) CLOCK FREDUENCY [MHz] TUH/5261-4
Timing Diagrams
Start Conversion
MST DATA ms mm M F--- tg I
W Mst nm was NOT MM) * iu.,
TLfHf6261-5
Output Enable and Reset INTR
um RESET
M 15mm ls IN!) M N /
TR|~STATE® "
- q)... - - - - - BYTE --
OUWUTS
‘The 244rin ADC1025 outputs all 10 bits on each m5
Nola: All timing is measured from the 50% voltage points.
TL/H15261-6
SZOI-OGVISDOI-OOV
ADC1005/ADC1025
Timing Diagrams (Continued)
Byte Sequencing for the 20-Pln ADC1005
Byte 8-Blt Data Bus Connection
Order 037 DB6 DBS DB4 DB3 DB2 DB1 DBO
Ist Bit? Bite Bit? Bits Bit5 Bit4 Bit3 Bit2
2nd Bit 1 Bit O 0 o O o 0 0
Block Diagram
mu! mommn
run m. Loam mun
rnnmnm.
Mtttlrt cu '
mo- ulnn A ‘m
um , -
ttttttttttt 5- ",, a fl ',llWl'lir"'"
= I n: E tun
mere _ Q "', (:32?) f Jll%' "W
1" E P E
" ' ' "
u: = - u: n
Vmun db :21 II
li' an cu A
"a" Va:
Vince) T xrzn gl',
I'm unuzlcm All) i L
v - mm”: _
nu l mmu‘r uncut: um
"'llllllllll'"
_r-'-"ual-a..---o -LF- nmr
Amman!
-d L...
Baum tl ===c) “mm "Pttt
M mm": CDITRDL tttWT
Nola 1:63 shown twice tor clarity. -1'-- omnum TL/HI5261-11
Not. t. SAR = Successive Approximation Regimen
FIGURE 1.
Functional Description
1.0 GENERAL OPERATION
A block diagram of the A/D converter is shown in Figure 1
All of the inputs and outputs are shown and the major logic
control paths are drawn in heavier weight lines.
1.1 Converter Operation
The ADC1005. AtXM025 use an advanced potentiometric
resistive ladder network. The analog inputs, as well as the
taps of this ladder network are switched into a weighted
capacitor array. The output of this capacitor array is the in-
put to a sampled data comparator. This comparator allows
the successive approximation logic to match the analog in-
put voltage Ned+) - th‘n to tape on the R network.
The most significant bit is tested first and after 10 compari-
sons (80 clock cycles) a digital IO-bit binary code (all "1''s
= tull-scale) is transferred to an output latch.
1.2 Starting a Conversion
The conversion is initialized by taking ug and WA simulta-
neously low. This sets the start flip-flop (F/F) and the result-
ing "I" level resets the 10-bit shift register, resets the inter-
rupt (INTR) F/F and inputs tl "I " to the D flop, F/F1, which
is at the input end of the 10-bit shift register. Internal clock
signals then transfer this "I" to the Q ouput of F/F1. The
AND gate, G1, combines this "I " output with a clock signal
to provide a reset signal to the start F/F. If the set signal is
no longer present (either WA or ug is a "I'') the start Fl F is
reset and the 10-bit shift register then can have the "I''
clocked in, allowing the conversion process to continue. If
the set signal were still present, this reset pulse would have
no effect and the 10-bit shift register would continue to be
held in the reset mode. This logic therefore allows for wide
tXI and WM signals. The converter will start after at least
one of these signals returns high and the internal clocks
again provide a reset signal for the start F/F.
To summarize, on the high-to-low transition of the WA input
the internal SAR latches and the shift register stages are
reset. As long as the E input and Tm input remain low, the
Al D will remain in a reset state. Conversion will start after at
least one of these inputs makes a low-to-high transition.
1.3 Output Control
After the "I'' is clocked through the 10-bit shift register
(which completes the SAR search) it causes the new digital
word to transfer to the TRI-STATE output latches. When the
XFER signal makes a high-to-low transition the one shot
fires, setting the INTR FIF. An inverting buffer then supplies
the IRtm output signal.
Note that this fr control of the INTR F/F remains low for
approximately 400 ns. If the data output is continuously en-
abled ($ and ATO" both held low) the WW output will still
signal the end of the conversion (by a high-to-low tran-
sition). This is because the m input can control the Q
output of the INTR F/F even though the RESET input is
constantly at a "I'' level. This ITTTTq output will therefore
stay low for the duration of the SE_T signal.
Lvtysn data is to be mad, the combination of both ug and
RD being low will cause the INTR F/ F to be reset and the
TFll-STATE output latches will be enabled.
1.4 Free-Runnlng and Selt-Clocklng Modes
For operation in the tree-running mode an initializing pulse
should be used, following power-up, to ensure circuit opera-
tion. In this application, the ug input is grounded and the
WA input is tied to the wm output. This RM and IN-TA
node should be momentarily forced to logic low following a
power-up cycle to ensure start up.
The clock for the A/ D can be derived from the CPU clock or
an external RC can be added to provide self-clocking. The
CLK IN makes use of a Schmitt trigger as shown in Figure 2.
CLK ll
CLK INLp
' >4 te"
fCLK " 1 1 RC
FIGURE 2. Sell-Clocklng the AID
2.0 REFERENCE VOLTAGE
The voltage applied to the reference input of these convert-
ers define, the voltage span of the analog input (the differ.
ence between VIN(MAX) and VIN(MIN)) over which the 1024
possible output codes apply. The devices can be used in
either ratiometric applications or in systems requiring abso-
lute accuracy. The reference pin must be connected to a
voltage source capable of driving the reference input resist-
ance of typically 4.8 kn. This pin is the top of a resistor
divider string used for the successive approximation conver-
In a ratiometric system tFigure 3a) the analog input voltage
is proportional to the voltage used for the AID reference.
This voltage is typically the system power supply, so the
VREF pin can be tied to Vcc, This technique relaxes the
stability requirements of the system references as the ana-
log input and A/D reference move together maintaining the
same output code for a given input condition.
For absolute accuracy (Figure 3b), where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time and temperature stable voltage
source. The LM385 and LM336 reference diodes are good
low current devices to use with these converters.
The maximum value of the reference is limited to the Vcc
supply voltage. The minimum value, however. can be small
to allow direct conversions of transducer outputs providing
less than a 5V output span. Particular care must be taken
with regard to noise pickup, circuit layout, and system error
voltage sources when operating with a reduced span due to
the increased sensitivity of the converter (1 LSB equals
VREF/1024).
TL/H/5261-12
SZOLOOV/SOOLOOV
ADC1005/ADC1025
Functional Description (Continued)
‘VINHI
TLlH/5261-17
FIGURE 3a. Ratlttmetrltt
3.0 THE ANALOG INPUTS
3.1 Analog Differential Voltage Inputs and
CttmrttttrtNttdtt Rejection
The differential inputs of these converters reduce the ef-
fects of common-mode input noise, which is defined as
noise common to both selected '' + " and " -" inputs (60 Hz
is most typical). The time interval between sampling the
"+" input and the "-" input is half of an internal clock
period. The change in the oommon-mode voltage during this
short time interval can cause conversion errors. For a sinus-
oidal common-mode signal, this error is:
VERRORiMAX) = VPEAK (br fem) x iiTK
where fCM is the frequency of the common-mode signal,
VpEAK is its peak voltage value and fCLK is the clock fre-
quency at the CLK IN pin.
For a 60 Hz oommon-mode signal to generate a 1/4 LSB
error (1.2 mV) with the converter running at 1.8 MHz, its
peak value would have to be 1.46V. A common-mode signal
this large is much greater than that generally found in data
aquisition systems.
3.2 Input Current
Due to the sampling nature of the analog inputs, short dura-
tion spikes of current enter the "+ '' input and exit the "-"
input at the clock rising edges during the conversion. These
currents decay rapidly and do not cause errors as the inter-
nal comparator is strobed at the end of a clock period.
3.3 input Bypass Capacitors
Bypass capacitors at the inputs will average the current
spikes noted in 3.2 and cause a DC current to flow through
the output resistances of the analog signal sources. This
charge pumping action is worse for continuous conversions
with the VIN(H input voltage at full scale. For continuous
conversions with a 1.8 MHz clock frequency with the Ved +)
W- 2.5V
Mft Vuiu)
ting 2.6V
htt -i
Milli)
TL/H15261-18
FIGURE 3b. Absolute with a Reduced Span
input at 5V, this DC current is at a maximum of approximate-
ly 5 PA. Therefore, bypass capacitors should not be usedat
the analog inputs or the Vngppin for high resistance S0uro-
es (>1 kn). If input bypass capacitors are necessary for
noise filtering and high source resistance is desirable to
minimize capacitor size. the detrimental effects of the volt-
age drop across this input resistance, which is due to the
average value of the input current, can be eliminated with a
full-scale adjustment while tho given source resistor and in-
put bypass capacitor are both in place. This is possible be-
cause the average value of the input current is a linear func.
tion of the differential input voltage.
3.4 Input Source Resistance
Large values of source resistance where an input bypass
capacitor is not used, will not cause am it the input cur-
rents settle out prior to the comparison time. If a low pass
filter is required in the system, use a low valued series resis-
tor (S1 kn) for a passive RC section or add an op amp RC
active low pass filter. For low source resistance applications
($0.1 km a 4700 pF bypass capacitor at the inputs will
prevent pickup due to series lead induction of a long wire. A
1000. series resistor can be used to isolate this capacitor -
both the R and the C are placed outside the feedback loop
- from the output of an op amp, it used.
3.5 Noise
The leads to the analog inputs (pins t) and 7) should be kept
as short as possible to minimize input noise coupling. Both
noise and undesired digital clock coupling to these inputs
can cause system errors. The source resistance for these
inputs should, in general, be kept below 1 kn. Larger values
of source resistance can cause undesired system noise
pickup. input bypass capacitors. placed from the analog in-
puts to ground, can reduce system noise pickup but can
create analog scale errors, See section 3.2, 3.3, and 3.4 it
input filtering is to be used.
Functional Description (Continued)
4.0 OFFSET AND REFERENCE ADJUSTMENT
4.1 Zero Offset
The zero error of the A/D converter relates to the location
of the first riser of the transfer function and can be mea-
sured by grounding tho Vt--) input and applying a small
magnitude positive voltage to the V(+) input Zero error is
the difference between the actual DC input voltage that is
necessary to just cause an output digital code transition
from 00 0000 0000 to 00 0000 0001 and the ideal 1/2 LSB
value (1 /2 LSB = 2.45 mV for VREF = 5.0 VDC).
The zero of the A/D normally does not require adiustment.
However, for cases where VIN(MIN) is not ground and in
reduced span applications (VREF < 5V), an offset adjust-
ment may be desired. The converter can be made to output
an all zero digital code tor an arbitrary input by biasing the
AIDS "d-) input at that voltage. This utilizes the differen-
tial input operation of the AID.
4.2 Full Scale
The full-scale adjustment can be made by applying a differ-
ential input voltage that is 1% LSB down from the desired
analog fulI-scale voltage range and then adjusting the mag-
nitude ot the VREF input for a digital output code that is lust
changingfrom1111111110to1111111111.
4.3 Adjusting for an Arbitrary Analog
Input Voltage Range
If the analog zero voltage of the AID is shifted away from
ground (for example. to accommodate an analog input sig-
nal that does not go to ground), this new zero reference
should be properly adjusted first. A VIN(+) voltage that
equals this desired zero reference plus 1/2 LSB (where tho
LSB is calculated for the desired analog span, 1 LSB =
analog span/1024) is applied to selected " + 'r input and the
AOCWOE
ADCIOZS
Ilat-l Van
zero reference voltage at the corresponding "-'' input
should then be adjusted to just obtain the OOOHEX 001HEX
code transition.
The full-scale adjustment should be made [with the proper
Ved-) voltage applied] by forcing a voltage to the VIN(+)
input given by:
Vm(+) FS adl = VMAX - 1.5 [N-M-A-is-L-vhs-
where VMAX = the high end of the analog input range and
VMIN = the low end (the offset zero) of the analog range.
(Both am ground referenced).
The VREF (or Vcc) voltage is then adjusted to provide a
code change from SFFHEX to SFEHEX. This completes the
adjustment procedure.
For an example see the Zero-Shift and Span-Adjust circuit
below.
5.0 POWER SUPPLIES
Noise spikes on the Vcc supply line can cause conversion
errors as the comparator wilt respond to this noise. A low
inductance tantalum filter capacitor should be used close to
the converter Vcc pin and values of 1 pF or greater are
recommended. If an unregulated voltage is available in the
system, a separate LM340LAZ-5.0, TO-92. 5V voltage regu-
lator tor the converter (and the other analog circuitry) will
greatly reduce digital noise on the V00 supply.
A single point analog ground that is separate from the logic
ground points should be used. The power supply bypass
capacitor and the self-clocking capacitor (if used) should
both be returned to the digital ground. Any VREF bypass
capacitors, analog input filters capacitors, or input signal
shielding should be returned to the analog ground point.
[ VluM 1%;
SET! IERO
cons vomc: "'
SETS VOLTAGE SPAN
Lum-u I
TL/H/6281-16
Figure 4.Zero~Shltt and Spttrt-Adlust (2V g VIN S W)
SZOLOGV/SOOLOGV
ADC1005/ADC1025
Typical Applications
TRAHSDIJBEB
150 g,
trr INPUTS
t0.Mr RESOLUTION
ANAUIG "(PIN
VOLTAGE RAISE
Ancms VmW
Vitil-1
TL/H/52M-13
Operating with Rtttiottttttrltt Transducers Handling i 5V Analog Inputs
Vcc (5 Vac) Vcc (5 Vnc)
Vet: lt lltt
Mht M +) Mk VII“ +1
4.- F m l 1l2LM358A "
" m; -
" Wer - :tlmm 15' Ilttr
IEM tim-y mm m
AN - "''t FF t"
I 1 5k
Mt10 EE- mu
Ved-) = 0.15 Vcc
TUHI5261-14
15% of Vcc S prn S 85% of Vcc TLfH/5261-15
TRI-STATE Test Circuits and Waveforms
t1H tm, Cu-- " pF
Moe f M
a 3331.:
“I h DATA V0" m
OUTPUT!
- - - - GNU —._
TL/H/52tsr-r t,=2o ns TL/H/5261-9
ton tm, cL=1o pF
let: Yee
TL/H/5261-8 V--20 rts TL/H/5261-10
Ordering Information
Package Temperature Llnearlty Package Temperature Unearlty
Part Number Outline Range Error Part Number Outline Range Error
AtXM005BCN N20A ADC1005CCN N20A
ADtM025BCN N240 ADC1025CCN N240
ADC1005BCV V20A ty'C to + 70°C ADC1OOSCCV V20A 0' C to + 7 0. C
ADtM025BCV V28A ADC1025CCV V28A
ADC1OOSBCJ-1 J20A * y, LSB ADC1OOSCCJ-1 J20A * 1 LSB
ADC102580J-1 J24F ADC1 02560.1-1 J24F
ADC1OOSBCJ J20A _ 40.0 to + tMPC ADC1005CCJ J20A - 40''C to + 85''C
ADC1 02530.1 J24F ADC1OZSCCJ J24F
ADC1005BJ J20A - 55''C to + 125°C ADC1 0050.1 J20A - 55°C to + 125%
ADC1025BJ J24F ADC10250J J24F
SZOlOGV/SOOLOGV
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
ADC1025CCN - product/adc1025ccn?HQS=T|-nu||-nulI-dscataIog-df-pf-null-wwe
ADC1005BCV - product/adc1005bcv?HQS=T|-nulI-nulI-dscatalog-df—pf—nuII-wwe
ADC1005BJ - productladc1005bj?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
ADC1005CCN - product/adc10050cn?HQS=T|—nuII-nulI—dscataIog-df-pf-null-wwe
ADC1005CCV - product/adc1005ccv?HQS=T|-nu|l-null-dscatalog-df-pf—nuII-wwe
ADC1005CJ - product/adc1005cj?HQS=T|-nu|I-null-dscatalog-df—pf—nuII-wwe
ADC1025 - product/adc1025?HQS=T|-nu|I-nu|I-dscataIog-df—pf-nuIl-wwe
ADC1025BCJ - product/adc1025bcj?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuIl-wwe
ADC1025BCJ-1 - product/adc1025bcj-1?HQS=T|—nu|l-nu|l-dscataIog-df-pf-null-wwe
ADC1025BCN - product/adc1025bcn?HQS=TI-nuIl-nu|I-dscataIog-df-pf-null-wwe
ADC1025BCV - product/adc1025bcv?HQS=T|-nulI-nulI-dscatalog-df—pf—nuII—wwe
ADC1025BJ - product/adc1025bj?HQS=T|-nu|l-null-dscatalog-df—pf-nuII-wwe
ADC1025CCJ - product/adc10250cj?HQS=T|-nu|l-nulI-dscatalog-df—pf—null-wwe
ADC1025CCJ-1 - product/adc102500j-1?HQS=T|—nuIl-nulI-dscatalog-df-pf-nulI-wwe
ADC1005BCN - product/adc1005bcn?HQS=TI—nuIl-nu|I-dscataIog-df-pf-null-wwe
ADC1025CCV - product/adc1025ccv?HQS=T|-nu|I-nuII-dscatalog-df—pf-nuII-wwe
ADC1025CJ - product/adc1025cj?HQS=T|-nu||-nu|l-dscatalog-df—pf—nuII-wwe
ADC1005CJ - product/adc1005cj?HQS=T|-nu|I-null-dscatalog-df—pf—nuII-wwe
ADC1025CCN - product/adc1025ccn?HQS=T|—nuII-nulI—dscataIog-df—pf—nuIl-wwe
ADC1025CCV - product/adc1025ccv?HQS=T|-nu|l-nuII-dscatalog-df—pf-nuII-wwe
ADC1025 - product/adc1025?HQS=T|-nu||-nu|I-dscatalog-df-pf-null-wwe
ADC1025BCJ - product/adc1025bcj?HQS=T|-nu|I-nuII-dscatalog-df—pf—null-wwe
ADC1025BCJ-1 - product/adc1025bcj-1?HQS=T|—nuII-nu|I-dscataIog-df-pf-nuII-wwe
ADC1025BCN - product/adc1025bcn?HQS=TI—nu|I—null—dscatalog-df—pf—null-wwe
ADC1025BCV - product/adc1025bcv?HQS=T|-nulI-nulI-dscatalog-df—pf—nuII-wwe
ADC1025BJ - productladc1025bj?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
ADC1025CCJ - product/adc1025cc]?HQS=T|-nu|I-nuII-dscatalog-df—pf—nuIl-wwe
ADC1005BJ - product/adc1005bj?HQS=T|-nu|l-null-dscatalog-df-pf—nuII-wwe
ADC1025CCJ-1 - http://W\MN.ti.com/product/adc10250cj-1?HQS=T|—nuIl-nulI-dscatalog-df-pf-nulI-wwe
ADC1025CJ - product/adc10250j?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
ADC1005CCN - product/adc1005ccn?HQS=T|-nu||-nulI-dscataIog-df-pf-null-wwe
ADC1005BCV - product/adc1005bcv?HQS=T|-nulI-nulI-dscatalog-df—pf—nuII-wwe
ADC1025 - product/adc1025?HQS=T|-nu|I-nu|I-dscataIog-df—pf-nuIl-wwe
ADC1005CJ - product/adc1005cj?HQS=T|—nul|—nulI-dscatalog-df—pf—nuII—wwe
ADC1005BCN - product/adc1005bcn?HQS=TI-nuIl-nu|I-dscataIog-df-pf-null-wwe
ADC1025CCJ-1 - product/adc1025ccj-1?HQS=T|—nuIl-nulI-dscatalog-df-pf-nulI-wwe
ADC1005CCV - product/adc1005ccv?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
ADC1005BCN - product/adc1005bcn?HQS=TI-nu|I-null—dscataIog-df-pf-null-wwe
ADC1005BCV - product/adc1005bcv?HQS=T|-null-null-dscatalog-df—pf—nuII-wwe
ADC1005BJ - product/adc1005bj?HQS=T|-nu|I-null-dscatalog-df—pf—nuII-wwe
ADC1025BCJ - product/adc1025bcj?HQS=T|-nu|I-nuII-dscatalog-df—pf—null-wwe
ADC1005CCN - product/adc1005ccn?HQS=T|—nuII—nulI—dscatalog-df—pf—null-wwe
ADC1025CJ - product/adc10250j?HQS=T|-nu||-nu|l-dscatalog-df-pf—nuII-wwe
ADC1025CCV - product/adc1OZSccv?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
ADC1025CCN - product/adc1025ccn?HQS=TI—nu||-nulI-dscataIog-df-pf-null-wwe
ADC1005CCV - product/adc1005ccv?HQS=T|-nu|I-nuII-dscatalog-df—pf-nuII-wwe
ADC1025BCJ-1 - product/adc1025bcj-1?HQS=T|-nu|I-nu|I-dscataIog-df-pf-null-wwe
ADC1025BCN - product/adc1025bcn?HQS=TI—nuIl-nu|I-dscataIog-df-pf-null-wwe
ADC1025BCV - product/adc1025bcv?HQS=T|-nulI-nulI-dscatalog-df—pf—nuII—wwe
ADC1025BJ - product/adc1025bj?HQS=T|-nu|l-null-dscatalog-df—pf-nuII-wwe
ADC1025CCJ - product/adc10250cj?HQS=T|-nu|I-nulI-dscatalog-df—pf—null-wwe
