ADC0820BCM ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionApplications
Digital Signal Processing
High Speed Data Acquisition
Telecommunications
High ..
ADC0820BCM ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionFeatures
I Built-in track-and-hold function
I No missing codes
No external clocking
Sin ..
ADC0820BCM ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionELECTRICAL CHARACTERISTICS
(VDD = +5V, VREF+ = +5V, VREF‘ = GND, RD-MODE, TA = TON to TMAX, unless ..
ADC0820BCN ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionELECTRICAL CHARACTERISTICS
(VDD = +5V, VREF+ = +5V, VREF‘ = GND, RD-MODE, TA = TON to TMAX, unless ..
ADC0820BCV ,8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionMarch 2004ADC08208-Bit ..
ADC0820BCWM ,8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionMarch 2004ADC08208-Bit ..
ADT7473ARQZ-1R7 , dBCOOL Remote Thermal Monitor and Fan Control
ADT7473ARQZ-1R7 , dBCOOL Remote Thermal Monitor and Fan Control
ADT7475ARQZ-REEL , dBCool Remote Thermal Monitor and Fan Controller
ADT7475ARQZ-REEL , dBCool Remote Thermal Monitor and Fan Controller
ADT7475ARQZ-REEL7 , dBCool Remote Thermal Monitor and Fan Controller
ADT7476ARQZ , dBCOOL Remote Thermal Controller and Voltage Monitor
ADC0820BCM
4.5 V to 8 V, 8-bit high speed uP compatible A/D converter with track/hold function
National
1 Semiconductor
ADC0820 8-Bit High Speed " Compatible
I_-. I P,
7/9”/ - g8r2kaaaep, t' a252aal
microCMOS
A/ D Converter with Track/Hold Function
General Description
By using a half-flash conversion technique. the 8-bit ll
ADC0820 CMOS A/D offers a 1.5 11.5 conversion time and n
dissipates only 75 mW of power. The half-flash technique a
consists of 32 comparators, a most significant 4-bit ADC n
and a least significant 4-bit ADC. n
The input to the ADC0820 is tracked and held by the input
sampling circuitry eliminating the need for an external sam-
ple-and-hold for signals moving at less than 100 mV/ "tr.
For ease of interface to microprocessors, the ADC0820 has
been designed to appear as a memory location or I/O port a
without the need for external interfacing logic.
Key Specifications
" Resolution
" Conversion Time
8 Bits
2.5 115 Max (RD Mode)
1.5 ps Max (WR-RD Mode)
I: Input signals with slew rate of 100 mV/ps converted
without external sample-and-hold to 8 bits
I: Low Power
a Total Unadjusted Error
75mWMax
i 'ALSBand:eILSB
Features
Built-in track-and-hold function
No missing codes
No external clocking
Single supply-S VDC
Easy interface to all microprocessors, or operates
stand-alone
Latched TRl-STATE® output
Logic inputs and outputs meet both MOS and T2L volt-
age level specifications
Operates ratiometrically or with any reference value
equal to or less than Vcc
0V to 5V analog input voltage range with single 5V
supply
No zero or full-scale adjust required
Overflow output available for cascading
0.3" standard width 20-pin DIP
20-pin molded chip carrier package
20-pin small outline package
Connection and Functional Diagrams
DuaI-ln-Line and Small
Outline Packages
" 1 20 -vcc
Mo-- 2 " -NC
om- 3 18 -oTL
naz- 4 17 -oe7
tw- 5 " -oae
-wTtptar- s IS -tXrs
uooc- 7 " -oe4
E- 8 13 .-eft v...
Wd 9 12 -Vm(o)
tmir-to 11 -vesrt-)
TL/H/MOI-t
Top View
Molded Chip Carrier
Package
is '5 ' ll ill
" " " -
"Vm(*)
-resre)
TL/H/5st"-33
V1134 + i on.
" 1:31;)
ll UTNI
TI-ITIYE
IUFFERS
" LXI!)
8rttri - I "ll
mama mo comInL macumiv —}—M
W L, J! l
FIGURE 1
TLn4/6501-2
See Ordering Information
OZBOOCIV
AD00820
Absolute Maximum Ratings (Notes1&2)
If MIIItary/Aerospace specified devlces are required,
please contact the National Sttntltttmdutttttr Sales
OmttttfDlatrlbutors tor avaIlablllty and specllleatlons.
Supply Voltage (Vcc) 10V
Logic Control Inputs -0.2V to Vcc +0.2V
Voltage at Other Inputs and Output -0.2V to Vcc + 0.2V
Storage Temperature Range -65'C to + 150°C
Package Dissipation at TA = 25°C 875 mW
Input Current at Any Pin (Note 5) 1 mA
Package Input Current (Note 5) 4 mA
ESD Susceptability (Note 9) 1200V
Lead Temp. (Soldering, 10 sec.)
Dual-ln-Line Package (plastic)
Dual-ln-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 sec.)
Infrared (15 see.)
21 5''C
Operating Ratings (Notes1&2)
Temperature Range
AD0082OBD, ADCOBZOCJ
ADC0820BCD, ADCOBZOCCJ
ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820CGV
ADC0820BCWM, ADC0820CCWhh
Voc Range
TMINSTASTMAX
-55°CSTAS + 125°C
--4trCsrTAsr +85°C
0°CSTAS70°C
0°CSTAS70°C
0°CsTAs70°C
4.5V to 8V
Converter Characteristics The following specifications apply tar RD mode (pin T-- O), Vcc-- 5V,
VREF( +)= 51t, and Vmrt-) = GND unless otherwise speeified. Boldlace limits apply from Tum to TMAX; all other limits
TA = T] = 2 5'0.
ADC0820BD, ADC0820Cd ADC0820BCN, ADC0820CCN
ADC0820BCD ADC0820CCd ADC0820BtW, AD00820CCV
' ADC0820BCWM, ADC0820CCWM Limit
Parameter Cttttdltltttttt T Tested Design T Tested Deslgn Unlts
("0:56) Limit lelt (Norgs) Limit lelt
(Note n (Note 8) (Note n (Note 8)
Resolution 8 8 8 Bits
Total Unadjusted Error ADC0820BD, BCD , y, LSB
(Note 3) ADC0820BCN i 14 i y, LSB
ADC0820CD, CCD k- 1 LSB
ADC0820CCN i 1 i 1 LSB
Minimum Reference 2.3 1.00 2.3 1.2 kn
Resistance
Maximum Reference 2.3 6 2.3 5.3 6 kn
Resistance
Maximum VREF( +) vce Vcc Vet; V
Input Voltage
Minimum VrtEF(--) GND GND GND V
Input Voltage
Minimum VHEF( +) VnEF( -) VREF( -) VREri-) V
Input Voltage
Maximum VREF( -) 1trtert +) VREF( +) VREF( +) V
Input Voltage
Maximum VIN Input Vcc + 0.1 Vcc + 0.1 Vet: + 0.1 V
Voltage
Minimum VIN Input GND--0.1 GND-OA GND--0.1 V
Voltage
Maximum Analog c-s = Vcc
Input Leakage Current VIN = Vcc 3 0.3 3 VA
VIN=GND -3 -0.3 -3 WA
Power Supply Vcc=5V 15% t w, i 'A ty'te l V; i 1/. LSB
Sensitivity
DC Electrical Characteristics The following specifications apply for Vcc= 5V, unless otherwise specified.
Boldface Ilmlts apply from Tum to Tux; all other limits TA = To = 25°C.
ADC0820BD, ADCOBZOCJ ADC0820BCN, ADC0820CCN
ADC0820BCD ADC0820CC,l ADtt0820BtW, ADCOB2OCCV
' ADC0820BCWM, ADC0820CCWM 1Utttit
Parameter Condltlons T Tested Design T Tested Design Units
("0:26) le11 Limit ("0:56) Umlt Limit
. (Note n (Note 8) (Note 7) (Note 8)
ihNioLogitu''1'' vcc=5.25v ' W, At5 2.0 2.0 2.0 v
Input Voltage Mode 3.5 3.5 3.5 v
me- Logical "0" vcc=4.75v ' WA, W 0.8 0.8 thtl v
InputVoltatN Mode 1.5 1.5 1.5 v
Ieoily, Logical "I'' VIN(1) = 5V; ' W) 0.005 1 0.005 1 FA
Input Current VIN(1) = 5V; WA 0.1 3 0.1 0.3 3 HA
me = 5V; Mode 50 200 50 170 200 PA
Im(o), Logical "ty' VIN(0)=ov; ' m "f/i-lA, -0.005 --1 -0.005 -1 HA
Input Current Mode
Vouroy Logical "I" vcc= 4.751. low: -360 M; 2.4 2.8 2.4 v
Output Voltage DBO-DB7, t5PT, WT
Vcc---4.75V,lorm-- -10 " 4.5 4.6 4.5 v
DBO-DB7, m, wr
Vourtoy Logical "0" Vcc = 4.75v, 1our= 1.6 mA; 0.4 0.34 0.4 v
Output Voltage DBO-DB7, 6PT., INT, RDY
Iour, THl-STATE vom=5v; DBO-DB7, RDY 0.1 3 0.1 0.3 3 “A
Output Current VOUT = 0V; DBO-DB7, FIDY -0.I - 3 - 0.1 -0.3 - 3 HA
ISOURCEI Output VOUT = 0V; DBO-D87, m - 12 -6 - 12 -7.2 - 6 mA
Source Current Fo- - 9 - 4.0 - 9 - 5.3 - 4.0 mA
Isrm, Output Sink vom=5v; DB0-DB7, UPT, 14 7 14 8.4 7 mA
Current WT. RDY
loo, Supply Current t5g--WA--mru-ty 7.5 " 7.5 13 " mA
AC Electrical Characteristics The following spocifications apply tor vcc= tN, tr-- tt= 20 ns, VREF( +)= 5v.
Vmri-) = 0V and TA = 25°C unless otherwise specified.
T Tested Design
Parameter Conditions oe,' 6) Umlt Limit Units
(Note n (Note 8)
tom), Conversion Time for RD Mode Pin 7 = o, (Figure a 1.6 2.5 p.s
tAcco, Access T1_me (Delay from Pin 7 = o, (Figure 2) tch + 20 ttmo + 50 ns
Falling Edge of RD to Output Valid)
tCWR..RD, Conversion Time for Pin 7 = Vcc; twrt = 600 ns, 1.52 0.5
WR-RD Mode tRD = 600 ns; (Figures 3a and 3b)
twp, Write Time Min Pin 7 == Vcc: (Figures a, and 3b) 600 ns
Max (Note 4) See Graph 50 us
inn. Read Time Min Pin 7 = vas (Figures at and ap ' 600 ns
(Note 4) See Graph
tAoc1. Access Time (Delay from Pin 7 = Vcc, tRD
Falling Edge of AT5 to Output Valid) (Figure at)
CL= 15 pF 190 280 ns
CL= 100 pF 210 320 ns
tAccty Access Time (Delay from Pin 7 = Vcc, tRD> tt; (Figure 3b)
Falling Edge of mi to Output Valid) CL= 15 pF 70 120 ns
Cc-- 100 pF 90 150 ns
OZBOOOV
ADCOBZO
AC Electrical Characteristics (Continued) The following specifications apply for Vcc= 5V, t, = tt = 20 ns,
VREFH ) = tiv, VREF(-) = 0V and TA = 25'C unless otherwise specified.
T Tested Deslgn
Parameter Conditions (N026) Limit Limit Unlts
(Note n (Note 8)
t., lntemal Comparison Time Pin 7 = Voci (Figures a, and 4) 800 1300 ns
CL = 50 pF
t1”, ttH, TRI-STATE Control__ RL = 1k, Cu-- 10 pF 100 200 ns
(Delay from Rising Edge of RD to
Hi-Z State)
tttRTL, Delay from Rising Edge of Pin 7 = Vcc, CL-- 50 pF
WA to Failing Edge of W tRD> t.: (Figure 3b) tl ns
tRD < in (Figure 3a) tan + 200 tRD + 290 ns
ttapo Delay from RisiEEdge of iFigures2, 3a and 3b) 125 225 ns
RD to Rising Edge of INT Cc-- 50 pF
WHwn. Delay from Rising Edge of (Figure 4/, th.--- 50 pF 175 270 ns
W to Rising Edge of WT
tnpy. Delay from CS to RDY (Figure a, Ct. = 50 pF, Pin 7 = 0 50 100 ns
tity Delay from INT to Output Valid (Figure 4) 20 50 ns
tto Delay from RO to WT Pin 7 = Vcc, tAD (Figure 3a)
tp, Delay from End of Conversion (Figums2, 3a, a, and 4) 500 ns
to Next Conversion (Note 4) See Graph
Slew Rate, Tracking 0.1 V/ws
CVIN, Analog Input Capacitance 45 pF
Cour, Logic Output Capacitance 5 pF
Cm. Logic Input Capacitance 5 pF
Note t.. Absolute Maximum Ratings Indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
tNrNvkxsbayr)rttHtsepaMedoperunqctxtNtiorts.
Note 2: All voltages are measured with respect to the GND pin, unless otherwise tpxgtied.
Note w. Total unadjusted erro¢ includes offset, full-scale, and linearity errors.
Note 4.. Amacy may degrade lf twn or tag is shatter than the minimum vatue specified. See Accuracy vs Mn and Accuracy vs tap graphs.
Note lk When the input voltage (VIN) at any pin exceeds the power suppIy rails (Vm < V' or VIN > V+) the absolute value of current at that pin should be limited
to 1 M or less. The 4 mA package input current limits the number of pins that can exceed the power amply boundaries with a 1 mA current limit to four.
Note 6: Typical: are at 25t and represent most likely parametric norm.
Note T: Tested limits are guaranteed to National's AOOL (Avevage Outgoing Quality Levei).
Note & Design limit: are guaranteed but not 100% tested. These Iimits are not used to calculate outgoing quality levess.
Note E. Human body model, 100 pF dlscharagtrd through a 1.5 kn resistor.
TRl-STATE Test Circuits and Waveforms
m tut cm. cL-1o pF
Inn " m
ounut m
CL " Ith
I mm on m
Tr "rf
= 'tT oumm
im TLmf5501 " tr " 20 " TLIH/5501-t
tor, um cL=1o pr
Vcc Va:
Moe Mn
a output Vcc m...-....--"
tt DAYI
l ouwun m
"a. I k--20 nthlL -a TL/H/ssm-a
IT.'' T.'' -.- 'rUHfS601-5
Timing Diagrams
Note: On power-up the state of W can be high or low.
- tot -
0534331- ---.--i---.----
k....-.,.,-...,-)
--ttM--
f- WITH EXTERNAL NU.ll'
"r----
tmo-oil?- - - - - - uri
--ttti,ut
um ----
TL/Hf550t-7
FIGURE 2. RD Mode (Pin 7 l8 Low)
x.- _I
---t----- hi
-o --tg,
---tigh- - -titTtti
"tci----- - - l-o, tgri
TL/HI5501-8
FIGURE 3a. wn-no Mode (Pin 7 Is High and tnp- ------ -- Mum
ar-ic''.. x...
In C""''"-
-'"'"")
IM-lm------.-----
thttt -
TL/H/5501-9
FIGURE 3b. WR-RD Mode (Pin r Is High and tnp>m
oo-occur)-------!
FIGURE 4. WR-RD Mode (Pln 7 Is High)
MU VALID F-. -
TL/H/5501-10
Stand-Alono Operation
OZQOOCIV
ADC0820
Typical Performance Characteristics
LOGIC INPU‘I YHRESHOLD VOL‘MGE (V)
LINEAR!" ERROR (L533)
unmm mm (mm
Logic Input Threshold
Voltage " Supply Voltage
-55''tsThs +125°C
1.5 /Z/
1.4 //
C5 (15 5.0 5.25 5.5
ett-stlPhf VOLTAGE (V)
Accuracy vs twn
Vnr-SV
" beacons .
um=600 n:
TA=25°C
mmmmmm
Accuracy vs VREF
o [VREF=VREF (+ 1-VREF C-ll
TA =25°c
VIE? (V)
-1Lsa="n_EF
um emu (1.83:) tcno-cnuvsnsmu mu: m)
lI—INTEHNAL SET COMPARISON TIME (pm)
Converslon Time (RD Mode)
3 " Temperature
2 Vcc=l.75%
Vcc =5.0V
Vac =5.25V
- 100 -50 tt 50 IN 150
Ta-holy TEMPERATURE (''t)
Accuracy vs tap
" vm=sv
V59 - "
T. a NNI
" b "soo m
M 3600 "
300 100 sou 500 no 500900
lnnl'll)
tl, Internal Tlme Delay "
Temperature
V;c=4.75V
m he--" ssl-sit)','?,-,-,
0.5 LA? tt
-100 -50 tt 50 100 150
TAvAMBIENY TEMPERATURE i''tl)
LINEAR!" EMU“ (L53!) lcc—SUPPLY CURRENT (ml)
OUYPUI CURRENT (1M)
Power Supply Current vs
Temperature (not Including
reference ladder)
-1tltl -ao 0 50 IN 150
TA-MOE" TEMPERATURE i'C)
Accuracy vs q
Vat; =5V
1.5 "‘2”
l 'te',',,':',',',','
ths l.
3tXl60t1S006tn7tltt8tX1900
triot)
Output Current vs
Temperature
m; = "
lsounce mn-- 2.4V
|smu Vour =0.“ 'No
-1ilil -50 O 50 IN 150
Tx-AMBIENT TEMPERATURE (°C)
TL/H/5501-11
Description of Pin Functions
Pin Name Function
1 VIN Analog input; range =GNDSVINSVCC
DBO TRI-STATE data output-hit 0 (LSB)
DB1 TRI-STATE data output-hit 1
DB2 TRI-STATE data output-hit 2
DB3 TRI-STATE data output-bit 3
WM/RDY WR-RD Mode
W: With a low, the conversion is start-
ed on the falling edge of W. Approxi-
mately BOO ns (the preset internal time
out, ti) after the W rising edge, the result
of the conversion will be strobed into the
output latch, provided that W does not
occur prior to this time out (see Figures
3a and Sb).
RD Mode
RDY: This is an open drain output (no in-
ternal pulI-up device). RDY witl go low af-
ter the falling edge of tM; RDY will go
TRI-STATE when the result of the corwer-
sion is strobed into the output latch. It is
used to simplify the interface to a micro-
processor system (see Figure a.
Mode: Mode selection input-it is inter-
nally tied to GND through a 50 ptA current
source.
RD Mode: When mode is low
WR-RD Mode: When mode is high
WR-RD Mode
With 3 low, the TRI-STATE data outputs
(DBO-DB7) wili be activated when AB
goes low (see Figure 4). AT) can also be
used to increase the speed of the con-
verter by reading data prior to the preset
internal time out (h, "-800 ns). if this is
done, the data result transferred to output
latch is latched after the falling edge of
the W (see Figures 3a and 3b).
RD Mode
With a low, the conversion will start with
W going low, also W will enable the
TRI-STATE data outputs at the comple-
tion of the conversion. RDY going TRI-
STATE and W going low indicates the
completion of the conversion (see Figure
0301th
7 Mode
1.0 Functional Description
1.1 GENERAL OPERATION
The ADC0820 uses two 4-bit flash A/ D converters to make
an 8-bit measurement (Figure 1). Each flash ADD is made
up of 15 comparators which compare the unknown input to
a reference ladder to get a 4-bit result. To take a full 8-bit
reading, one flash conversion is done to provide the 4 most
significant data bits (via the MS flash ADC). Driven by the 4
MSBs, an internal DAG recreates an analog approximation
of the input voltage. This analog signal is then subtracted
from the input, and the difference voltage is converted by a
second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.
Pin Name Function
9 W WR-RD Mode
IN_T going low indicates that the conver-
sion is completed and the data result is in
the output latch. wr will go low, _ 800 ns
(the preset internal time out, t.) after the
rising edge ot WA (see Figure 3b); or TtTT
will go low after the falling edge of At5, if
W goes low prior to the 800 ns time out
(see Figure ar). IN-T is reset by the rising
edge of W or cs (see Figures 38 and
RD Mode
IN_T going low indicates that the conver-
sion is completed and the data result is in
the output latch. WT is reset by the rising
edge of W or C_S (see Figure a.
Ground
The bottom of resistor ladder, voltage
range: GNDscVREA-)scVmri+) (Note
The top of resistor ladder, voltage range:
y_r1EF(-)ecVnEF(+)scVcciNotit...f) -
ttS must be low in order for the RD or WR
to be recognized by the converter.
TRI-STATE data output-bit 4
TRI-STATE data output-bit 5
TRI-STATE data output-bit 6
TRI-STATE data output-bit 7 (MSB)
Overflow output-lf the analog input is
higher than the VREFH ), m will be low
at the end of conversion. It can be used to
cascade 2 or more devices to have more
resolution (9, 10-bit). This output is always
active and does not go into TRI-STATE
as DB0-DB7 do.
No connection
Power supply voltage
10 GND
11 VREF(-)
12 VREFH)
14 DB4
15 DB5
16 DB6
17 DB7
18 GET.
The internal DAC is actually a subsection of the MS flash
converter. This is accomplished by using the same resistor
ladder for the MD as well as for generating the DAC signal.
The DAC output is actually the tap on the resistor ladder
which most closely approximates the analog input. In addi-
tion, the "sampled-data" comparators used in the ADC0820
provide the ability to compare the magnitudes of several
analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADO,
where the signal to be converted is an analog difference.
OZBOOOV
ADC0820
1.0 Functional Description (Continued)
1.2 THE SAMPLED-DATA COMPARATOR
Each comparator in the ADCOBZO consists of a CMOS in-
verter with a capacitively coupled input (Figure 5). Analog
switches connect the two comparator inputs to the input
capacitor (C) and also connect the irwerter's input and out-
put. This device in effect now has one differential input pair.
A comparison requires two cycles, one for zeroing the com-
parator, and another for making the comparison.
In the first cycle, one input switch and the inverter’s teed-
back switch (Figure 5a) are closed. In this interval, C is
charged to the connected input (V1) less the inverter's bias
voltage Ms, approximately 1.2V). In the second cycle (Fi -
ure 5b), these two switches are opened and the other (V2)
input's switch is closed. The input capacitor now subtracts
its stored voltage from the second input and the difference
is amplified by the inverter's open loop gain. The inverter's
input (i/B') becomes
VB-NI c+cs
and the output will go high or low depending on the sign of
VB' -VB.
v',']',)",,",,,",]')--).:,:.:,:;)'-"
TUH/5501-12
. vo = Va
. V on C = V1 -Vg
. Ct = strayinput
node capacitor
. Va = inverter input
bias voltage
FIGURE Se. Zeroing Phase
The actual circuitry used in the ADC0820 is a simple but
important expansion of the basic comparator described
above. By adding a second capacitor and another set of
switches to the input (Figure ti), the scheme can be expand-
ed to make dual differential comparisons. In this circuit, the
feedback switch and one input switch on each capacitor (2
switches) are closed in the zeroing cycle. A comparison is
then made by connecting the second input on each capaci-
tor and opening all of the other switches (S switches). The
change in voltage at the inverter's input, as a result of the
change in charge on each input capacitor, will now depend
on both input signal differences.
1.3 ARCHITECTURE
In the ADC0820, one bank of 15 comparators is used in
each 4-bit flash AID converter IFigurst n. The MS (most
significant) flash ADC also has one additional comparator to
detect input overrange. These two sets of comparators op-
erate alternately, with one group in its zeroing cycle while
the other is comparing.
v-,,-'''';
TL/H/5501-13
"r-rl, = ("-v1)c-dii,-
ova = ci-li/wa- CV1]
OVO’ :3 dependent on V2 - V1
FIGURE 5b. Compare Phase
FIGURE 5. SampIed-Data Comparator
(m C1 l
Vin 0/
nu tom
Ml -e'', Ct
If? gl _0/
C1+C2+Cs
_ C1+C2+Cs
vo = it3IMt- VI)+G20M-V3)l
[AOC1 + at2c2l
TL/H/5501-14
FIGURE 6. ADC0820 Comparator (from MS Flash ADC)
Detailed Block Diagram
A an as A us: A an "
rusn com me svmcnzs rusn cuuv
" mm m) IV3t I/l LS! VDlTAGE
CL “ml -l -NNN
avzmow -
cms o-ofo-, cr
I it am
l l it n l
- 1 - com:
4" oumn
mm 1 c cu
:t I l /
P I it ms
om - our -
l cm: a ol,:,, 1 cu '
l 4 I t A
> ft F
' I k" ms
cm: "wt'",,, cu
.__-__
, ftf16
cm nus
ouvuts oumrs
usn Lsr:
DECODE utcnoe I a s A mg" Ctomlh
me Lam:
um Ann com
lI-IWE 0ittNT l 'gl'?
1/2 LSI must 1 3-. 0A: cum." J34
am!) ue'', " ue",
us counmcns u QI,',"'""
cm {ms cu- L15
" M} m LS! VOLTAGE e-'.i',Ci'iy
A I I _
m LAMA ue', an: uncut ue'',
TL/H/550t-15
FIGURE 7
OZSOOGV
ADCOBZO
1.0 Functional Description (Continued)
When a typical conversion is started, the W line is brought
low. At this instant the MS comparators go from zeroing to
comparison mode (Figure 8). When W is returned high af-
ter at least 600 ns, the output from the first set of compara-
tors (the first flash) is decoded and latched. At this point the
two 4-bit converters change modes and the LS (least signifi-
cant) flash ADC enters its compare cycle. No less than 600
ns later, the FTO- line may be pulled low to latch the lower 4
data bits and finish the 8-bit conversion. When At5 goes low,
the flash A/Ds change state once again in preparation for
the next conversion.
Figure 8 also outlines how the converter’s interface timing
relates to its analog input (VIN). In WR-RD mode, VIN is
measured while WA is low. In RD mode, sampling occurs
during the first 800 ns of W. Because of the input connec-
tions to the ADC0820's LS and MS comparators, the con-
verter has the ability to sample VIN at one instant (Section
2.4), despite the fact that two separate 4-bit conversions are
being done. More specifically, when WA is low the MS flash
is in compare mode (connected to VIN), and the LS flash is
in zero mode (also connected to VIN). Therefore both flash
ADCs sample V.N at the same time.
1.4 DIGITAL INTERFACE
The ADC0820 has two basic interface modes which are se-
lected by strapping the MODE pin high or low.
RD Mode
With the MODE pin grounded, the converter is set to Read
mode. in this configuration, a complete conversion is done
by pulling ATo low until output data appears. An TIT line is
provided which goes low at the end of the conversion as
well as a RDY output which can be used to signal a proces-
sor that the converter is busy or can also serve as a system
Transfer Acknowledge signal.
RD Mode (Pln 7 is Low)
ger"n.,..,..,_._/'"""uC.C"
IDV ""'""""-l..-""""""-""'""-'""'-
080-037 ------------- (CD---------
TL/HI5501-16
When in RD mods, the comparator phases are internally
triggered. At the falling edge of ATI the MS flash converter
goes from zero to compare mode and the LS ADC's com-
parators enter their zero cycle. After 800 ns, data from the
MS flash is latched and the LS flash ADC enters compare
mode. Following another 800 ns, the lower 4 bits are recov-
WR then RD Mode
With the MODE pin tied high, the A/D will be set up for the
WR-RD mode. Here, a conversion is started with the wm
input; however, there are two options for reading the output
data which relate to interface timing. If an interrupt driven
scheme is desired, the user can wait for W to go low be.
fore reading the conversion result (Figure B). IN_T will typi-
cally go low 800 ns after W’s rising edge. However, if a
shorter conversion time is desired, the processor need not
wait for W and can exercise a read after only 600 ns Wig-
ure A). If this is done, mm will immediately go low and data
will appear at the outputs.
080-087 -.------ -CCD- - - - -
TL/H/5501-17
FIGURE A. wn-RD Mode (Pin 7 Is High and tnpmm-im------------::)
TL/H/550t-18
FIGURE B. WR-RD Mode (Pin , is High and tnp>t.)
Stand-Alone
For stand-alone operation in WR-RD mode, TS- anpdit5 can
be tied low and a conversion can be started with WR. Data
will be valid approximately 800 ns following WA's rising
WR-RD Mode (Pin 7 is ngh) Stand-Alone Operation
w -""L.w"'-""'-L,,/'""-
orc-y''""":..-,)"
"W CCCD-----CCD--
TL/H/5501-19
1.0 Functional Description (Continued)
. Mt COMPAMTORS ZERO
T0 REFERENCE LINER.
. LS BDMPAHATDIS nun.
. MS BOMMMTDRS COMPARE
Vin ro THEIR MFERENCE
LADDER TAP, THE COMPARATOR
OUTPUTS DIGITAL“ TRACK
\tu-Vunm w
. LS coummns mo to
m. THE coumaroa‘s
INPUT CAPACITORS TRACK Vm.
Note: MS means most significant
LS means least ss'qrtifieartt
. 'g'ttMmtthTthtihlrP1lrs ( 'i'tdfl'l'Jl2tl'lll''
ARE UTCHED. ne "
mu: is 58 ms MS BE mo.
CONFIRM“ FUWS. . " COMPARATOR RETURN
. b8 DOMPAMTDRS COMPARE TO ZERO tttW.
Git SECTION OF MFEMNCE
LADDER.
TL/H/5501 -20
FIGURE 8. Operating Sequence (WR-RD Mode)
OTHER INTERFACE CONSIDERATIONS
In order to maintain conversion accuracy, WTT has a maxi-
mum width spec of 50 " When the MS flash ADC's sam-
pled-data comparators (Section 1.2) are in comparison
mode (W is low), the input capacitors (C, Figure 6) must
hold their charge. Switch leakage and inverter bias current
can cause errors if the comparator is left in this phase for
too long.
Since the MS flash ADC enters its zeroing phase at the end
of a conversion (Section 1.3), a new conversion cannot be
started until this phase is complete. The minimum spec for
this time (tp, Figures a Sa, 30, and 4) is 500 ns.
2.0 Analog Considerations
2.1 REFERENCE AND INPUT
The two VREF inputs of the ADC0820 are fully differential
and define the zero to lull-scale input range of the A to D
converter. This allows the designer to easily vary the span
of the analog input since this range will be equivalent to the
voltage difference between mm +) and Ved--). By reducing
Vmr0mEF---Vmri+)-VREF(-)) to less than 5V, the sen-
sitivity of the converter can be increased (i.e., it VREF= 2V
then 1 LSB=7.8 mV). The input/reference arrangement
also facilitates ratiometric operation and in many cases the
chip power supply can be used for transducer power as well
as the VREF source.
This reference flexibility lets the input span not only be var-
ied but also offset from zero. The voltage at VREF(_) sets
the input level which produces a digital output of all zeroes.
Though VIN is not itself differential, the reference design
affords nearty ditferential-input capability for most measure-
ment applications. Figure t? shows some of the configura-
tions that are possible.
2.2 INPUT CURRENT
Due to the unique conversion techniques employed by the
ADC0820, the analog input behaves somewhat differently
than in conventional devices. The AIDS sampled-data com-
parators take varying amounts of input current depending
on which cycle the conversion is in. _
The equivalent input circuit of the ADCOSZO is shown in
Figure ttht. When a conversion starts (W low. WR-RD
mode), all input switches close, connecting VIN to thirty-one
1 pF capacitors. Although the two 4-bit flash circuits are not
both in their compare cycle at the same time, " still sees
all input capacitors at once. This is because the MS tlash
converter is connected to the input during its compare inter-
val and the LS flash is connected to the input during its
zeroing phase (Section 1.3). in other words, the LS ADC
uses " as its zero-phase input
The input capacitors must charge to the input voltage
through the on resistance of the analog switches (about 5
kn to 10 kn). in addition, about 12 pF of input stray capaci-
tance must also be charged. For large source resistances.
the analog input can be modeled as an RC network as
shown in Figure tob. As Rs increases, it will take longer for
the input capacitance to charge.
In RD mode, the input switches are closed for approximately
800 ns at the start of the conversion. In WR-RD mode, the
time that the switches are closed to allow this charging is
the time that thm is low. Since other factors force this time
to be at least 600 ns, input time constants of 100 ns can be
accommodated without special consideration. Typical total
input capacitance values of 45 pF allow Rs to be 1.5 kn
without lengthening W to give VIN more time to settle.
3-1 01
OZQOOCIV
ADCOBZO
2.0 Analog Considerations (Continued)
External Reference 2.5V FuIl-Scate
"t+I------
"l-tr""'"
ViNl-lT 8ND
" REFle)
RFFf-l
TLlH/5501 -2t
Power Supply as Reference
lhttHl -l.--. tN+
" - mm " "FM
Lmas-zs
Jr" 'IEFi-) VIN(_) "tEFi-)
Input Not Referred to GND
Ihyi+)-- IN+
sr GNO
TL/H/ 5501 -22
'Current path must
still exist from lei .-)
to ground
TL/H/5501-23
FIGURE 9. Analog Input Options
R-LM DER
= " " l no”
Rs Hon
wrt-MN-d .-u11-om
m 1.83 e y l pF l "
15 LS8 CDMPAMTDRS
m msa e k' IPF
nuunsn . 1 pf
16 M38 COMPARATORS
TL/H/550t-t?4
FIGURE 10a
2.3 INPUT FILTERING
It should be made clear that transients in the analog input
signal, caused by charging current flowing into VIN, will not
degrade the AIDS performance in most cases. In efftttrt the
ADC0820 does not "look" at the input when these tran-
sients occur. The comparators’ outputs are not latched
while W is low, so at least 600 ns will be provided to
charge the ABC's input capacitance. It is therefore not nec-
essary to filter out these transients by putting an external
cap on the " terminal.
2.4 INHERENT SAMPLE-HOLD
Another benefit of the ADC0820's input mechanism is its
ability to measure a variety of high speed signals without the
help of an external sampie-and-hold. In a conventional SAR
type converter. regardless of its speed, the input must re-
main at least y, LSB stable throughout the conversion pro-
cess if full accuracy is to be maintained. Consequently, for
many high speed signals, this signal must be externally
sampled, and held stationary during the conversion.
TL/H/5501 -25
FIGURE 10b
Sampled-data comparators. by nature of their input switch-
ing, already accomplish this function to a large degree (Sec-
tion 1.2). Although the conversion time for the ADCOBZO is
1.5 ps. the time through which VIN must be 1/2 LSB stable
is much smaller. Since the MS flash ADC uses VIN as its
"compare" input and the LS ADC uses " as its "zero"
input, the ADCOBZO only "samples" ViN when W is low
(Sections 1.3 and 2.2). Even though the two flashes are not
done simultaneously, the analog signal is measured at one
instant. The value of Vm approximately 100 ns after the
rising edge of wm (100 ns due to internal logic prop delay)
will be the measured value.
Input signals with slew rates typically below 100 mV/ws can
be converted without error. However, because of the input
time constants, and charge injection through the opened
comparator input switches. faster signals may cause errors.
Still, the ADC0820's loss in accuracy for a given increase in
signal slope is far less than what would be witnessed in a
conventional successive approximation device. An SAR
type converter with a conversion time as fast as 1 ps would
still not be able to measure a 5V 1 kHz sine wave without
the aid of an external sampIe-and-hold. The ADC0820, with
no such help, can typically measure 5V, 7 kHz waveforms.
3.0 Typical Applications
8-Blt Resolullon Configuration
' B we: - -
2: M 'Lmr "Ltur
i 9 51' 2 T
' INT , .. TI."
Q l 080 MODE
y, V ' n31 VIN - Tr
a ", Mt It
" :1: M3 VRHHI "
t " Il84
Q " 085 Vnzr(-) 11 0.1 "
' Mii I
_ A " - -
V " DB? 10 - -
EFT mm -Cl
TL/H/5501-26
9-Bit Resolution Configuration
MODE I
VIEFI +3
TL/Hf5501-27
Telecom A/D Converter Multiple Input Channels
25k " mam
--NSN-- cm
158 mu - 1 13 g mm L
mu . " is _ IW m um: tr m
3 am P
'"f - ' cm 1
- li - t I I VIN ll
" m - " tom -t58 "rf E
(ill :0 m ca:
10 ' SIMPLE am li
Yr: - -
* “" - km W. W“
n a n1 nonnazu m L w:
w . cm t as A.
sun ITti 2. - F.--
= . l mm:
o l N 9
w - m q l I i7tTitr' n t Vcc Rt
ll mm 037 to sun it-S)
m -) N mm mm! l?
I MODE CHANNELS = - Vnm t I van co rm
. V|N=3 kHz max t 4Ve - 7 l-l, thrl -l [14-17]
. No track-and-hold needed man:
. Low power consumption TL/r0550t 23 l
TL/H/6501 -29
OZSOOCIV
ADCO820
3.0 Typical Applications (Continued)
8-Blt 2A2uadrant Analog Multiplier
Xm CLK Vm
m TO W) 40tlelQ I-UN to +1W)
l s t '
IO sun t 7 mun 3
u M a a noun a
a M 4 5 ma "
" s o t
- 1heFi-l cs
Ancnazn nAcnm
TI" " t6 "
1511 WEI
" 7 15 15 IL"
Lmaao-snuz m: to
Va: tW
- 20 15 u 19 ,
- MODE
1m It IT use " I ,
(av TO sec- “EH“ LE
- 8tgt= z
- ms: hl
= -15v
22 " TL/H/5501-30
Fast Intlnlte Sample-and-Hold
(avro MTU-
llitEr1--)
nucom Ct "
mawsnuz Ilix V
lltttF1+)
1% TL/H/5501-a1
Dlgltal Waveform Recorder
A "I ll ADDRESS
mm HEIDIY COUNVERS I m D CONTROL [.0616
,———a—-‘ r—fi—q F-‘——‘ r
IX X 8 MM DMNLSm
WLW IIO‘
INN! .
0' Y0 5V
ZKXGRAM
IIM'IILSJSS
DMNLMM
TRIGGER OUI'
ID...” ‘0
DH'MLSJ‘I‘
$10!!!!)
0V T!) -5V
0 1.3M samplaslaec
I 4k memory
CLOCK INPUT 0c)
(SAMPUNB FIEOUENCV : lcl!)
1 H” _
TL/H/ssm -32
3.0 Typical Applications (Continued)
OZBOOGV
ADC0820
Ordering Information
Total Temperature
Part Number Unadjusted Error Package Range
ADC0820BD D20A-Gavity DIP - 55°C to + 125°C
ADC0820BCD D20A--Cavity DIP - 40°C to + 80'C
ADC0820BCV i y, LSB 1t20A-Moldtxi Chip trc to + 70'C
Carrier
ADC0820BCM M20B--Wide Body Small tPC to + 70°C
Outline
ADC0820BCN N20A-Molded DIP 0°C to + 70'C
ADCOBZOCJ J20A-Cerdip -55'C to + 125°C
ADC0820CCd J20A-Cerdip - 40°C to + 85''C
ADC0820CCV l , LSB V20A-Molded Chip trc to + 70°C
Cartier
ADC0820CCM MJ20B-Wide Body Small 0°C to + 70°C
Outline
ADC0820CCN N20A-Moldtrd DIP 0°C to + 70°C
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
ADC0820BD - product/ad00820bd?HQS=T|-nu|I-nu|I-dscataIog-df-pf-null-wwe
ADC0820BCD - product/adc0820bcd?HQS=TI-nuIl-nu|I-dscataIog-df-pf-null-wwe
ADC0820BCM - product/adcO820bcm?HQS=TI-nulI-nu|I—dscatalog-df-pf-nulI-wwe
