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ADADC80-12
12-BIT SUCCESSIVE APPROXIMATION INTERATED CIRCUIT A/D CONVERTER
ANALOG
DEVICES
12-Bit Successive Approximation
Integrated Circuit A/D Converter
ho ADCBO
FEATURES
True 12-Bit Operation: Max Nonlinearity 10.01296
Low Gain T.C.: i30ppml°c max
FUNCTIONAL BLOCK DIAGRAM
Low Power: 800mW BIT 6 BIT 7
Fast Conversion Time: 25ps arr 5 BIT 8
Precision 6.3V Reference for External Application
Short-Cycle Capability MT 4 BIT 9
Serial or Parallel Data Outputs BIT3 BIT 10
Monolithic DAC with Scaling Resistors for Stability
Low Chip Count-High Reliability BIT 2 BIT ll
Industry Standard PInout BIT 1 MSB BIT 12 L58
"Z" Models for i12V Supplies
+5V As1jhl"j SERIAL OUT
IT a -1sv OR -12v
+5v DIGITAL REF OUT
SUPPLY 12-BIT DAC c)ifitiK (5-3V)
DIGITAL GND cmcun's CLOCK OUT
COMPARATen STATUS
BIPOLAR
OFFSET
OUT CYCLE
10V SPAN IN lilflg,
EXTERNAL
20V SPAN IN REFERENCE CLOCK IN
ANALOG GND Egg”
GAIN ADJUST AD ADC80 +15v on +12v
PRODUCT DESCRIPTION
The AD ADC80 is a complete 12-bit successive approximation
analog-to-digital converter that includes an internal clock, refer- PRODUCT HIGHLIGHTS
ence and comparator. Its hybrid IC design utilizes MSI digital
and linear monolithic chips in conjunction with a 12-bit mono-
lithic DAC to provide modular performance and versatility with
IC size, price and reliability.
Important performance characteristics of the AD ADC80 in-
clude a maximum linearity error at +25°C of i0.012%, max
gain T.C. of 30ppm/OC, typical power dissipation of 800mW
and max conversion time of MPs. Monotonic operation of the
feedback D/A converter guarantees no missing codes over the
temperature range of -25°C to +85°C.
The design of the AD ADC80 includes scaling resistors that
provide analog signal ranges of $2.5, M.0, +-10, o to +5 or 0
to +10 volts. The 6.3V precision reference may be used for ex-
ternal applications. All digital signals are fully DTL and TTL
compatible; output data may be read in both serial and par-
allel form.
The AD ADC80 is available in two performance grades, the
AD ADC80-12 (0.012% of FSR max) and the AD ADC80-10
(0.048% of FSR max). Both grades are specified for use over
the -2f'c to +85°C temperature range and both are available
in a 32-pin ceramic DIP.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights ofthird parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
The AD ADC80 is a complete 12-bit A/D converter. No
external components are required to perform a conversion.
2. A monolithic 12-bit feedback DAC is used for reduced
chip count and higher reliability.
. The internal buried zener reference is laser trimmed to 6.3
volts. The reference voltage is available externally and can
supply up to 1.5mA beyond that required for the reference
and bipolar offset current.
. The scaling resistors are included on the monolithic DAC
for exceptional thermal tracking.
. The AD ADC80 directly replaces other devices of this type
with significant increases in performance.
. The fast conversion rate of the AD ADC80 makes it an
excellent choice for applications requiring high system
throughput rates.
. The short cycle and external clock options are provided for
applications requiring faster conversion speeds or lower
resolutions.
One Technology Way, P.0. Box 9106, Norwood, MA 02062-9106, U.S.A.
Fax: 617/326-8703 wa: 710/394-6577
Cable: ANALOG NORWOODMASS
el: 617/329-4700
elex: 924491
All A0080 - SPECIFICATIONS (typical @ +25°c, ce15ll and +lill unless otherwise specified)
MODEL AD ADC80-12 AD ADCKD-IO
RESOLUTION 12 Bits 10 Bits
ANALOG INPUTS
Voltage Ranges
Bipolar :2.5v. MV, $10V
Unipolar 0V to +5V. 0V to e10V
Impedance (Direct Input)
ov to +5v, t2.5V 25m .
0V (0+10V. 25V SkQ .
110V 10kf2 .
DIGITAL INPUTS'
Convert Command Positive Pulse lOOns Wide (min)
("0" to "I'' Initiates Conversion)
Logic Loading lTTL Load
External Clock ITTL Load
TRANSFER CHARACTERISTICS ERROR
Gain Error2 10.1% of FSR3 .
Offset Error2
Unipolar 10.05% of FSR .
Bipolar 101% of FSR .
Linearity Error (max)' 10.012% of FSR 10mm of FSR
Inherent Quantization Error il/ZLSB .
Differential Linearity Error 11/2 LSB .
No Masutg Codes Temperature Range -2f'C to +85°C .
Power Supply Sensitivity
ilSV 10.0030% of FSR/% Vs .
+SV 10.001596 of FSR/% Vs .
Specification Temperature Range -2s''c to +85°C .
Gain (max) tsoppm/''C .
Offset
Unipolar tsppm of FSR/'c .
Bipolar (max) t15ppm of FSRI°C .
Linearity (max) tippm of FSR/'C .
Monotonicity GUARANTEED .
CONVERSION SPEEDS 22ps typ, 25ps max 21ps max
DIGITAL OUTPUT
(all codes complementary)
Parallel
Output Codcs6
Unipolar CSB
Bipolar COB, CTC
Output Drive 2TTL Loads
Serial Data Codes (NRZ) CSB, COB
Output Drive 2TTL Loads
Status Logic "I'' During Conversion
Status Output Drive 2TTL Loads
Internal Clock
Clock Output Drive 2TTL Loads
Frequency' 575kllz
INTERNAL REFERENCE VOLTAGE 6.3V tIOmV
Max. External Current (with no
degradation of specifications) 1.5mA
Tcmpco of Drift tloppm/'c typ, t20ppm/0C max
POWER REQUIREMENTS
Rated Voltages
Range for Razed Accuracy
t15V, +5V
4.75V to 5.25V and k14.OV to 216.0V
z Modcls8 4.75V to 5.25v and 211.4v to A16.OV
Supply Drain +15V +10mA
-1sv -20mA
+sv nemA
TEMPERATURE RANGE
Specification
Operating (Derated Specs)
-25°C to +ss°c
-55°C to +100°c
Storage -sfc to +125°C
PACKAGE OPTION,
DHB2D AD ADCSO-IZ AD ADCSO-IO
'DTL/TTL compatible im, Logic "o'' -0.8V max, Logic "i'' -- 2.0V min for digital inputs,
Logic "0" = +0.4V mu and "1 " = 2.4V min digital outputs.
’Adjusuble {0 zero with external trimpots,
' FSR mun: Full Scale Range-for example, unit connected for :10V range has 20V FSR.
'Error shown is the same " ti/2LSB mnx for resolution of AID converter,
'Conversion time with imernal clock.
'see Table l. CSB - Cnmplemenury Sung)“ Birury
COB - Compkmenury Offset Binary
CTC - Complerrtenury Two's Complement
T For conversion speeds specified.
'For 2 models order AD ADC802-12 or AD Aoc80za0.
'For packnge outline inforrnltion see Pacing: Information section.
"speeititmu'ons am: Is AD ADCMF12.'
Specifications subject to dung: withoutnoitice.
Specirwatiorts subject to change without notice.
LINEARITY ERROR
DIFFERENTIAL
LINEARITY ERROR
e BIT " BIT 12 an
1/2LSB \
1/4LSB 'N, k
3/4LSB
1/2LSB r
BBIT\ 10 an 12 arr
1/4LSB l 's,.
GAIN DRIFT ERROR — % of FSR
REFERENCE DRIFT ERROR —%
CONVERSION TIME - m
Figure I. Linearity Error vs. Conversion
Time (Normalized)
o 2 4 6 8101214161820222426
CONVERSION TIME - [15
Figure 2. Differential Linearity Error vs.
Conversion Time (Normalized)
+25 +85
TEMPERATURE - 't
Figure 3. Maximum Gain Drift Error-% of
FSR vs. Temperature
TYPICAL
-55 -25 0 +25 t85 +100
TEMPERATURE - 'tt
Figure 4. Reference Drift- % Error
vs. Temperature
REV. A
Applying the M A0880
THEORY OF OPERATION
On receipt of a CONVERT START command, the AD ADC80
converts the voltage at its analog input into an equivalent 12-
bit binary number. This conversion is accomplished as follows..
the 12-bit successive-approximation register (SAR) has its
12-bit outputs connected both to the device bit output pins
and to the corresponding bit inputs of the feedback DAC.
The analog input is successively compared to the feedback
DAC output, one bit at a time (MSB first, LSB last). The
decision to keep or reject each bit is then made at the com-
pletion of each bit comparison period, depending on the state
of the comparator at that time.
TIMING
The timing diagram is shown in Figure 5 . Receipt of a CON-
VERT START signal sets the STATUS flag, indicating conver-
sion in progress. This, in turn, removes the inhibit applied to
the gated clock, permitting it to run through 13 cycles. All
SAR parallel bit and STATUS flip-flops are initialized on the
leading edge, and the gated clock inhibit signal is removed on
the trailing edge of the CONVERT START signal. At time to,
B1 is reset and B; -Bm are set unconditionally. At tt the Bit 1
decision is made (keep) and Bit 2 is unconditionally reset. At
t2. the Bit 2 decision is made (keep) and Bit 3 is reset uncon-
ditionally. This sequence continues until the Bit 12 (LSB) de-
cision (keep) is made at t12. After a 40ns delay period, the
STATUS flag is reset, indicating that the conversion is com-
plete and that the parallel output data is valid. Resetting the
STATUS flag restores the gated clock inhibit signal, forcing the
clock output to the Logic "o'' state.
Corresponding serial and parallel data bits become valid on
the same positivegoing clock edge. Serial data does not change
and is guaranteed valid on negative-going clock edges, however;
serial data can be transferred quite simply by clocking it into a
receiving shift register on these edges (see Figure 5 ).
Incorporation of this 40ns delay guarantees that the parallel
(and serial) data are valid " the Logic "I'' to "o'' transition
of the STATUS flag, permitting parallel data transfer to be
initiated by the trailing edge of the STATUS signal.
I----- MAXIMUM THROUGHPUT TIME --I
CONVERT' '
START ---------- CONVERSION TIME (2) --------',
INTERNAL LI U Lflflf1fLnflf"lflf -
l I I I l I l I I I
STATUS To T, (T, Ir:, T4 ITs Ts lr, T8 I Ts T10 l T11
- (3) - . a u R i ft i - (4) T
MSB 3:] "0" I I l l l I 12
- t l l
BIT2 ___j "1" I I I I I
ans yiC.I n ,"1'
BIT4 "Cf"'"""""- "O'' i-'"-
ma Cy-r-"-'-, 'W' I l I C""''"
BIT6 :::i "I'' I I
BIT7 -.r m" I I I I
BIT8 CCCI- I |"1"
BIT9 III I "o" I
31110 :1 "1..
BIT11 " m"
LSB 22:] gm" I
'ir/e :2: TB 2.. 3 4 I 5 6 I 7 :78 I 9 Ito',aoLeL't.gga/gg
OUT I‘lo" "1" "1" "o" "o'' "1" "1" "I'' "0" "I'' "I'' "0%
NOTES:
l. THE CONVERT START PULSE WIDTH IS100ns MIN AND MUST REMAIN LOW DURING
A CONVERSION. THE CONVERSION IS INITIATED BY THE "RISING EDGE" OF THE
CONVERT COMMAND.
2. 25ps FOR 12 BITS AND 2hs FOR 10 BITS (MAX).
3. MSB DECISION
4. LSB DECISION 40ns PRIOR TO THE STATUS GOING LOW
''BIT DECISIONS
Figure 5. Timing Diagram (Binary Code 011001110110)
REV. A
All A0080
DIGITAL OUTPUT DATA
Both parallel and serial data from TTL storage registers are in
negative true form. Parallel data output coding is complemen-
tary binary for unipolar ranges and either complementary off-
set binary or complementary two's complement binary, de-
pending on whether BIT 1 (pin 6) or its logical inverse BIT 1
(pin 8) is used as the MSB, Parallel data becomes valid approx-
imately 40ns before the STATUS flag returns to Logic "o'',
permitting parallel data transfer to be clocked on the "I'' to
"0" transition of the STATUS flag.
Serial data coding is complementary binary for unipolar input
ranges and complementary offset binary for bipolar input
ranges. Serial output is by bit (MSB first, LSB last) in NRZ
(non-return-to-zero) format. Serial and parallel data outputs
change state on positive-going clock edges. Serial data is guaran-
teed valid 200ns after the rising clock edges, permitting serial
data to be clocked directly into a receiving register on these
edges as shown in F igure 5. There are 13 negative-going clock
edges in the complete 12-bit conversion cycle, as shown in Fig-
ure 5. The first edge shifts an invalid bit into the register,
which is shifted out on the 13th negative-going clock edge. All
serial data bits will have been correctly transferred and be in
the receiving shift register locations shown at the completion
of the conversion period.
Short Cycle Input: A Short Cycle Input, pin 21, permits the
timing cycle shown in Figure 5 to be terminated after any
number of desired bits has been converted, permitting some-
what shorter conversion times in applications not requiring full
12-bit resolution. When 10-bit resolution is desired, pin 21 is
connected to Bit 11 output pin 28. The conversion cycle then
terminates, and the STATUS flag resets after the Bit 10 de-
cision (tlo +40ns in timing diagram of F igure 5). Short
Cycle pin connections and associated maximum 12-, 10- and
8-bit conversion times are summarized in Table I. When 12-
bit resolution is required, pin 21 is connected to +SV (pin 9).
Connect Short Maximum Status Flag
Cycle Pin 21 to Resolution Conversion Reset
Pin.. Bits (% FSR) Time (ps)
9 12 0.024 25 t12 +40ns
28 10 0.100 21 tio + 40ns
30 8 0.390 17 ta + 40ns
Table L Short Cycle Connections
INPUT SCALING
The AD ADC80 input should be scaled as close to the maxi-
mum input signal range as possible in order to utilize the
maximum signal resolution of the AID converter. Connect the
input signal as shown in Table II. See Figure 6 for circuit
details.
10V RANGE 13
20V RANGE 14
COMP IN 11
FROM D/A TO SAR
CONVERTER
COMPARATOR
BIPOLAR 6.3k
OFFSET 12 o-MN-- VREF
ANALOG
COMMON Ili 'eg..
Figure 6. AD ADC80 Input Scaling Circuit
Connect
Input Connect Connect Input
Signal Output Pin 12 Pin 14 Signal
Range Code To Pin To To
i10V COB or CTC 11 Input Signal 14
15V COB or CTC 11 Open 13
12.5V COB or CTC 11 Pin 1 1 13
0V to +5V CSB 15 Pin 11 13
0V to +10V CSB 15 Open 13
Table I L AD ADC80 Input Scaling Connections
Bi BIN
l't1'2 ( ) INPUT VOLTAGE RANGE AND LSB VALUES
Analog Input
Voltage Range Defined As: iIOV MV 12.5V 0V to +10V 0V to +SV
Code COB" COB' COB"
Designation or CTC* . or CTC' . or CTC' . CSB' . * CSB' . .
One Least FSR 2f2Y _10V LV 10V fy
Significant 2n 211 2n 2n 2n 2n
Bit (LSB) n=8 78.13mV 39.06mV 19.53mV 39.06mV 19.53mV
n = 10 19.53mV 9.77mV 4.88mV 9.77mV 4.88mV
n = 12 4.88mV 2.44mV 1.22mV 2.44mV 1.22mV
Transition Values
MSB LSB
000 _ . . ooo"" +Full Scale +10V -3/2LSB +5V -3/2LSB +2.5V -3/2LSB +10V -3/2LSB +5V -3/2LSB
011 . . . 111 Mid Scale o 0 +5V +2.5V
111 . . . 110 -Full Scale -10V +1/2LSB -SV +1/2LSB -2.5V +1/2LSB 0 + 1/2LSB o +1/2LSB
NOTES:
'COB = Complementary Offset Binary
"CTC = Complementary Two's complement-obtained by using the complement
of the most significant bit (M-SB). m is available _on pin 8.
"'C53 = Complementary Straight Binary.
. . “Voltages given are the nominal value for transition to the code specified.
Table III. Input Voltages and Code Definitions
-4- REV. A
M A0880
OFFSET ADJ USTMENT
The zero adjust circuit consists of a potentiometer connected
across tArs with its slider connected through a 1.8Mf2 resistor
to Comparator Input pin 11 for all ranges. As shown in Figure
7 the tolerance of this fixed resistor is not critical, and a car-
bon composition type is generally adequate. Using a carbon
composition resistor having a -l 200ppm/°C tempco contributes
a worst-case offset tempco of 8 X 244X 10-6 x 1200ppm/° c =
2.3ppm/°c of FSR, if the OFFSET ADJ potentiometer is set
at either end of its adjustment range. Since the maximum off-
set adjustment required is typically no more than i4LSB, use
of a carbon composition offset summing resistor typically con-
tributes no more than lppm/°C of FSR offset tempco.
10KB 1.8MQ 11
TO AD ADC80
Figure 7. Offset Adjustment Circuit
An alternate offset adjust circuit, which contributes negli-
gible offset tempco if metal film resistors (tempco <100
ppm/°C) are used, is shown in Figure 8.
180k M.F. 180k M.F. 11
AD ADC80
22kt2 M.F.
Figure 8. Low Tempco Zero Adjustment Circuit
In either zero adjust circuit, the fixed resistor connected to
pin 11 should be located close to this pin to keep the pin 11
connection runs short (Comparator Input pin 11 is quite
sensitive to external noise pick-up).
GAIN ADJ USTMENT
The gain adjust circuit consists of a potentiometer connected
across iVs with its slider connected through a 10Mf2 resistor
to the gain adjust pin 16 as shown in Figure 9.
10en 10Mft 16
0.01M:6
Figure 9. Gain Adjustment Circuit
AD ADCBD
100kft
An alternate gain adjust circuit which contributes negligible
gain tempco if metal film resistors (Tempco <100ppm/0C) are
used is shown in Figure 10.
AD ADCBO
Figure 10. Low Tempco Gain Adjustment Circuit
REV. A
CALIBRATION
External ZERO AD) and GAIN AD) potentiometer:;, con-
nected as shown in F igures 11 and 12, are used for device
calibration. To prevent interaction of these two adjustments,
Zero is always adjusted first and then Gain. Zero is adjusted
with the analog input near the most negative end of the analog
range (0 for unipolar and -FS for bipolar input ranges). Gain
is adjusted with the analog input near the most positive end of
the analog range.
0 to +10V Range: Set analog input to +1LSB = +0.0024V.
Adjust Zero for digital output = 11 11 11111110. Zero is now
calibrated. Set analog input to +FSR -2LSB = +9.9952V.
Adjust Gain for o00000000001 digital output code; full-
scale (Gain) is now calibrated. Half-scale calibration check:
set analog input to +5.0000V; digital output code should be
-10V to +10V Range.. Set analog input to -9.9951V;adjust
Zero for 111111 111 110 digital output (complementary offset
binary) code. Set analog input to +9.9902V; adjust Gain for
000000000001 digital output (complementary offset binary)
code. Half-scale calibration check: set analog input to 0.0000V;
digital output (complementary offset binary) code should be
Other Ranges: Representative digital coding for o to +10V and
-10V to +10V ranges is given above. Coding relationships and
calibration points for o to +5V, -2.5V to +2.5V and -5V to
+5V ranges can be found by halving the corresponding code
equivalents listed for the o to +10V and -10V to +10V ranges,
respectively.
Zero and full-scale calibration can be accomplished to a pre-
cision of approximately i1/4LSB using the static adjustment
procedure described above. By summing a small sine or tri-
angular-wave voltage with the signal applied to the analog in-
put, the output can be cycled through each of the calibration
codes of interest to more accurately determine the center (or
end points) of each discrete quantization level. A detailed
description of this dynamic calibration technique is presented
in "A/D Conversion Notes," D. Sheingold, Analog Devices,
Inc., 1977, Part 11, Chapter 3.
G N REF DAC
15V 17 " -
t ' COM
.15v‘3_
25 R, AD ADCBO
7 9 10 16 12 14 13 11
'sv-d . ‘L
" . 1.8M 10k
-tliV = HSV
10k . ANALOG
0.01uF-_ INPUT
+15V F
Figure 11. Analog and Power Connections for
Unipolar tr- 10V Input Range
