ADADC71KD ,Complete, High Resolution 16-Bit A/D ConvertersAPPLICATIONS
The AD ADC71 and AD ADC72 m excellent for use in appli-
cations requiring 14-bit a ..
ADADC80-12 ,12-BIT SUCCESSIVE APPROXIMATION INTERATED CIRCUIT A/D CONVERTERSPECIFICATIONS (typical @ +25°c, tl5ll and " unless otherwise specified)
AD ADC80-10
MODE L A ..
ADADC80Z-12 ,12-Bit Successive Approximation Integrated Circuit A/D ConverterApplicationSARShort-Cycle Capability4 29BIT 3 BIT 10Parallel Data Output5 28BIT 11BIT 2Monolithic D ..
ADADC84-12 ,FAST, COMPLETE 12-BIT A/D CONVERTERSspecifications) LO . . . . mA
Tempco of Drift, (max) 120/max t 10 typ t5 typ 15 typ AIO ppm/"C
PO ..
ADADC85C-12 ,FAST, COMPLETE 12-BIT A/D CONVERTERSapplications requiring high system throughput rates.
4. The internal buried zener reference is l ..
ADADC85SZ-12 ,Fast, Complete 12-Bit A/D Convertersapplications, and the input buffer amplifier add flexibility and value. All digital signals are ful ..
ADSP-BF531SBSTZ400 ,400 MHz Low Cost Blackfin ProcessorGENERAL DESCRIPTIONThe ADSP-BF531/2/3 processors are members of the Blackfin ADSP-BF531/2/3 PROCESS ..
ADSP-BF531-SBSTZ400 ,400 MHz Low Cost Blackfin ProcessorSpecifications .. 19176-Lead LQFP Pinout ........ 51Recommended Operating Conditions .... 19Outline ..
ADSP-BF532SBBC400 ,400 MHz High Performance Blackfin ProcessorGENERAL DESCRIPTIONThe ADSP-BF531/2/3 processors are members of the Blackfin ADSP-BF531/2/3 PROCESS ..
ADSP-BF532SBBZ400 ,400 MHz High Performance Blackfin ProcessorSpecifications subject to change without notice. No license is granted by implication www.analog.co ..
ADSP-BF532SBBZ400 ,400 MHz High Performance Blackfin ProcessorFEATURESSDRAM, SRAM, FLASH, and ROMUp to 600 MHz high performance Blackfin processor Flexible memor ..
ADSP-BF532SBST400 ,400 MHz High Performance Blackfin ProcessorSpecifications ....... 21System Integration ... 3 Clock and Reset Timing . 22ADSP-BF531/2/3 Process ..
ADADC71JD-ADADC71KD
Complete, High Resolution 16-Bit A/D Converters
ANALOG
DEVICES
Complete, High Resolution
16-Bit A/ll Converters
ho ADlm/AD A0072
FEATURES
Commute 18-Blt Converter With Reference
and Clock
$000396 Maximum Nonhtttarfty
Na Missing Codes to " Bits
Fast Conversion - 35ps (14 Bit)
Short Cycle CapahTtty
Parallel and Social Logic Outputs
Low Power: 645mW Typical
Industry Standard Pin Out
PRODUCT DESCRIPTION
The AD ADC71 and AD ADC72 are high resolution 16-bit
hybrid IC analog-to-digital converters including reference, clock,
and laser-trimmed thin-film components. The package is a compact
M-pin hermetic ceramic DIP. The thin-film scaling resistors
allow analog input ranges of t2.5V, t 5V, t 10V, 0 to + SV, 0
to +10V, and 0 to +20V.
Important performance characteristics of the devices are maximum
linearity error of t 0.003% of FSR (AD ADC7IK, AD ADC72K
and B), and maximum conversion time of 50ws. This performance
is due to innovative design and the use of proprietary monolithic
D/A converter chips. Laser-trimmed thinmlm resistors provide
the linearity and wide temperature range for no missing codes.
The AD ADC71 and AD ADC72 provide data in parallel form
with corresponding clock and status outputs. The AD ADC71
also provides data in serial form. All digital inputs and outputs
are TTL compatible.
APPLICATIONS
The AD ADC! and AD ADC72 are excellent for use in appli-
cations requiring 14-bit accuracy over extended temperature
ranges. Typical applications include medical and analytic in-
strumentation, precision measurement for industrial robots,
automatic test equipment (ATE), multichannel data acquisition
systems, servo control systems and anywhere that excellent
stability and wide dynamic range in the smallest space is
required.
The serial output function is nonfunctional after date
code 0120.
This is u abridged version of the data sheet. To obtain a complete data
sheet, eonnet your numt ales oftice.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norfor any infringements of patents or other rights ofthird partiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices, Trademarks and
registered trademarks are the property of their respective companies.
FUNCTIONAL BLOCK DIAGRAM
- III I - “El
un ADADcn/ n mum
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PRODUCT HIGHLIGHTS
l. The AD ADC7I and AD ADC72 provide 16-bit resolution
with maximum linearity error less than I 0.003% (t0.006%
for J and A grades) at 25°C.
2. Conversion time is 35ws typical to 14 bits with short cycle
capability.
3. Two binary codes are available on the AD ADC7I and AD
ADC72 output. They are complementary straight binary
(CSB) for unipolar input voltage ranges and complementary
offset binary (COB) for bipolar input ranges. Complementary
two's complement (CTC) coding may be obtained by inverting
Pin 1 (MSB).
4. The proprietary chips used in this hybrid design provide
excellent stability over temperature and lower chip count for
improved reliability.
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703 © 2003 Analog Devices, Inc, All rights reserved.
Al] ADC71/AD Mil72- SPECIFICATION
(typical at T, = +25%; lls = ate15, +5 volts
unless otherwise noted)
Model AD ADCHIDIKD AD ADCmDIKD AD ADC73ADIBD Units
RESOLUTION l6 (mu) . . Bits
ANALOG INPUTS
Voltage Ranges
Bipohr 22.5, t. S, :10 . ' Volts
Unipolu Ottt +S,Oto +l0.0(o +20 . . Volts
lmpcdmcc (Direct Input)
0to+W, :2.SV 1.88 . . m
0to +10V. :5.0V 3.75 . . m
0to+20V, :IOV 7.50 . . en
DIGITAL INPUTS'
Carmen Command Positive Pulse Sons Wide (min) Trailing Edge Initiates Conversion
Logic Loading l (max) . . LS'ITL land
TRANSFER CHARACTERISTICS
ACCURACY
GainEmr t0.tttt0.2trux) . . %
Offset Error
Unipoln 20.05’( 20.] max) . q %ofFSR’
Bipolu -t0.Ptt0.2rsuxy - . %ofFSR
Lincuily Emor(nnx) 20.0060) 30.0060) :0.006(A) %ofFSR
20.00300 :0.003 (K) 20.00303) %ofFSR
Inherent Quantimtioet Error , V2 . . LSB
Diffetetttid Linearity Error 20.003 . . %ofFSR
NoMissiihdesCe ts'ty To l4Biu(K Grade) . To 14BitUB Gnde) Gmnnmed
POWER SUPPLY SENSmvtTY
, lSVdc 0.003 . * %of FSR/N AV;
+SV dc 0.00t . * %ofFSR/% Mls
CONVERSIONTIME’(I4BTTS) 35(50mu) . . u-s
WARM-UP TIME ' (min) . . Minutes
Gain 31501111) 210(220mu) +7(:15mu) pptnf'C
Offset
Unipolu 12(24mu) :1(:4mu) :2(:4mzx) pptnorFSRfC
Bipolar 210(mu) :8(210rmx) 25(zl0mu) ppmofFSR/‘C
Unarixy 32(3mu) , l.5(2m2x) 21.00sz) ppmofFSR/‘C
Gmnzccd No Missing Code
Temperature Range'
711D. 7210. 72ADO3Bits) Olo 70 I . 'C
71KD, NKD, 7280(14 Bits)
DIGITAL OUTPUT'
(All Codes Gtttipletnestury)
Parallel and Serial
Output Codef
Unipolu CSB . .
Bipolar COB, CTC' . .
Output Drive ' . . LSTTL Loads
Sums Logic " l " During Conversion
Sums Output Drive ' (max) ' . LSTTL Loads
Inlcmal Clock
C1ockOutputDri" S(mu) . . LSTTLLtads
Frequency 400 . . kHz
INTERNAL REFERENCE VOLTAGE 6.3 . I V dc
Error , , max * . %
Mu Exmul Current Drain
With no chndnion of Specs , 200 mu . M
TempemtureCefrtcietlt , [Own . , , max pptnPC
POWER SUPPLY REQUIREMENTS
Power Consumption 645 (850 max) * . mW
tutedVoiage,luuiN : 15 20.51311! . . Vdc
Rated Voltage, Digiul + ' t 0.25 mu . . V dc
SupplyDnin + ISVdc +l6 . . mA
Supply Drain - lSVdc -21 ' . mA
Supply Drain ' SV de + l8 . . mA
TEMPERATURE RANGE
Speenation 0 to ' 70 . - 25 to+ 85 'C
0tmrutittg(Dersed Specs) -25to+8S . -25 toe 125 'C
Slang: - SS ttt + 125 . . 'C
'Miuubklom.
'ra Sale Range.
Toe derusitionM"NoMissingCodes" ntcno Theory ot0teotitxutisll dm sheet.)
e-sa, time nub: Wed vim "Short tWe" set for kmerrewtutitxt.
'CSB -ctsatNe- Smut: Binary. con -Ctmtpletnentarr thrset Binary. CTC- (hmpkmury Tm Ctrtttptetnetu.
'cTctmrngottaimdbrusvertingMSBtt'iat).
.stmitksiattoaatessADADC70D.KD.
Spcdfntianwbimtom'ixboumodcz.
'tmic''0" - c.leux. Lop'c‘T' " 1.tBl,tninforinpatrFordigiuioutputsLaic"0'' " tth4Vmax.L8ric"t" a 2,4th.
REV. B
AD ADB'II/AD A0672
"tttSS
iii,''
g -....
-tLttt86
"' I mls no OB
Figure t. Linearity Error vs. Temperature
unnam-
.....'Rc"w
' ANV'" "sfeiggy:'iii,ii,,
§-...\§ Cs
.1... W79 N
-25 . us no 015
Figure 2. ADADC72 Gain Drift Error vs. Temperature
"m' “'M ss.,.-,';)'" “m
. " on "' no on 90° oN
Figure 3. ADADC71 Gain Drift Error vs. Temperature
THEORY OF OPERATION
The analog continuum is partitioned into 2i6 discrete ranges for
16-bit conversion. All analog values within a given quantum are
represented by the same digital code, usually assigned to the
nominal midrange value. There is an inherent quantization
uncertainty of t1/2LSB, associated with the resolution, in
addition to the actual conversion errors.
The actual conversion errors that are associated with AID con-
verters are combinations ofanalog errors due to the linear circuitry,
REV. B
matching and tracking properties of the ladder and scaling net-
works, reference error and power supply rejection. The matching
and tracking mm in the converter have been minimized by the
use of monolithic DACs that include the scaling network. The
initial gain and offset errors are specified at t0.2% FSR for
gain and t0.1% FSR for offset. These errors may be trimmed
to zero by the use of external trim circuits as shown in Figures
5 and 6. Linearity error is defined for unipolar ranges as the
deviation from a true straight line transfer characteristic from a
zero voltage analog input, which calls for a zero digital output,
to a point which is defined " a full scale. The linearity error is
based on the DAC resistor ratios. It is unadjustable and is the
most meaningful indication of ND converter accuracy. Differential
nonlinearity is a measure of the deviation in the staircase step
width between codes from the ideal least significant bit step size
(Figure 4).
Au. "SON-t
000 ..000 GAIN
, -mtsa
s h LI'
on , b
. . . m ' 2
OFFSET Fl
ERROR "m5“
”.1111 ALL enscrr
's * "
- FS ANALOG INPUT
"s -1L$B
Figure 4. Transfer Characteristics for an Idea! BipolarA/D
Monotonic behavior requires that the differential linearity error
be less than ILSB, however a monotonic converter can have
missing codes; the AD ADC71/AD ADC72 are specified as
having no missing codes over temperature ranges " specified on
the data page.
There are three types of drift error over temperature: offset,
gain and linearity. Offset drift causes a shift of the transfer
characteristic left or right on the diagram over the operating
temperature range. Gain drift causes a rotation of the transfer
characteristic about the zero for unipolar ranges or minus full
scale point for bipolar ranges. The worst case accuracy drift is
the summation of all three drift errors over temperature. Statis-
tically, however, the drift error behaves as the root-sum-squared
(RSS) and can be shown as:
RSS = s17r-eo'est
ea = Gain Drift Error (pprnPC)
co = Offset Drift Error (ppm of FSRPC)
EL = Linearity Error (ppm of FSRPC)
DESCRIPTION OF OPERATION
On receipt of a CONVERT START command, the AD ADC7l/
AD ADC72 converts the voltage at its analog input into an
equivalent ltr-bit binary number. This conversion is accomplished
as follows: the 16-bit successive-approximation register (SAR)
has its 16-bit outputs connected both to the device bit output
pins and to the corresponding bit inputs of the feedback DAC.
The analog input is successively compared to the feedback DAC
output, one bit at a time (MSB first, LSB last). The decision to
keep or reject each bit is then made at the completion of each
hil ADC71/AD A0872
bit comparison period, depending on the state of the comparator
at that time.
GAIN ADJUSTMENT
The gain adjust circuit consists of a 100ppmPC potentiometer
connected across t Vs with its slider connected through a S10kn
resistor to the gain adjust pin 29 as shown in Figure 5.
If no external trim adjustment is desired, pins 27 (offset adj)
and pin 29 (gain adj) may be left open.
Figure 5. Gain Adjustment Circuit
OFFSET ADJUSTMENT
The zero adjust circuit consists of a 100ppmf'C potentiometer
connected across t Vs with its slider connected thmugh a 1.8hin
resistor to Comparator Input pin 27 for all ranges. As shown in
Figure 6, the tolerance of this fixed resistor is not critical, and a
carbon composition type is generally adequate. Using a carbon
composition resistor having a - 1200ppmf'C tempco contributes
a worst-case offset tempeo of 32LSBu x Glppm/LSBu x
lZOOpmeC = 2.3pprnf'C of FSR, if the OFFSET ADJ poten-
tiometer is set " either end of its adjustment range. Since the
maximum offset adjustment required is typically no more than
gt: 16LSBu, use of a carbon composition offset summing resistor
typically contributes no more than lppme of FSR offset
tempco.
Fig um 6. offgtstAdjustment Circuit
An alternate offset adjust circuit, which contributes negligible
offset tempco if metal film resistors (tempco <100ppmPC) are
used, is shown in Figure 7.
In either adjust circuit, the fixed resistor connected to pin 27
should be located close to this pin to keep the pin connection
runs short (Comparator Input pin 27 is quite sensitive to external
noise pick-up).
ttmit M.F.
180kft MP.
'"1ig TO
Figure 7. Low Tempco Zero Adjustment Circuit
TIMING
The timing diagram is shown in Figure 8. Receipt of a CONVERT
START signal sets the STATUS flag, indicating conversion in
progress. This, in tum, removes the inhibit applied to the gated
clock, permitting it to run through 17 cycles. All the SAR parallel
bits, STATUS flip-flops, and the gated clock inhibit signal are
initialized on the trailing edge of the CONVERT START signal.
At time to, B, is reset and Be - Bus are set unconditionally. At
t. the Bit 1 decision is made (keep) and Bit 2 is reset uncondi-
tionally. This sequence continues until the Bit 16 (LSB) decision
(keep) is made at tis. The STATUS flag is reset, indicating that
the conversion is complete and that the parallel output data is
valid. Resetting the STATUS flag restores the gated clock inhibit
signal, forcing the clock output to the low Logic "o" state.
Note that the clock remains low until the next conversion.
Corresponding parallel data bits become valid on the same positive-
going clock edge.
MAM“ WM TIME
oouvm‘r'
START me m-------;
sums " u u I. lu u h u lu " h. Hi In 1.. h. 1.. m
m- . . . . . . .
m u_ i
Bart ri,ri-r-aea,'..i-',..1,,,.. f l I A-KA-er.,' 1 7 T I m ..',y J,'..' IC'.'.,' '..e.reT1-,'i'r"m'm
N" "t" "t" "r "
, MC wmsvm 'UlSE WIDTH IS "" MN AND "U57 RIM!“ LOW DUING
A CONVERSION The CDNVKRSDN S mnnm IV TME mum EDGE" OF THE
CONWRT COMM MANO
l w I m " INS AND “pl Fol " 817$!th
J. M it DEOSSON
. CLOCK mus LOW An“ LAST MT DEClSm
Figure 8. Timing Diagram (Binary Code 011001 1 mr 1 1 1010)
DIGITAL OUTPUT DATA
Both parallel and serial data from TTL storage registers is in
negative true form (Logic "I'' = 0V and Logic "o'' = 2.4V).
Parallel data output coding is complementary binary for unipolar
ranges and complementary offset binary for bipolar ranges.
Parallel data becomes valid at least 20ns before the STATUS
flag returns to Logic "O", permitting parallel data transfer to be
clocked on the "l" to "o'' transition of the STATUS flag (see
Figure 9).
VAUD N 5
BUSY I l
(STATUS) .l \
20ns MIN TO Sthts
Figure 9. LSB Valid to Status Low
Serial data coding is complementary binary for tmipolar input
ranges and complementary offset binary for bipolar input ranges.
Serial output is by bit (MSB first, LSB last) in NR2 (non-retum-
to-zero) format. Serial and parallel data outputs change state on
positive-going clock edges. Serial data is guaranteed valid 120ns
after the rising clock edges, permitting serial data to be clocked
directly into a receiving register on the negative-going clock
edges " shown in Figure 10. There are 17 negative-going clock
REV. B
