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AD9995KCP
12-Bit CCD Signal Processor with Precision Timing ⑩ Generator
ANALOG
DEVICES
12-Bit Mil Signal Processor with
Precision 1)hnhg"' Generator
FEATURES
6-Phase VerticaITransfer Clock Support
Correlated Double Sampler (CDS)
6 dB to 42 dB 10-BitVariable Gain Amplifier (VGA)
12-Bit 36 MHz A/D Converter
Black Level Clamp with Variable Level Control
Complete On-ChipTiming Generator
PrecisionTiming Core with <600 ps Resolution
On-Chip 3V Horizontal and RG Drivers
2-Phase and 4-Phase H-Clock Modes
Electronic and Mechanical Shutter Modes
On-Chip Driver for External Crystal
On-Chip Sync Generator with External Sync Input
56-Lead LFCSP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
GENERAL DESCRIPTION
The AD9995 is a highly integrated CCD signal processor for
digital still camera and camcorder applications. It includes a
complete analog front end with A/D conversion, combined with a
full-function programmable timing generator. The timing genera-
tor is capable of supporting both ' and 6-phase vertical clocking.
A Precision Timing core allows adjustment of high speed clocks
with less than 600 ps resolution at 36 MHz operation.
The AD9995 is specified at pixel rates of up to 36 MHz.The
analog front end includes black level clamping, CDS,VGA,
and a 12-bit A/D converter. The timing generator provides all
the necessary CCD clocks: RG, H-clocks,V-clocks, sensor gate
pulses, substrate clock, and substrate bias control. Operation is
programmed using a 3-wire serial interface.
Packaged in a space-saving 56-lead LFCSP, the AD9995 is speci-
fied over an operating temperature range of -2(Y'C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
VRT VRB
(i A09995
GdlBTO 42dB 12
ccom cos VGA / 12-BIT q BOUT
I l ADC
INTERNAL CLOCKS -e(7 DCLK
f f f f i
HORIZONTAL A PRECISION A MSHUT
DRIVERS - 653331” -
H1-H4 STROBE
V-H SYNC A
CONTROL GENERATOR ‘ INTERNAL
VSG1-VSG5 REGISTERS
VSUB SUBCK
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reliable. However, no responsibility is assumed byAnalog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective owners.
VD SYNC CLl CLO SL SCK DATA
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Tel: 781/329-4700
Fax: 781/326-8703 © 2003 Analog Devices, lnc.All rights reserved.
A09995
TABLE OF CONTENTS
SPECIFICATIONS ............................... 3 VERTICAL TIMING EXAMPLE .................... 24
Digital Specifications ............................. 3 Important Note about Signal Polarities ............... 24
AD9995 Analog Specifications ...................... 4 SHUTTER TIMING CONTROL .................... 26
Timing Specifications ............................. 5 Normal Shutter Operation ........................ 26
ABSOLUTE MAXIMUM RATINGS .................. 5 High Precision Shutter Operation ................... 26
PACKAGE THERMAL CHARACTERISTICS ........... 5 Low Speed Shutter Operation ...................... 26
ORDERING GUIDE ............................... 5 SUBCK Suppression ............................ 27
PIN CONFIGURATION ........................... 6 Readout after Exposure ........................... 27
PIN FUNCTION DESCRIPTIONS ................... 6 Using the TRIGGER Register ...................... 27
TERMINOLOGY ................................. 7 VSUB Control ................................. 28
EQUIVALENT CIRCUITS .......................... 7 MSHUT and STROBE Control .................... 28
TYPICAL PERFORMANCE CHARACTERISTICS ...... 8 TRIGGER Register Limitations .................... 29
SYSTEM OVERVIEW .............................. 9 EXPOSURE AND READOUT EXAMPLE ............ 3O
PRECISION TIMING HIGH SPEED TIMING AFE DESCRIPTION AND OPERATION ............. 31
GENERATION .................................. 10 DC Restore ................................... 31
Timing Resolution ............................... 10 Correlated Double Sampler ....................... 31
High Speed Clock Programmability ................. 10 Variable Gain Amplifier .......................... 31
H-Driver and RG Outputs ........................ 11 A/D Converter ................................. 32
Digital Data Outputs ............................ 1 1 Optical Black Clamp ............................. 32
HORIZONTAL CLAMPING AND BLANKING ........ 13 Digital Data Outputs ............................ 32
Individual CLPOB and PBLK Patterns ............... 13 POWER-UP AND SYNCHRONIZATION ............. 33
Individual HBLK Patterns ........................ 13 Recommended Power-Up Sequence for Master Mode. . . . 33
Generating Special HBLK Patterns .................. 14 Generating Software SYNC without
Generating HBLK Line Alternation ................. 14 External SYNC Signal ......................... 33
HORIZONTALTIMING SEQUENCE EXAMPLE ...... 15 SYNC during Master Mode Operation ............... 34
VERTICAL TIMING GENERATION ................ 16 Power-Up and Synchronization in Slave Mode ......... 34
Vertical Pattern Groups (V PAT) .................... 17 STANDBY MODE OPERATION .................... 34
Vertical Sequences (VSEQ) ........................ 18 CIRCUIT LAYOUT INFORMATION ................ 36
Complete Field: CombiningV-Sequences ............. 19 SERIAL INTERFACE TIMING ..................... 37
Generating Line Alternation for V-Sequence and HBLK . . 20 Register Address Banks 1 and 2 ..................... 38
Second V-Pattern Group during VSG Active Line ....... 20 Updating of New RegisterValues .................... 39
Sweep Mode Operation ........................... 21 COMPLETE LISTING OF REGISTER BANK 1 ....... 40
Multiplier Mode ................................ 21 COMPLETE LISTING OF REGISTER BANK 2 ....... 43
Vertical Sensor Gate (Shift Gate) Patterns ............. 22 OUTLINE DIMENSIONS ......................... 59
MODE Register ................................ 23
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AiMM-SPEillFliWl0lllS
Parameter Min Typ Max Unit
TEMPERATURE RANGE
Operating -20 +85 °C
Storage -65 +150 °C
POWER SUPPLY VOLTAGE
AVDD (AFE Analog Supply) 2.7 3.0 3.6 V
TCVDD (Timing Core Analog Supply) 2.7 3.0 3.6 V
RGVDD (RG Driver) 2.7 3.0 3.6 V
HVDD (HI-H4 Drivers) 2.7 3.0 3.6 V
DRVDD (Data Output Drivers) 2.7 3.0 3.6 V
DVDD (Digital) 2.7 3.0 3.6 V
POWER DISSIPATION (See TPC 1 for Power Curves)
36 MHz,Typ Supply Levels, 100 pF HI-H4 Loading 360 mW
Power from HVDD Only'' 130 mW
Standby 1 Mode 130 mW
Standby 2 Mode 12 mW
Standby 3 Mode 0.5 mW
MAXIMUM CLOCK RATE (CLI) 36 MHz
'The total power dissipated by the HVDD supply may be approximated using the equation
Total HVDD Power = [CLOAD x HVDD M Pixel Frequency] x HVDD JK Numberof H-outputs used
Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation.
Specifications subject to change without notice.
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage VIH 2. l V
Low Level Input Voltage VIL 0.6 V
High Level Input Current Im 10 yA
Low Level Input Current lu: 10 “A
Input Capacitance Cs 10 pF
LOGIC OUTPUTS (Except H and RG)
High Level Output Voltage @ 10H = 2 mA VOH 2.2 V
Low Level Output Voltage @ lor. = 2 mA VOL 0.5 V
RG and H-DRIVER OUTPUTS (HI-H4)
High Level Output Voltage @ Max Current VOH VDD - 0.5 V
Low Level Output Voltage @ Max Current Vor, 0.5 V
Maximum Output Current (Programmable) 30 mA
Maximum Load Capacitance (For Each Output) 100 pF
Specifications subject to change without notice.
REV. O
AD9995
ANALOG SPEC I Fl CA" illis (AVIJD = Ill ll, hu = 38 MHz, Typical Timing Specifications, ho to us, unless otherwise noted.)
Parameter Min Typ Max Unit Notes
Allowable CCD Reset Transient 500 mV
Max Input Range before Saturation 1.0 V p-p
Max CCD Black Pixel Amplitude $50 mV
VARIABLE GAIN AMPLIFIER (V GA)
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range
Min Gain (VGA Code 0) 6 dB
Max Gain (VGA Code 1023) 42 dB
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC output.
Min Clamp Level (Code 0) 0 LSB
Max Clamp Level (Code 255) 255 LSB
A/D CONVERTER
Resolution 12 Bits
Differential Nonlinearity (DNL) -1.0 $0.5 +1.0 LSB
No Missing Codes Guaranteed
Full-Scale Input Voltage 2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (REFT) 2.0 V
Reference Bottom Voltage (REFB) 1.0 V
SYSTEM PERFORMANCE Includes entire signal chain.
Gain Accuracy
Low Gain (VGA Code 0) 5.0 5.5 6.0 dB Gain = (0.0351 X Code) + 6 dB
Max Gain (VGA Code 1023) 40.5 41.5 42.5 dB
Peak Nonlinearity, 500 mV Input Signal 0.2 % 12 dB gain applied.
Total Output Noise 0.8 LSB rms AC grounded input, 6 dB gain applied.
Power Supply Rejection (PSR) 50 dB Measured with step change on supply.
"Input signal characteristics defined as follows:
oar;, --____
RESET TRANSIENT
opnciirgrg PIXEL INPUT gléxxnmee
Specifications subject to change without notice.
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