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AD9991KCP
10-Bit CCD Signal Processor with Precision Timing™ Generator
10-Bit CCD Signal Processor with
Precision Timing ™ Generator
FEATURES
6-Phase Vertical Transfer Clock Support
Correlated Double Sampler (CDS)
6 dB to 42 dB 10-Bit Variable Gain Ampliﬁ er (VGA)
10-Bit 27 MHz A/D Converter
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Generator
Precision Timing Core with 800 ps Resolution
On-Chip 3 V Horizontal and RG Drivers
2-Phase and 4-Phase H-Clock Modes
Electronic and Mechanical Shutter Modes
On-Chip Driver for External Crystal
On-Chip Sync Generator with External Sync Input
56-Lead LFCSP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
GENERAL DESCRIPTION
The AD9991 is a highly integrated CCD signal processor for
digital still camera and camcorder applications. It includes a
complete analog front end with A/D conversion, combined with a
full-function programmable timing generator. The timing genera-
tor is capable of supporting both 4- and 6-phase vertical clocking.
A Precision Timing core allows adjustment of high speed clocks
with 800 ps resolution at 27 MHz operation.
The AD9991 is speciﬁ ed at pixel rates of up to 27 MHz. The
analog front end includes black level clamping, CDS, VGA,
and a 10-bit A/D converter. The timing generator provides all
the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control. Operation is
programmed using a 3-wire serial interface.
Packaged in a space-saving 56-lead LFCSP, the AD9991 is speci- ed over an operating temperature range of –20°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
DCLK
MSHUT
STROBE
CLOCLI
DOUT
H1–H4
V1–V6
VSG1–VSG5
VRTVRB
VSUBSUBCKHDVDSYNCSCKDATA
CCDIN
REV. 0
AD9991
TABLE OF CONTENTS
SPECIFICATIONS ...............................................................3Digital Speciﬁ cations ..........................................................3Analog Speciﬁ cations...........................................................4Timing Speciﬁ cations...........................................................5
ABSOLUTE MAXIMUM RATINGS.....................................5
PACKAGE THERMAL CHARACTERISTICS......................5
ORDERING GUIDE.............................................................5
PIN CONFIGURATION.......................................................6
PIN FUNCTION DESCRIPTIONS.......................................6
TERMINOLOGY..................................................................7
EQUIVALENT CIRCUITS....................................................7
TYPICAL PERFORMANCE CHARACTERISTICS.............8
SYSTEM OVERVIEW............................................................9
PRECISION TIMING HIGH SPEED TIMING
GENERATION....................................................................10 Timing Resolution.............................................................10High Speed Clock Programmability....................................10H-Driver and RG Outputs.................................................11Digital Data Outputs ........................................................11
HORIZONTAL CLAMPING AND BLANKING.................13Individual CLPOB and PBLK Patterns..............................13Individual HBLK Patterns.................................................13Generating Special HBLK Patterns....................................14Generating HBLK Line Alteration .....................................14
HORIZONTAL TIMING SEQUENCE EXAMPLE.............15
VERTICAL TIMING GENERATION .................................16 Vertical Pattern Groups......................................................17Vertical Sequences..............................................................18 Complete Field: Combining V-Sequences...........................19 Generating Line Alternation for V-Sequence and HBLK......20 Second V-Pattern Group during VSG Active Line................20 Sweep Mode Operation......................................................21 Multiplier Mode................................................................21 Vertical Sensor Gate (Shift Gate) Patterns...........................22 MODE Register................................................................23
VERTICAL TIMING EXAMPLE....................................... 24Important Note about Signal Polarities...............................24
SHUTTER TIMING CONTROL........................................26Normal Shutter Operation.................................................26High Precision Shutter Operation.......................................26Low Speed Shutter Operation............................................26SUBCK Suppression.........................................................27Readout after Exposure......................................................27Using the TRIGGER Register............................................27VSUB Control...................................................................28MSHUT and STROBE Control........................................28TRIGGER Register Limitations.........................................29
EXPOSURE AND READOUT EXAMPLE..........................30
ANALOG FRONT END DESCRIPTION AND OPERATION......................................................... 31DC Restore ..................................................................... 31Correlated Double Sampler............................................... 31Variable Gain Ampliﬁ er .................................................... 31A/D Converter ..................................................................31Optical Black Clamp......................................................... 32Digital Data Outputs.........................................................32
POWER-UP AND SYNCHRONIZATION...........................33Recommended Power-Up Sequence for Master Mode.........33Generating Software SYNC without External SYNC Signal ...................................................33SYNC during Master Mode Operation...............................34Power-Up and Synchronization in Slave Mode....................34
STANDBY MODE OPERATION........................................34
CIRCUIT LAYOUT INFORMATION.................................36
SERIAL INTERFACE TIMING...........................................37Register Address Banks 1 and 2..........................................38Updating of New Register Values........................................39
COMPLETE LISTING OF REGISTER BANK 1............... 40
COMPLETE LISTING OF REGISTER BANK 2............... 43
OUTLINE DIMENSIONS.................................................. 59
AD9991–SPECIFICATIONS
Parameter Min Typ Max Unit
TEMPERATURE RANGEOperating –20 +85 °CStorage –65 +150 °C
POWER SUPPLY VOLTAGEAVDD (AFE Analog Supply) 2.7 3.0 3.6 VTCVDD (Timing Core Analog Supply) 2.7 3.0 3.6 VRGVDD (RG Driver) 2.7 3.0 3.6 VHVDD (H1–H4 Drivers) 2.7 3.0 3.6 VDRVDD (Data Output Drivers) 2.7 3.0 3.6 VDVDD (Digital) 2.7 3.0 3.6 V
POWER DISSIPATION (See TPC 1 for Power Curves) 27 MHz, Typ Supply Levels, 100 pF H1–H4 Loading 270 mW Power from HVDD Only* 100 mWStandby 1 Mode 105 mWStandby 2 Mode 10 mW Standby 3 Mode 0.5 mW
MAXIMUM CLOCK RATE (CLI) 27 MHz
*The total power dissipated by the HVDD supply may be approximated using the equationTotal HVDD Power = [CLOAD � HVDD � Pixel Frequency] � HVDD � Number of H-outputs used
Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation.
Speciﬁ cations subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage VIH 2.1 V
Low Level Input Voltage VIL 0.6 V
High Level Input Current IIH 10 µA
Low Level Input Current IIL 10 µA
Input Capacitance CIN 10 pF
LOGIC OUTPUTS (Except H and RG)
High Level Output Voltage @ IOH = 2 mA VOH 2.2 V
Low Level Output Voltage @ IOL = 2 mA VOL 0.5 V
RG and H-DRIVER OUTPUTS (H1–H4)
High Level Output Voltage @ Max Current VOH VDD – 0.5 V
Low Level Output Voltage @ Max Current VOL 0.5 V
Maximum Output Current (Programmable) 30 mA
Maximum Load Capacitance (For Each Output) 100 pF
Speciﬁ cations subject to change without notice.
(RGVDD = HVDD = DVDD = DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, un less oth er wise noted.)
AD9991
ANALOG SPECIFICATIONS

SYSTEM PERFORMANCE
*Input signal characteristics deﬁ ned as follows:
Speciﬁ cations subject to change without notice.
(AVDD = 3.0 V, fCLI = 27 MHz, Typical Timing Speciﬁ cations, TMIN to TMAX, unless otherwise noted.)
AD9991
TIMING SPECIFICATIONS (CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 27 MHz, unless otherwise noted.)

NOTES
1Parameter is programmable.
2Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Speciﬁ cations subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only. Functional operation of the device
at these or any other conditions above those listed in the operational sections of
this speciﬁ cation is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. Absolute maximum ratings apply
individually only, not in combination. Unless otherwise speciﬁ
are referenced to GND.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000
AD9991
PIN CONFIGURATION
TOP VIEW
AD9991
PIN 1
IDENTIFIER
42 SDI
41 SL
40 REFB
39 REFT
38 AVSS
37 CCDIN
36 AVDD
35 CLI
34 CLO
33 TCVDD
D3 1
D4 2
D5 3
D6 4
D7 5
D8 6
D9 7
DRVDD 8
DRVSS 9
VSUB 10
56 D255 D154 D053 NC52 NC51 DCLK50 HD49 DVDD48 DVSS47 VD
V4 15V5 16
V6 17
VSG1 18VSG2 19VSG3 2
VSG4 21VSG5 22
H1 23
H2 24
SUBCK 11
V1 12
V2 13
V3 14
HVSS 25
HVDD 26
H3 27H4 28
32 TCVSS
31 RGVDD
30 RG
29 RGVSS
46 SYNC45 STROBE44 MSHUT43 SCK
Pin Mnemonic Type2 Description
36 AVDD P Analog Supply for AFE
37 CCDIN AI CCD Signal Input
38 AVSS P Analog Ground for AFE
39 REFT AO Voltage Reference Top Bypass
40 REFB AO Voltage Reference Bottom Bypass
41 SL DI 3-Wire Serial Load Pulse
42 SDI DI 3-Wire Serial Data Input
43 SCK DI 3-Wire Serial Clock
44 MSHUT DO Mechanical Shutter Pulse
45 STROBE DO Strobe Pulse
46 SYNC DI External System Sync Input
47 VD DIO Vertical Sync Pulse
(Input for Slave Mode,
Output for Master Mode)
48 DVSS P Digital Ground
49 DVDD P Power Supply for VSG, V1–V6,
HD/VD, MSHUT, STROBE,
SYNC, and Serial Interface
50 HD DIO Horizontal Sync Pulse
(Input for Slave Mode, Output for
Master Mode)
51 DCLK DO Data Clock Output
52 NC Not Internally Connected
53 NC Not Internally Connected
54 D0 DO Data Output (LSB)
55 D1 DO Data Output
56 D2 DO Data Output
NOTESSee Figure 38 for circuit conﬁ guration.AI = Analog Input, AO = Analog Output, DI = Digital Input,
DO = Digital Output, DIO = Digital Input/Output, P = Power.
PIN FUNCTION DESCRIPTIONS1
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a ﬁ nite width. No missing codes guaranteed to
10-bit resolution indicates that all 1024 codes must be present
over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain speciﬁ cation, refers to
the peak deviation of the output of the AD9991 from a true
straight line. The point used as zero scale occurs 0.5 LSB
before the ﬁ rst code transition. Positive full scale is deﬁ ned as
a level 1.5 LSB beyond the last code transition. The deviation
is measured from the middle of each particular output code to
the true straight line. The error is then expressed as a percent-
age of the 2 V ADC full-scale signal. The input signal is always
appropriately gained up to ﬁ ll the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated in
LSB and represents the rms noise level of the total signal chain at
the speciﬁ ed gain setting. The output noise can be converted to
an equivalent voltage using the relationship 1 LSB = (ADC Full
Scale/2n codes), where n is the bit resolution of the ADC. For the
AD9991, 1 LSB is 1.95 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR speciﬁ cation is calculated from the change in the
data outputs for a given step change in the supply voltage.
EQUIVALENT CIRCUITS
Circuit 1. CCDIN
DVDD
DVSSDRVSS
DRVDD
THREE-
STATE
DATA
DOUT
Circuit 2. Digital Data Outputs
Circuit 3. Digital Inputs
Circuit 4. H1–H4, RG Drivers
AD9991–Typical Performance Characteristics
TPC 1. Power Dissipation vs. Sample Rate
TPC 2. Typical DNL Performance
VGA GAIN CODE (LSB)1000400
OUTPUT NOISE (LSB)
7.5
TPC 3. Output Noise vs. VGA Gain
SYSTEM OVERVIEW
Figure 1 shows the typical system block diagram for the AD9991
used in Master mode. The CCD output is processed by the
AD9991’s AFE circuitry, which consists of a CDS, VGA, black
level clamp, and A/D converter. The digitized pixel information
is sent to the digital image processor chip, which performs the
postprocessing and compression. To operate the CCD, all CCD
timing parameters are programmed into the AD9991 from the
system microprocessor through the 3-wire serial interface. From
the system master clock, CLI, provided by the image processor
or external crystal, the AD9991 generates all of the CCD’s hori-
zontal and vertical clocks and all internal AFE clocks. External
synchronization is provided by a SYNC pulse from the micropro-
cessor, which will reset internal counters and resync the VD and
HD outputs.
Alternatively, the AD9991 may be operated in Slave mode, in
which VD and HD are provided externally from the image pro-
cessor. In this mode, all AD9991 timing will be synchronized
with VD and HD.
Figure 1. Typical System Block Diagram, Master Mode
The H-drivers for H1–H4 and RG are included in the AD9991,
allowing these clocks to be directly connected to the CCD.
H-drive voltage of up to 3.3 V is supported. An external V-driver
is required for the vertical transfer clocks, the sensor gate pulses,
and the substrate clock.
The AD9991 also includes programmable MSHUT and
STROBE outputs, which may be used to trigger mechanical
shutter and strobe (ﬂ ash) circuitry.
Figures 2 and 3 show the maximum horizontal and vertical
counter dimensions for the AD9991. All internal horizontal and
vertical clocking is controlled by these counters to specify line
and pixel locations. Maximum HD length is 4095 pixels per line,
and maximum VD length is 4095 lines per ﬁ eld.
Figure 2. Vertical and Horizontal Counters
Figure 3. Maximum VD/HD Dimensions
AD9991
PRECISION TIMING HIGH SPEED TIMING GENERATION
The AD9991 generates high speed timing signals using the exible Precision Timing core. This core is the foundation for
generating the timing used for both the CCD and the AFE: the
reset gate RG, horizontal drivers H1–H4, and the SHP/SHD
sample clocks. A unique architecture makes it routine for the
system designer to optimize image quality by providing precise
control over the horizontal CCD readout and the AFE correlated
double sampling.
The high speed timing of the AD9991 operates the same in either
Master or Slave mode conﬁ guration. For more information on
synchronization and pipeline delays, see the Power-Up and Syn-
chronization section.
Timing Resolution
The Precision Timing core uses a 1� master clock input (CLI)
as a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 4 illustrates how the internal timing core
divides the master clock period into 48 steps or edge positions.
Using a 20 MHz CLI frequency, the edge resolution of the Preci-
sion Timing core is 1 ns. If a 1� system clock is not available, it
is also possible to use a 2� reference clock by programming the
CLIDIVIDE register (Addr 0x30). The AD9991 will then inter-
nally divide the CLI frequency by 2.
The AD9991 also includes a master clock output, CLO, which is
the inverse of CLI. This output is intended to be used as a crystal
driver. A crystal can be placed between the CLI and CLO pins to
generate the master clock for the AD9991. For more information
on using a crystal, see Figure 39.
High Speed Clock Programmability
Figure 5 shows how the high speed clocks RG, H1–H4, SHP, and
SHD are generated. The RG pulse has programmable rising and
falling edges, and may be inverted using the polarity control. The
horizontal clocks H1 and H3 have programmable rising and fall-
ing edges and polarity control. The H2 and H4 clocks are always
inverses of H1 and H3, respectively. Table I summarizes the high
speed timing registers and their parameters. Figure 6 shows the
typical 2-phase H-clock arrangement in which H3 and H4 are
programmed for the same edge location as H1 and H2.
The edge location registers are six bits wide, but there are only
48 valid edge locations available. Therefore, the register values
aremapped into four quadrants, with each quadrant containing
Figure 4. High Speed Clock Resolution from CLI Master Clock Input
12 edge locations. Table II shows the correct register values for
the corresponding edge locations.
Figure 7 shows the default timing locations for all of the high
speed clock signals.
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9991
features on-chip output drivers for the RG and H1–H4 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver and RG current can be adjusted for optimum
rise/fall time into a particular load by using the DRVCONTROL
register (Addr 0x35). The 3-bit drive setting for each output is
adjustable in 4.1 mA increments, with the minimum setting of 0
equal to OFF or three-state, and the maximum setting of 7 equal
to 30.1 mA.
As shown in Figures 5, 6, and 7, the H2 and H4 outputs are
inverses of H1 and H3, respectively. The H1/H2 crossover volt-
age is approximately 50% of the output swing. The crossover
voltage is not programmable.
Digital Data Outputs
The AD9991 data output and DCLK phases are programmable
using the DOUTPHASE register (Addr 0x37, Bits [5:0]). Any
edge from 0 to 47 may be programmed, as shown in Figure 8a.
Normally, the DOUT and DCLK signals will track in phase based
on the DOUTPHASE register contents. The DCLK output phase
can also be held ﬁ xed with respect to the data outputs by chang-
ing the DCLKMODE register HIGH (Addr 0x37, Bit 6). In this
mode, the DCLK output will remain at a ﬁ xed phase equal to
CLO (the inverse of CLI) while the data output phase is still
programmable.
There is a ﬁ xed output delay from the DCLK rising edge to the
DOUT transition, called tOD. This delay can be programmed to
four values between 0 ns and 12 ns, by using the DOUTDELAY
register (Addr 0x037, Bits [8:7]). The default value is 8 ns.
The pipeline delay through the AD9991 is shown in Figure 8b.
After the CCD input is sampled by SHD, there is an 11-cycle
delay until the data is available.
Table I. Timing Core Register Parameters for H1, H3, RG, SHP/SHD
Figure 6. 2-Phase H-Clock Operation
Table II. Precision Timing Edge Locations
I 0 to 11
AD9991
Figure 7. High Speed Timing Default Locations
Figure 8a. Digital Output Phase Adjustment
HORIZONTAL CLAMPING AND BLANKING
The AD9991’s horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. Individual control
is provided for CLPOB, PBLK, and HBLK during the different
regions of each ﬁ eld. This allows the dark pixel clamping and
blanking patterns to be changed at each stage of the readout in
order to accommodate different image transfer timing and high
speed line shifts.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 9. These two signals are independently pro-
grammed using the registers in Table III. SPOL is the start
polarity for the signal, and TOG1 and TOG2 are the ﬁ rst and
second toggle positions of the pulse. Both signals are active low
and should be programmed accordingly.
A separate pattern for CLPOB and PBLK may be programmed
for each 10 V-sequence. As described in the Vertical Timing Gen-
eration section, up to 10 separate V-sequences can be created,
each containing a unique pulse pattern for CLPOB and PBLK.
Figure 9 shows how the sequence change positions divide the
readout ﬁ eld into different regions. A different V-Sequence can be
assigned to each region, allowing the CLPOB and PBLK signals
to be changed accordingly with each change in the vertical timing.
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 10 is simi-
lar to CLPOB and PBLK. However, there is no start polarity
control. Only the toggle positions are used to designate the start
and stop positions of the blanking period. Additionally, there is a
polarity control HBLKMASK that designates the polarity of the
horizontal clock signals H1–H4 during the blanking period. Set-
ting HBLKMASK high will set H1 = H3 = Low and H2 = H4 =
High during the blanking, as shown in Figure 11. As with the
CLPOB and PBLK signals, HBLK registers are available in each
V-sequence, allowing different blanking signals to be used with
different vertical timing sequences.
(3)(2)
CLPOB
PBLK
. . .
NOTES
PROGRAMMABLE SETTINGS:
(1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
(2) FIRST TOGGLE POSITION
(3) SECOND TOGGLE POSITION
. . .
Figure 9. Clamp and Pre-Blank Pulse Placement
Table III. CLPOB and PBLK Pattern Registers
Table IV. HBLK Pattern Registers
AD9991
Figure 10. Horizontal Blanking (HBLK) Pulse Placement
Figure 11. HBLK Masking Control
Generating Special HBLK Patterns
There are six toggle positions available for HBLK. Normally,
only two of the toggle positions are used to generate the standard
HBLK interval. However, the additional toggle positions may be
used to generate special HBLK patterns, as shown in Figure 12.
The pattern in this example uses all six toggle positions to gen-
erate two extra groups of pulses during the HBLK interval. By
changing the toggle positions, different patterns can be created.
Generating HBLK Line Alternation
One further feature of the AD9991 is the ability to alternate dif-
ferent HBLK toggle positions on odd and even lines. This may be
used in conjunction with V-pattern odd/even alternation or on its
own. When a 1 is written to the HBLKALT register, TOG1 and
TOG2 are used on odd lines only, while TOG3–TOG6 are used
on even lines. Writing a 2 to the HBLKALT register gives the
opposite result: TOG1 and TOG2 are used on even lines, while
TOG3–TOG6 are used on odd lines. See the Vertical Timing
Generation, Line Alternation section for more information.
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 13 shows an example CCD layout. The horizontal register
contains 28 dummy pixels, which will occur on each line clocked
from the CCD. In the vertical direction, there are 10 optical
black (OB) lines at the front of the readout and two at the back
of the readout. The horizontal direction has four OB pixels in the
front and 48 in the back.
Figure 14 shows the basic sequence layout, to be used during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the noneffective CCD
pixels. HBLK is used during the vertical shift interval.
The HBLK, CLPOB, and PBLK parameters are programmed in
the V-sequence registers.
More elaborate clamping schemes may be used, such as adding
in a separate sequence to clamp during the entire shield OB lines.
This requires conﬁ guring a separate V-sequence for reading out
the OB lines.
Figure 13. Example CCD Conﬁ guration
Figure 14. Horizontal Sequence Example
AD9991
VERTICAL TIMING GENERATION
The AD9991 provides a very ﬂ exible solution for generating
vertical CCD timing, and can support multiple CCDs and dif-
ferent system architectures. The 6-phase vertical transfer clocks
V1–V6 are used to shift each line of pixels into the horizontal
output register of the CCD. The AD9991 allows these outputs to
be individually programmed into various readout conﬁ gurations
using a four step process.
Figure 15 shows an overview of how the vertical timing is gener-
ated in four steps. First, the individual pulse patterns for V1–V6
are created by using the vertical pattern group registers. Second,
the V-pattern groups are used to build the sequences, where
additional information is added. Third, the readout for an entire eld is constructed by dividing the ﬁ eld into different regions and
then assigning a sequence to each region. Each ﬁ eld can contain
up to seven different regions to accommodate different steps of
the readout such as high speed line shifts and unique vertical line
transfers. Up to six different ﬁ elds may be created. Finally, the
Mode register allows the different ﬁ elds to be combined into any
order for various readout conﬁ gurations.
Vertical Pattern Groups (VPAT)
The vertical pattern groups deﬁ ne the individual pulse patterns
for each V1–V6 output signal. Table V summarizes the registers
available for generating each of the 10 V-pattern groups. The start
polarity (VPOL) determines the starting polarity of the verti-
cal sequence, and can be programmed high or low for
each V1–V6 output. The ﬁ rst, second, and third toggle posi-
tion (VTOG1, VTOG2, VTOG3) are the pixel locations within
the line where the pulse transitions. A fourth toggle position
(VTOG4) is also available for V-Pattern Groups 8 and 9. All tog-
gle positions are 12-bit values, allowing their placement anywhere
in the horizontal line. A separate register, VPATSTART, speciﬁ es
the start position of the V-pattern group within the line (see the
Vertical Sequences section). The VPATLEN register designates
the total length of the V-pattern group, which will determine the
number of pixels between each of the pattern repetitions, when
repetitions are used (see the Vertical Sequences section).
The FREEZE and RESUME registers are used to temporarily
stop the operation of the V1–V6 outputs. At the pixel location
speciﬁ ed in the FREEZE register, the V1–V6 outputs will be
held static at their current dc state, high or low. The V1–V6
outputs are held until the pixel location speciﬁ ed by RESUME
register. Two sets of FREEZE/RESUME registers are pro-
vided, allowing the vertical outputs to be interrupted twice in
the same line. The FREEZE and RESUME positions are pro-
grammed in the V-pattern group registers, but are separately
enabled using the VMASK registers, which are described in the
Vertical Sequence section.
Table V. Vertical Pattern Group Registers
Figure 16. Vertical Pattern Group Programmability
AD9991
Vertical Sequences (VSEQ)
The vertical sequences are created by selecting one of the 10
V-pattern groups and adding repeats, start position, and horizon-
tal clamping, and blanking information. Up to 10 V-sequences
can be programmed, each using the registers shown in Table VI.
Figure 17 shows how the different registers are used to generate
each V-sequence.
The VPATSEL register selects which V-pattern group will be
used in a given V-sequence. The basic V-pattern group can have
repetitions added, for high speed line shifts or line binning, by
using the VPATREPO and VPATREPE registers. Generally, the
same number of repetitions are programmed into both registers,
but if a different number of repetitions is required on odd and
even lines, separate values may be used for each register (see
the V-Sequence Line Alternation section). The VPATSTART
register speciﬁ es where in the line the V-pattern group will start.
The VMASK register is used in conjunction with the FREEZE/
RESUME registers to enable optional masking of the V-outputs.
Either or both of the FREEZE1/RESUME1 and FREEZE2/
RESUME2 registers can be enabled.
The line length (in pixels) is programmable using the HDLEN
registers. Each V-sequence can have a different line length to
accommodate various image readout techniques. The maximum
number of pixels per line is 4096. Note that the last line of the eld is separately programmable using the HDLAST register
located in the Field register section.
Table VI. V-Sequence Registers (see Tables III and IV for HBLK, CLPOB, PBLK Registers)
Figure 17. V-Sequence Programmability
Complete Field: Combining V-Sequences
After the V-sequences have been created, they are combined
to create different readout ﬁ elds. A ﬁ eld consists of up to seven
different regions, and within each region a different V-sequence
can be selected. Figure 18 shows how the sequence change
positions (SCP) designate the line boundry for each region, and
the VSEQSEL registers then select which V-sequence is used
during each region. Registers to control the VSG outputs are
also included in the Field registers.
Table VII summarizes the registers used to create the different elds. Up to six different ﬁ elds can be preprogrammed using all
of the Field registers.
The VEQSEL registers, one for each region, select which of the
10 V-sequences will be active during each region. The SWEEP
registers are used to enable SWEEP mode during any region.
The MULTI registers are used to enable Multiplier mode dur-
ing any region. The SCP registers create the line boundries for
each region. The VDLEN register speciﬁ es the total number of
lines in the ﬁ eld. The total number of pixels per line (HDLEN) is
speciﬁ ed in the V-sequence registers, but the HDLAST register
speciﬁ es the number of pixels in the last line of the ﬁ eld. The
VPATSECOND register is used to add a second V-pattern group
to the V1–6 outputs during the sensor gate (VSG) line.
The SGMASK register is used to enable or disable each indi-
vidual VSG output. There is a single bit for each VSG output:
setting the bit high will mask the output, setting it low will enable
the output. The SGPAT register assigns one of the four different
SG patterns to each VSG output. The individual SG patterns are
created separately using the SG pattern registers. The SGLINE1
register speciﬁ es which line in the ﬁ eld will contain the VSG out-
puts. The optional SGLINE2 register allows the same VSG pulses
to be repeated on a different line.
Table VII. Field Registers
SGMASK
Figure 18. Complete Field is Divided into Regions
AD9991
Generating Line Alternation for V-Sequence and HBLK
During low resolution readout, some CCDs require a different
number of vertical clocks on alternate lines. The AD9991 can
support this by using the VPATREPO and VPATREPE regis-
ters. This allows a different number of VPAT repetitions to be
programmed on odd and even lines. Note that only the number
of repeats can be different in odd and even lines, but the VPAT
group remains the same.
Additionally, the HBLK signal can also be alternated for odd
and even lines. When the HBLKALT register is set high, the
HBLK TOG1 and TOG2 positions will be used on odd lines,
while the TOG3–TOG6 positions will be used on even lines.
This allows the HBLK interval to be adjusted on odd and even
lines if needed.
Figure 19 shows an example of VPAT repetition alternation and
HBLK alternation used together. It is also possible to use VPAT
and HBLK alternation separately.
Second V-Pattern Group during VSG Active Line
Most CCDs require additional vertical timing during the sensor
gate line. The AD9991 supports the option to output a second
V-pattern group for V1–V6 during the line when the sensor gates
VSG1–VSG5 are active. Figure 20 shows a typical VSG line,
which includes two separate sets of V-pattern groups for V1–V6.
The V-pattern group at the start of the VSG line is selected in the
same manner as the other regions, using the appropriate VSE-
QSEL register. The second V-pattern group, unique to the VSG
line, is selected using the VPATSECOND register, located with
the Field registers. The start position of the second VPAT group
uses the VPATLEN register from the selected VPAT registers.
Because the VPATLEN register is used as the start position and
not as the VPAT length, it is not possible to program multiple
repetitions for the second VPAT group.
Figure 19. Odd/Even Line Alternation of VPAT Repetitions and HBLK Toggle Positions
Sweep Mode Operation
The AD9991 contains an additional mode of vertical timing
operation called Sweep mode. This mode is used to generate a
large number of repetitive pulses that span multiple HD lines.
One example of where this mode is needed is at the start of the
CCD readout operation. At the end of the image exposure but
before the image is transferred by the sensor gate pulses, the
vertical interline CCD registers should be free of all charge. This
can be accomplished by quickly shifting out any charge using
a long series of pulses from the V1–V6 outputs. Depending on
the vertical resolution of the CCD, up to 2,000 or 3,000 clock
cycles will be needed to shift the charge out of each vertical CCD
line. This operation will span across multiple HD line lengths.
Normally, the AD9991 vertical timing must be contained within
one HD line length, but when Sweep mode is enabled, the HD
boundaries will be ignored until the region is ﬁ nished. To enable
Sweep mode within any region, program the appropriate
SWEEP register to High.
Figure 21 shows an example of the Sweep mode operation. The
number of vertical pulses needed will depend on the vertical
resolution of the CCD. The V1–V6 output signals are gener-
ated using the V-pattern registers (shown in Table VII). A single
pulse is created using the polarity and toggle position registers.
The number of repetitions is then programmed to match the
number of vertical shifts required by the CCD. Repetitions are
programmed in the V-sequence registers using the VPATREP
registers. This produces a pulse train of the appropriate length.
Normally, the pulse train would be truncated at the end of the
HD line length, but with Sweep mode enabled for this region,
the HD boundaries will be ignored. In Figure 21, the Sweep
region occupies 23 HD lines. After the Sweep mode region is
completed, in the next region, normal sequence operation will
resume. When using Sweep mode, be sure to set the region
boundries (using the sequence change positions) to the appropri-
ate lines to prevent the Sweep operation from overlapping the
next V-sequence.
Multiplier Mode
To generate very wide vertical timing pulses, a vertical region
may be conﬁ gured into a multiplier region. This mode uses
the V-pattern registers in a slightly different manner. Multiplier
mode can be used to support unusual CCD timing requirements,
such as vertical pulses that are wider than a single HD line length.
The start polarity and toggle positions are still used in the same
manner as the standard VPAT group programming, but the
VPATLEN is used differently. Instead of using the pixel counter
(HD counter) to specify the toggle position locations (VTOG1,
2, 3) of the VPAT group, the VPATLEN is multiplied with the
VTOG position to allow very long pulses to be generated. To cal-
culate the exact toggle position, counted in pixels after the start
position, use the equation
Multiplier Mode Toggle Position = VTOG � VPATLEN
Because the VTOG register is multiplied by VPATLEN,
the resolution of the toggle position placement is reduced. If
VPATLEN = 4, the toggle position accuracy is now reduced
to 4-pixel steps instead of single pixel steps. Table VIII sum-
marizes how the VPAT group registers are used in Multiplier
mode operation. In Multiplier mode, the VPATREPO and
VPATREPE registers should always be programmed to the same
value as the highest toggle position.
Figure 21. Example of Sweep Region for High Speed Vertical Shift
Table VIII. Multiplier Mode Register Parameters
VTOG3
VPATLEN
VPATREP
AD9991
The example shown in Figure 22 illustrates this operation. The rst toggle position is 2, and the second toggle position is 9. In
non-Multiplier mode, this would cause the V-sequence to toggle
at pixel 2 and then pixel 9 within a single HD line. However,
toggle positions are now multiplied by the VTPLEN = 4, so the rst toggle occurs at pixel count 8, and the second toggle occurs
at pixel count 36. Sweep mode has also been enabled to allow the
toggle positions to cross the HD line boundaries.
Vertical Sensor Gate (Shift Gate) Patterns
In an Interline CCD, the vertical sensor gates (VSG) are used
to transfer the pixel charges from the light-sensitive image area
into light-shielded vertical registers. From the light-shield verti-
cal registers, the image is then read out line-by-line by using the
vertical transfer pulses V1–V6 in conjunction with the high speed
horizontal clocks.
Table IX contains the summary of the VSG pattern registers. The
AD9991 has ﬁ ve VSG outputs, VSG1–VSG5. Each of the out-
puts can be assigned to one of four programmed patterns by using
the SGPATSEL registers. Each pattern is generated in a similar
manner as the V-pattern groups, with a programmable start polar-
ity (SGPOL), ﬁ rst toggle position (SGTOG1), and second toggle
position (SGTOG2). The active line where the VSG1–VSG5
pulses occur is programmable using the SGLINE1 and SGLINE2
registers. Additionally, any of the VSG1–VSG5 pulses may be
individually disabled by using the SGMASK register. The individ-
ual masking allows all of the SG patterns to be preprogrammed,
and the appropriate pulses for the different ﬁ elds can be separately
enabled. For maximum ﬂ exibility, the SGPATSEL, SGMASK,
and SGLINE registers are separately programmable for each ﬁ eld.
More detail is given in the Complete Field section.
Figure 22. Example of Multiplier Region for Wide Vertical Pulse Timing
Table IX. VSG Pattern Registers (also see Field Registers in Table VII)
MODE Register
The MODE register is a single register that selects the ﬁ eld tim-
ing of the AD9991. Typically, all of the ﬁ eld, V-sequence, and
V-pattern group information is programmed into the AD9991
at startup. During operation, the MODE register allows the user
to select any combination of ﬁ eld timing to meet the current
requirements of the system. The advantage of using the MODE
register in conjunction with preprogrammed timing is that it
greatly reduces the system programming requirements during
camera operation. Only a few register writes are required when
the camera operating mode is changed, rather than having to
write in all of the vertical timing information with each camera
mode change.
A basic still camera application might require ﬁ ve different elds of vertical timing: one for draft mode operation, one for
autofocusing, and three for still image readout. All of the reg-
ister timing information for the ﬁ ve ﬁ elds would be loaded at
startup. Then, during camera operation, the MODE register
would select which ﬁ eld timing would be active, depending on
how the camera was being used.
Table X shows how the MODE register bits are used. The three
MSBs, D23–D21, are used to specify how many total ﬁ elds will
be used. Any value from 1 to 7 can be selected using these three
bits. The remaining register bits are divided into 3-bit sections to
select which of the six ﬁ elds are used and in which order. Up to
seven ﬁ elds may be used in a single MODE write. The AD9991
will start with the Field timing speciﬁ ed by the ﬁ rst Field bits,
and on the next VD will switch to the timing speciﬁ ed by the
second Field bits, and so on.
After completing the total number of ﬁ elds speciﬁ ed in Bits
D23 to D21, the AD9991 will repeat by starting at the ﬁ rst
Field again. This will continue until a new write to the MODE
register occurs. Figure 24 shows example MODE register set-
tings for different ﬁ eld conﬁ gurations.
Table X. MODE Register Data Bit Breakdown (D23 = MSB)
Figure 24. Using the MODE Register to Select Field Timing
AD9991
VERTICAL TIMING EXAMPLE
To better understand how the AD9991 vertical timing generation
is used, consider the example CCD timing chart in Figure 25.
This particular example illustrates a CCD using a general 3-ﬁ eld
readout technique. As described in the previous Field section,
each readout ﬁ eld should be divided into separate regions to
perform each step of the readout. The sequence change posi-
tions (SCP) determine the line boundaries for each region, and
the VSEQSEL registers will then assign a particular V-sequence
to each region. The V-sequences will contain the speciﬁ c timing
information required in each region: V1–V6 pulses (using VPAT
groups), HBLK/CLPOB timing, and VSG patterns for the SG
active lines.
This particular timing example requires four regions for each
of the three ﬁ elds, labeled Region 0, Region 1, Region 2, and
Region 3. Because the AD9991 allows up to six individual ﬁ elds
to be programmed, the Field 0, Field 1, and Field 2 registers can
be used to meet the requirements of this timing example. The
four regions for each ﬁ eld are very similar in this example, but
the individual registers for each ﬁ eld allow ﬂ exibility to accom-
modate other timing charts.
Region 0 is a high speed vertical shift region. Sweep mode can be
used to generate this timing operation, with the desired number
of high speed vertical pulses needed to clear any charge from the
CCD’s vertical registers.
Region 1 consists of only two lines, and uses standard single line
vertical shift timing. The timing of this region area will be the
same as the timing in Region 3.
Region 2 is the sensor gate line, where the VSG pulses transfer the
image into the vertical CCD registers. This region may require the
use of the second V-pattern group for SG active line.
Region 3 also uses the standard single line vertical shift timing,
the same timing as Region 1.
In summary, four regions are required in each of the three ﬁ elds.
The timing for Regions 1 and 3 is essentially the same, reducing
the complexity of the register programming.
Other registers will need to be used during the actual readout
operation, such as the MODE register, shutter control registers
(TRIGGER, SUBCK, VSUB, MSHUT, STROBE), and the AFE
gain register. These registers will be explained in other examples.
Important Note About Signal Polarities
When programming the AD9991 to generate the V1–V6,
VSG1–VSG5, and SUBCK signals, it is important to note that
the V-driver circuit usually inverts these signals. Carefully check
the required timing signals needed at the input and output of
the V-driver circuit being used, and adjust the polarities of the
AD9991 outputs accordingly.
Figure 25. CCD
iming Example: Di
viding Eac
h Field into R
egions
AD9991
SHUTTER TIMING CONTROL
The CCD image exposure time is controlled by the substrate
clock signal (SUBCK), which pulses the CCD substrate to clear
out accumulated charge. The AD9991 supports three types of
electronic shuttering: normal shutter, high precision shutter,
and low speed shutter. Along with the SUBCK pulse placement,
the AD9991 can accommodate different readout conﬁ gurations
to further suppress the SUBCK pulses during multiple ﬁ eld
readouts. The AD9991 also provides programmable outputs to
control an external mechanical shutter (MSHUT), strobe/ﬂ ash
(STROBE), and the CCD bias select signal (VSUB).
Normal Shutter Operation
By default, the AD9991 is always operating in the normal shutter
conﬁ guration in which the SUBCK signal is pulsing in every VD eld (see Figure 26). The SUBCK pulse occurs once per line,
and the total number of repetitions within the ﬁ eld will determine
the length of the exposure time. The SUBCK pulse polarity
and toggle positions within a line are programmable using the
SUBCKPOL and SUBCK1TOG registers (see Table XI).
The number of SUBCK pulses per ﬁ eld is programmed in the
SUBCKNUM register (addr. 0x63).
As shown in Figure 26, the SUBCK pulses will always begin
in the line following the SG active line, which is speciﬁ ed in
the SGACTLINE registers for each ﬁ eld. The SUBCKPOL,
SUBCK1TOG, SUBCK2TOG, SUBCKNUM, and SUBCK-
SUPPRESS registers are updated at the start of the line after the
sensor gate line, as described in the Serial Update section.
High Precision Shutter Operation
High precision shuttering is used in the same manner as nor-
mal shuttering, but uses an additional register to control the
very last SUBCK pulse. In this mode, the SUBCK still pulses
once per line, but the last SUBCK in the ﬁ eld will have an
additional SUBCK pulse whose location is determined by the
SUBCK2TOG register, as shown in Figure 27. Finer resolution
of the exposure time is possible using this mode. Leaving the
SUBCK2TOG register set to max value (0xFFFFFF) will disable
the last SUBCK pulse (default setting).
Low Speed Shutter Operation
Normal and high precision shutter operations are used when
the exposure time is less than one ﬁ eld long. For long exposure
times greater than one ﬁ eld interval, low speed shutter opera-
tion is used. The AD9991 uses a separate exposure counter to
achieve long exposure times. The number of ﬁ elds for the low
speed shutter operation is speciﬁ ed in the EXPOSURE register
(addr. 0x62). As shown in Figure 28, this shutter mode will
suppress the SUBCK and VSG outputs for up to 4095 ﬁ elds
(VD periods). The VD and HD outputs may be suppressed
during the exposure period by programming the VDHDOFF
register to 1.
To generate a low speed shutter operation, it is necessary to trig-
ger the start of the long exposure by writing to the TRIGGER
register bit D3. When this bit is set High, the AD9991 will begin
an exposure operation at the next VD edge. If a value greater than
zero is speciﬁ ed in the EXPOSURE register, the AD9991 will
suppress the SUBCK output on subsequent ﬁ elds.
Figure 26. Normal Shutter Mode
If the exposure is generated using the TRIGGER register and the
EXPOSURE register is set to zero, the behavior of the SUBCK
will not be any different than the normal shutter or high precision
shutter operations, in which the TRIGGER register is not used.
SUBCK Suppression
Normally, the SUBCKs will begin to pulse on the line following
the sensor gate line (VSG). With some CCDs, the SUBCK pulse
needs to be suppressed for one or more lines following the VSG
line. The SUBCKSUPPRESS register allows for suppression of
the SUBCK pulses for additional lines following the VSG line.
Readout after Exposure
After the exposure, the readout of the CCD data occurs, beginning
with the sensor gate (VSG) operation. By default, the AD9991 is
generating the VSG pulses in every ﬁ eld. In the case where only a
single exposure and single readout frame are needed, such as the
CCD’s preview mode, the VSG and SUBCK pulses can be oper-
ating in every ﬁ eld.
However in many cases, during readout the SUBCK output
needs to be further suppressed until the readout is completed.
The READOUT register speciﬁ es the number of additional elds after the exposure to continue the suppression of SUBCK.
READOUT can be programmed for zero to seven additional elds, and should be preprogrammed at startup, not at the same
time as the exposure write. A typical interlaced CCD frame read-
out mode will generally require two additional ﬁ elds of SUBCK
suppression (READOUT = 2). A 3-ﬁ eld, 6-phase CCD will
require three additional ﬁ elds of SUBCK suppression after the
readout begins (READOUT = 3).
If the SUBCK output is required to start back up during the last eld of readout, simply program the READOUT register to one
less than the total number of CCD readout ﬁ elds.
Like the exposure operation, the readout operation must be trig-
gered by using the TRIGGER register.
Using the TRIGGER Register
As described previously, by default the AD9991 will output the
SUBCK and VSG signals on every ﬁ eld. This works well for con-
tinuous single ﬁ eld exposure and readout operations, such as the
CCD’s live preview mode. However, if the CCD requires a longer
exposure time, or if multiple readout ﬁ elds are needed, then the
TRIGGER register is needed to initiate speciﬁ c exposure and
readout sequences.
Typically, the exposure and readout bits in the TRIGGER
register are used together. This will initiate a complete exposure-
plus-readout operation. Once the exposure has been completed,
the readout will automatically occur. The values in the EXPO-
SURE and READOUT registers will determine the length of
each operation.
Figure 28. Low Speed Shutter Mode Using EXPOSURE Register
Table XI. Shutter Mode Register Parameters
Register Length Range Description
TRIGGER 5b On/Off for Five Signals Trigger for VSUB [0], MSHUT [1], STROBE [2], Exposure [3],
and Readout Start [4]
READOUT 3b 0–7 # of Fields Number of Fields to Suppress SUBCK after Exposure
EXPOSURE 12b 0–4095 # of Fields Number of Fields to Suppress to SUBCK and VSG during
Exposure Time (Low Speed Shutter)
VDHDOFF 1b On/Off Disable VD/HD Output during Exposure (1 = On, 0 = Off)
SUBCKPOL* 1b High/Low SUBCK Start Polarity for SUBCK1 and SUBCK2
SUBCK1TOG* 24b 0–4095 Pixel Locations Toggle Positions for First SUBCK Pulse (Normal Shutter)
SUBCK2TOG* 24b 0–4095 Pixel Locations Toggle Positions for Second SUBCK Pulse in Last Line
(High Precision)
SUBCKNUM* 12b 1–4095 # of Pulses Total Number of SUBCKs per Field, at One Pulse per Line
AD9991
It is possible to independently trigger the readout operation
without triggering the exposure operation. This will cause the
readout to occur at the next VD, and the SUBCK output will be
suppressed according to the value of the READOUT register.
The TRIGGER register is also used to control the STROBE,
MSHUT, and VSUB signal transitions. Each of these signals are
individually controlled, although they will be dependent on the
triggering of the exposure and readout operation.
See Figure 32 for a complete example of triggering the exposure
and readout operations.
VSUB Control
The CCD readout bias (VSUB) can be programmed to accom-
modate different CCDs. Figure 29 shows two different modes
that are available. In Mode 0, VSUB goes active during the ﬁ eld
of the last SUBCK when the exposure begins. The On position
(rising edge in Figure 29) is programmable to any line within
the ﬁ eld. VSUB will remain active until the end of the image
readout. In Mode 1, the VSUB is not activated until the start of
the readout.
An additional function called VSUB KEEP-ON is also available.
When this bit is set high, the VSUB output will remain on (active)
even after the readout has ﬁ nished. To disable the VSUB at a later
time, set this bit back to low.
MSHUT and STROBE Control
MSHUT and STROBE operation is shown in Figures 30, 31,
and 32. Table XII shows the register parameters for controlling
the MSHUT and STROBE outputs. The MSHUT output is
switched on with the MSHUTON registers, and will remain on
until the location speciﬁ ed in the MSHUTOFF registers. The
location of MSHUTOFF is fully programmable to anywhere
within the exposure period, using the FD (ﬁ eld), LN (line), and
PX (pixel) registers. The STROBE pulse is deﬁ ned by the on and
Figure 29. VSUB Programmability
Figure 30. MSHUT Output Programmability
off positions. STROBON_FD is the ﬁ eld in which the STROBE
is turned on, measured from the ﬁ eld containing the last SUBCK
before exposure begins. The STROBON_ LN PX register gives
the line and pixel positions with respect to STROBON_FD. The
STROBE off position is programmable to any ﬁ eld, line, and
pixel location with respect to the ﬁ eld of the last SUBCK.
TRIGGER Register Limitations
While the TRIGGER register can be used to perform a complete
exposure and readout operation, there are limitations on its use.
Once an exposure-plus-readout operation has been triggered,
another exposure/readout operation cannot be triggered right
away. There must be at least one idle ﬁ eld (VD intervals) before
the next exposure/readout can be triggered.
The same limitation applies to the triggering of the MSHUT
signal. There must be at least one idle ﬁ eld after the completion
of the MSHUT OFF operation before another MSHUT OFF
operation may be programmed.
The VSUB trigger requires two idle ﬁ elds between exposure/
readout operations in order to ensure proper VSUB on/off trig-
gering. If the VSUB signal is not required to be turned on and
off in between each successive exposure/readout operation, this
limitation can be ignored. The VSUB Keep-On mode is useful
when successive exposure/readout operations are required.
Figure 31. STROBE Output Programmability
Table XII. VSUB, MSHUT, and STROBE Register Parameters
Register Length Range Description
VSUBMODE[0] 1b High/Low VSUB Mode (0 = Mode 0, 1 = Mode 1) (See Figure 29).
VSUBMODE[1] 1b High/Low VSUB Keep-On Mode. VSUB will stay active after readout when set high.
VSUBON[11:0] 12b 0–4095 Line Location VSUB On Position. Active starting in any line of ﬁ eld.
VSUBON[12] 1b High/Low VSUB Active Polarity.
MSHUTPOL[0] 1b High/Low MSHUT Active Polarity.
MSHUTPOL[1] 1b On/Off MSHUT Manual Enable (1 = Active or Open).
MSHUTON 24b 0–4095 Line/Pix Location MSHUT On Position Line [11:0] and Pixel [23:12] Location.
MSHUTOFF_FD 12b 0–4095 Field Location Field Location to Switch Off MSHUT (Inactive or Closed).
MSHUTOFF_LNPX 24b 0–4095 Line/Pix Location Line/Pixel Position to Switch Off MSHUT (Inactive or Closed).
STROBPOL 1b High/Low STROBE Active Polarity.
STROBON_FD 12b 0–4095 Field Location STROBE ON Field Location, with Respect to Last SUBCK Field.
STROBON_LNPX 24b 0–4095 Line/Pix Location STROBE ON Line/Pixel Position.
STROBOFF_FD 12b 0–4095 Field Location STROBE OFF Field Location, with Respect to Last SUBCK Field.
STROBOFF_LNPX 24b 0–4095 Line/Pix Location STROBE OFF Line/Pixel Position.
AD9991
Figure 32. Example of Exposure and Still Image R
eadout Using Shut
ter Signals and Mode R
egister
ister (addr 0x61) to specify the number of ﬁ
elds
ta is read out.
In this example,
elds
during exposure. In
this example,
TRIGGER reg
ister (addr 0x60) to enable the STR
OBE,
MSHUT
and to star
t the exposure/readout opera
tion.
o tr
igger all
ents (as in Figure 32),
set the reg
ister
TRIGGER = 31.
Readout will
iod is ﬁ
nished.
ister (0x1B) to conﬁ
gure the next ﬁ
elds
. The
st
ing exposure are the same as the cur
rent draft mode ﬁ
elds,
and the
elds are the still frame readout ﬁ
elds
. The reg
ister
s for the Draft
elds ha
e already been prog
rammed.
alling edge will upda
te the ser
ial wr
ites from 1.
VSUB output tur
ns on a
t the line speciﬁ
ed in
ister (addr 0x68).
4.
STR
OBE output tur
ns on and off a
t the loca
tion speciﬁ
ed in the STR
OBEON
and OFF reg
ister
s (addr 0x6E to 0x71).
5.
MSHUT output tur
ns off a
t the loca
tion speciﬁ
ed in the MSHUT
OFF reg
is-
ter
s (addr 0x6B and 0x6C).
6.
The next
VD f
alling edge will automa
tically star
t the ﬁ
st readout ﬁ
eld.
7.
The next
VD f
alling edge will automa
tically star
t the second readout ﬁ
eld.
8.
The next
VD f
alling edge will automa
tically star
t the third readout ﬁ
eld.
9.
ite to the MODE reg
ister to reconﬁ
gure the single Draft mode ﬁ
eld timing.
ite to the MSHUT
ON reg
ister (addr 0x6A) to open the mechanical shutter
VD/HD f
alling edge will upda
te the ser
ial wr
ites from 9.
VSG outputs retur
n to Draft mode timing.
SUBCK output resumes opera
tion.
MSHUT output retur
ns to the on position (activ
e or open).
VSUB output retur
ns to the off position (inactiv
e).

Partno	Mfg	Dc	Qty	Available	Descript
AD9991KCP	AD	N/a	10	avai	10-Bit CCD Signal Processor with Precision Timing™ Generator