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AD9985BSTZ-110-AD9985KSTZ-110-AD9985KSTZ-140
110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
110 MSPS/140 MSPS Analog Interface for
Flat Panel Displays
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
FEATURES
Automated clamping level adjustment
140 MSPS maximum conversion rate
300 MHz analog bandwidth
0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 110 MSPS
3.3 V power supply
Full sync processing
Sync detect for hot plugging
Midscale clamping
Power-down mode
Low power: 500 mW typical
4:2:2 output format mode
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TV
FUNCTIONAL BLOCK DIAGRAM
RAIN
GAIN
BAIN
SCL
SDA
SOGIN
FILT
HSYNCFigure 1.
GENERAL DESCRIPTION The AD9985 is a complete 8-bit, 140 MSPS, monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode rate
capability and full power analog bandwidth of 300 MHz
support resolutions up to SXGA (1280 × 1024 at 75 Hz).
The AD9985 includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and Hsync and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9985’s on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz
to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9985 also offers full sync
processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9985 is
provided in a space-saving 80-lead LQFP surface-mount
plastic package and is specified over the –40°C to +85°C
temperature range.
TABLE OF CONTENTS Revision History...........................................................................2
Specifications.....................................................................................3
Explanation of Test Levels...........................................................6
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Design Guide...................................................................................11
General Description...................................................................11
Digital Inputs..............................................................................11
Input Signal Handling................................................................11
Hsync, Vsync Inputs...................................................................11
Serial Control Port.....................................................................11
Output Signal Handling.............................................................11
Clamping.....................................................................................11
RGB Clamping........................................................................11
YUV Clamping.......................................................................12
Gain and Offset Control............................................................12
Auto Offset..............................................................................12
Sync-on-Green............................................................................13
Clock Generation.......................................................................13
Power Management....................................................................14
Timing..........................................................................................15
Hsync Timing.............................................................................15
Coast Timing...............................................................................15
2-Wire Serial Register Map.......................................................16
2-Wire Serial Control Register Detail Chip Identification...19
PLL Divider Control..................................................................19
Clock Generator Control..........................................................19
Clamp Timing.............................................................................20
Hsync Pulsewidth.......................................................................20
Input Gain...................................................................................20
Input Offset.................................................................................20
Mode Control 1..........................................................................21
2-Wire Serial Control Port........................................................26
Data Transfer via Serial Interface.............................................26
Sync Slicer....................................................................................28
Sync Separator............................................................................28
PCB Layout Recommendations...............................................29
Analog Interface Inputs.............................................................29
Power Supply Bypassing............................................................29
PLL...............................................................................................30
Outputs (Both Data and Clocks)..............................................30
Digital Inputs..............................................................................30
Voltage Reference.......................................................................30
Outline Dimensions.......................................................................31
Ordering GuIde..........................................................................31
REVISION HISTORY
5/04—Revision 0: Initial Version SPECIFICATIONS Analog Interface: VD = 3.3 V, VDD = 3.3 V, ADC clock = maximum conversion rate, unless otherwise noted.
Table 1.
1 VCO range = 10, charge pump current = 110, PLL divider = 1693. DATACK load = 15 pF, data load = 5 pF.
Table 2.
VCO range = 10, charge pump current = 110, PLL divider = 1693. 2 DATACK load = 15 pF, data load = 5 pF.
EXPLANATION OF TEST LEVELS
Test Level I. 100% production tested.
II. 100% production tested at 25°C and sample tested at specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and characterization testing.
ABSOLUTE MAXIMUM RATINGS
Table 3. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions outside of those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND
GNDGND
GND
COASTHSYNCVSYNC
GND
FILT
GNDV
RED <0
RED <1
RED <2
RED <3
RED <4
RED <5
RED <6
RED <7
GND
GND
GND
VDD
BLUE <7>
BLUE <6>
GND
REF BYPASS
SDA
SCL
RAIN
GND
GND
SOGIN
GAIN
BLUE <5>
BLUE <4>
BLUE <3>
BLUE <2>
BLUE <1>
BLUE <0>
GND
GND
GND
BAIN
GND
GND
MIDSCV
CLAMP
GND
DATACKHSOUT
VSOUTGNDV
GND
Figure 2. Pin Configuration
Table 4. Complete Pinout List
Table 5. Pin Function Descriptions SERIAL PORT (2-Wire)
DATA OUTPUTS
DATA CLOCK OUTPUT
POWER SUPPLY
DESIGN GUIDE
GENERAL DESCRIPTION The AD9985 is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat-panel
monitors or projectors. The circuit is ideal for providing a
computer interface for HDTV monitors or as the front end to
high performance video scan converters. Implemented in a high
performance CMOS process, the interface can capture signals
with pixel rates up to 110 MHz.
The AD9985 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a
2-wire serial interface. Full integration of these sensitive analog
functions makes system design straightforward and less
sensitive to the physical and electrical environment.
With a typical power dissipation of only 500 mW and an
operating temperature range of 0°C to 70°C, the device requires
no special environmental considerations.
DIGITAL INPUTS All digital inputs on the AD9985 operate to 3.3 V CMOS levels.
However, all digital inputs are 5 V tolerant. Applying 5 V to
them will not cause any damage.
INPUT SIGNAL HANDLING The AD9985 has three high impedance analog input pins for
the Red, Green, and Blue channels. They will accommodate
signals ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-pin D connector, or via BNC connectors.
The AD9985 should be located as close as practical to the input
connector. Signals should be routed via matched-impedance
traces (normally 75 Ω) to the IC input pins.
At that point the signal should be resistively terminated (75 Ω
to the signal ground return) and capacitively coupled to the
AD9985 inputs through 47 nF capacitors. These capacitors form
part of the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal
bandwidth. The ultrawide bandwidth inputs of the AD9985
(300 MHz) can track the input signal continuously as it moves
from one pixel level to the next, and digitize the pixel during a
long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
slightly and providing a high quality signal over a wider range
of conditions. Using a Fair-Rite #2508051217Z0 High Speed
Signal Chip Bead inductor in the circuit of Figure 3 gives good
results in most applications.
RGB
INPUT
RAIN
GAIN
BAIN
47nF
75Ω04799-0-003
Figure 3. Analog Input Interface Circuit
HSYNC, VSYNC INPUTS The interface also takes a horizontal sync signal, which is used
to generate the pixel clock and clamp timing. This can be either
a sync signal directly from the graphics source, or a preproc-
essed TTL or CMOS level signal.
The Hsync input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no
termination is required.
SERIAL CONTROL PORT The serial control port is designed for 3.3 V logic. If there are
5 V drivers on the bus, these pins should be protected with
150 Ω series resistors placed between the pull-up resistors and
the input pins.
OUTPUT SIGNAL HANDLING The digital outputs are designed and specified to operate from a
3.3 V power supply (VDD). They can also work with a VDD as low
as 2.5 V for compatibility with other 2.5 V logic.
CLAMPING
RGB Clamping To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board A/D
converters.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground and black is at 300 mV. Then white is at approximately
1.0 V. Some common RGB line amplifier boxes use emitter-
follower buffers to split signals and increase drive capability.
This introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9985.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. An
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to
eliminate offset errors.
In most PC graphics systems, black is transmitted between
active video lines. With CRT displays, when the electron beam
has completed writing a horizontal line on the screen (at the
right side), the beam is deflected quickly to the left side of the
screen (called horizontal retrace), and a black signal is provided
to prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of Hsync. Fortunately, there is virtually
always a period following Hsync, called the back porch, where a
good black reference is provided. This is the time when
clamping should be done.
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time (with External Clamp = 1).
The polarity of this signal is set by the clamp polarity bit.
A simpler method of clamp timing employs the AD9985
internal clamp timing generator. The clamp placement register
is programmed with the number of pixel times that should pass
after the trailing edge of HSYNC before clamping starts. A
second register (clamp duration) sets the duration of the clamp.
These are both 8-bit values, providing considerable flexibility in
clamp generation. The clamp timing is referenced to the trailing
edge of Hsync because, though Hsync duration can vary widely,
the back porch (black reference) always follows Hsync. A good
starting point for establishing clamping is to set the clamp
placement to 09H (providing 9 pixel periods for the graphics
signal to stabilize after sync) and set the clamp duration to 14H
(giving the clamp 20 pixel periods to reestablish the black
reference).
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capacitor
affects the performance of the clamp. If it is too small, there will
be a significant amplitude change during a horizontal line time
(between clamping intervals). If the capacitor is too large, then
it will take excessively long for the clamp to recover from a large
change in incoming signal offset. The recommended value
(47 nF) results in recovering from a step error of 100 mV to
within 1/2 LSB in 10 lines with a clamp duration of 20 pixel
periods on a 60 Hz SXGA signal.
YUV Clamping YUV graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) can be at
the midpoint of the graphics signal rather than at the bottom.
For these signals, it can be necessary to clamp to the midscale
Clamping to midscale rather than to ground can be accom-
plished by setting the clamp select bits in the serial bus register.
Each of the three converters has its own selection bit so that
they can be clamped to either midscale or ground inde-
pendently. These bits are located in Register 10H and are
Bits 0–2. The midscale reference voltage that each A/D
converter clamps to is provided on the MIDSCV pin (Pin 37).
This pin should be bypassed to ground with a 0.1 µF capacitor,
even if midscale clamping is not required.
GAIN
INP
T RANGE
(V
0.504799-0-004
Figure 4. Gain and Offset Control
GAIN AND OFFSET CONTROL The AD9985 can accommodate input signals with inputs
ranging from 0.5 V to 1.0 V full scale. The full-scale range is set
in three 8-bit registers (Red Gain, Green Gain, and Blue Gain).
Note that increasing the gain setting results in an image with less
contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (Red Offset,
Green Offset, Blue Offset) provide independent settings for
each channel. The offset controls provide a ±63 LSB adjustment
range. This range is connected with the full-scale range, so if the
input range is doubled (from 0.5 V to 1.0 V) then the offset step
size is also doubled (from 2 mV per step to 4 mV per step).
Figure 4 illustrates the interaction of gain and offset controls.
The magnitude of an LSB in offset adjustment is proportional to
the full-scale range, so changing the full-scale range also
changes the offset. The change is minimal if the offset setting is
near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same
amount as the zero-scale level.
Auto Offset In addition to the manual offset adjustment mode (via
Registers 0Bh to 0Dh), the AD9985 also includes circuitry to
automatically calibrate the offset for each channel. By
monitoring the output of each ADC during the back porch of
offset errors in its own ADC channels as well as any offset
errors present on the incoming graphics or video signals.
To activate the auto-offset mode, set Register 1Dh, Bit 7 to 1.
Next, the target code registers (19h through 1Bh) must be
programmed. The values programmed into the target code
registers should be the output code desired from the AD9985
during the back porch reference time. For example, for RGB
signals, all three registers would normally be programmed to
code 1, while for YPbPr signals the green (Y) channel would
normally be programmed to code 1 and the blue and red
channels (Pb and Pr) would normally be set to 128. Any target
code value between 1 and 254 can be set, although the AD9985’s
offset range may not be able to reach every value. Intended
target code values range from (but are not limited to) 1 to 40
when ground clamping and 90 to 170 when midscale clamping.
The ability to program a target code for each channel gives
users a large degree of freedom and flexibility. While in most
cases all channels will be set to either 1 or 128, the flexibility to
select other values allows for the possibility of inserting
intentional skews between channels. It also allows for the ADC
range to be skewed so that voltages outside of the normal range
can be digitized. (For example, setting the target code to 40
would allow the sync tip, which is normally below black level, to
be digitized and evaluated.)
Lastly, when in auto offset mode, the manual offset registers
(0Bh to 0Dh) have new functionality. The values in these
registers are digitally added to the value of the ADC output. The
purpose of doing this is to match a benefit that is present with
manual offset adjustment. Adjusting these registers is an easy
way to make brightness adjustments. Although some signal
range is lost with this method, it has proven to be a very popular
function. In order to be able to increase and decrease brightness,
the values in these registers in this mode are signed twos
complement. The digital adder is used only when in auto offset
mode. Although it cannot be disabled, setting the offset registers
to all 0’s will effectively disable it by always adding 0.
SYNC-ON-GREEN The Sync-on-Green input operates in two steps. First, it sets a
baseline clamp level off of the incoming video signal with a
negative peak detector. Second, it sets the sync trigger level to a
programmable level (typically 150 mV) above the negative peak.
The Sync-on-Green input must be ac-coupled to the Green
analog input through its own capacitor, as shown in Figure 5.
The value of the capacitor must be 1 nF ±20%. If Sync-on-
Green is not used, this connection is not required. Note that the
Sync-on-Green signal is always negative polarity.
04799-0-005
Figure 5. Typical Clamp Configuration
CLOCK GENERATION A phase-locked loop (PLL) is employed to generate the pixel
clock. In this PLL, the Hsync input provides a reference
frequency. A voltage controlled oscillator (VCO) generates a
much higher pixel clock frequency. This pixel clock is divided
by the PLL divide value (Registers 01H and 02H) and phase
compared with the Hsync input. Any error is used to shift the
VCO frequency and maintain lock between the two signals.
The stability of this clock is a very important element in
providing the clearest and most stable image. During each pixel
time, there is a period during which the signal is slewing from
the old pixel amplitude and settling at its new value. Then there
is a time when the input voltage is stable, before the signal must
slew to a new value (Figure 6). The ratio of the slewing time to
the stable time is a function of the bandwidth of the graphics
DAC and the bandwidth of the transmission system (cable and
termination). It is also a function of the overall pixel rate.
Clearly, if the dynamic characteristics of the system remain
fixed, the slewing and settling time is likewise fixed. This time
must be subtracted from the total pixel period, leaving the stable
period. At higher pixel frequencies, the total cycle time is
shorter, and the stable pixel time becomes shorter as well.
PIXEL CLOCKINVALID SAMPLE TIMES04799-0-006
Figure 6. Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined, and must also be subtracted
from the stable pixel time.
Considerable care has been taken in the design of the AD9985’s
clock generation circuit to minimize jitter. As indicated in
Figure 7, the clock jitter of the AD9985 is less than 5% of the
total pixel time in all operating modes, making the reduction in
the valid sampling time due to jitter negligible.
FREQUENCY (MHz)
CLO
CK J
ITTE
R (p-p) (%)04799-0-007
Figure 7. Pixel Clock Jitter vs. Frequency
The PLL characteristics are determined by the loop filter design,
by the PLL charge pump current, and by the VCO range setting.
The loop filter design is illustrated in Figure 8. Recommended
settings of VCO range and charge pump current for VESA
standard display modes are listed in Table 9.
0.0082µF
FILT04799-0-008
Figure 8. PLL Loop Filter Detail
Four programmable registers are provided to optimize the
performance of the PLL:
1. The 12-Bit Divisor Register. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock
frequencies in the range of 12 MHz to 110 MHz. The
Divisor register controls the exact multiplication factor.
This register may be set to any value between 221 and 4095.
(The divide ratio that is actually used is the programmed
divide ratio plus one.)
2. The 2-Bit VCO Range Register. To improve the noise
performance of the AD9985, the VCO operating frequency
range is divided into three overlapping regions. The VCO
range register sets this operating range. Table 6 lists the
frequency ranges for the lowest and highest regions.
Table 6. VCO Frequency Ranges 3. The 3-Bit Charge Pump Current Register. This register
allows the current that drives the low-pass loop filter to be
varied. The possible current values are listed in Table 7.
Table 7. Charge Pump Current/Control Bits 4. The 5-Bit Phase Adjust Register. The phase of the gen-
erated sampling clock may be shifted to locate an optimum
sampling point within a clock cycle. The phase adjust
register provides 32 phase-shift steps of 11.25° each. The
Hsync signal with an identical phase shift is available
through the HSOUT pin.
The COAST pin is used to allow the PLL to continue to
run at the same frequency, in the absence of the incoming
Hsync signal or during disturbances in Hsync (such as
equalization pulses). This may be used during the vertical
sync period, or any other time that the Hsync signal is
unavailable. The polarity of the COAST signal may be set
through the coast polarity register. Also, the polarity of the
Hsync signal may be set through the Hsync polarity
register. If not using automatic polarity detection, the
Hsync and COAST polarity bits should be set to match the
respective polarities of the input signals.
POWER MANAGEMENT The AD9985 uses the activity detect circuits, the active interface
bits in the serial bus, the active interface override bits, and the
power-down bit to determine the correct power state. There are
three power states—full-power, seek mode, and power-down.
Table 8 summarizes how the AD9985 determines what power
mode to be in and which circuitry is powered on/off in each of
these modes. The power-down command has priority over the
automatic circuitry.
Table 8. Power-Down Mode Descriptions
Table 9. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
TIMING The following timing diagrams show the operation of the
AD9985.
The output data clock signal is created so that its rising edge
always occurs between data transitions and can be used to latch
the output data externally.
There is a pipeline in the AD9985, which must be flushed before
valid data becomes available. This means that four data sets are
presented before valid data is available.
DATAHSOUT04799-0-009
Figure 9. Output Timing
HSYNC TIMING Horizontal Sync (Hsync) is processed in the AD9985 to
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with
respect to Hsync, through a full 360° in 32 steps via the phase
adjust register (to optimize the pixel sampling time). Display
systems use Hsync to align memory and display write cycles, so
it is important to have a stable timing relationship between
Hsync output (HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9985. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be
programmed either active high or active low (Register 0EH,
Bit 5). Second, HSOUT is aligned with DATACK and data
outputs. Third, the duration of HSOUT (in pixel clocks) is set
via Register 07H. HSOUT is the sync signal that should be used
to drive the rest of the display system.
COAST TIMING In most computer systems, the Hsync signal is provided
continuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary and should not be used, and
the pin should be permanently connected to the inactive state.
disappear. In other systems, such as those that employ
Composite Sync (Csync) signals or embedded Sync-on-Green
(SOG), Hsync includes equalization pulses or other distortions
during Vsync. To avoid upsetting the clock generator during
Vsync, it is important to ignore these distortions. If the pixel
clock PLL sees extraneous pulses, it will attempt to lock to this
new frequency, and will have changed frequency by the end of
the Vsync period. It will then take a few lines of correct Hsync
timing to recover at the beginning of a new frame, resulting in a
“tearing” of the image at the top of the display.
The COAST input is provided to eliminate this problem. It is an
asynchronous input that disables the PLL input and allows the
clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
RGBIN
HSYNC
PxCK
ADCCK
DATACK
DOUTA
HSOUT04799-
Figure 10. 4:4:4 Mode (For RGB and YUV)
RGBIN
HSYNC
PxCK
ADCCK
GOUTA
HSOUTROUTA
VARIABLE DURATIONFigure 11. 4:2:2 Mode (For YUV Only)
2-WIRE SERIAL REGISTER MAP The AD9985 is initialized and controlled by a set of registers, that determine the operating modes. An external controller is employed to
write and read the control registers through the two-line serial interface port.
Table 10. Control Register Map
