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AD9958BCPZ
2-Channel 500 MSPS DDS with 10-Bit DACs
2-Channel 500 MSPS DDS
with 10-Bit DACs
FEATURES
2 synchronized DDS channels @ 500 MSPS
Independent frequency/phase/amplitude control between
channels
Matched latencies for frequency/phase/amplitude changes
Excellent channel-to-channel isolation (>72 dB)
Linear frequency/phase/amplitude sweeping capability
Up to 16 levels of frequency/phase/amplitude modulation
(pin-selectable)
2 integrated 10-bit D/A converters (DACs)
Individually programmable DAC full-scale currents
32-bit frequency tuning resolution
14-bit phase offset resolution
10-bit output amplitude scaling resolution
Serial I/O Port (SPI) with 800Mbps data throughput
Software-/hardware-controlled power-down
Dual supply operation (1.8 V DDS core/3.3 V serial I/O)
Multiple device synchronization
Selectable 4× to 20× REF_CLK multiplier (PLL)
Selectable REF_CLK crystal oscillator
56-Lead LFCSP
APPLICATIONS
Agile local oscillator
Phased array radar/sonar
Instrumentation
Synchronized clocking
RF source for AOTF
Single-side band suppressed carrier
Quadrature communications
FUNCTIONAL BLOCK DIAGRAM
IOUT
IOUT
SYNC_CLK
CLK_MODE_SEL
AVDDDVDD
SYNC_IN
SYNC_OUT
I/O_UPDATE
IOUTIOUT
DAC_RSET
REF_CLK
REF_CLK
PWR_DWN_CTL
SCLK
SDIO_0SDIO_1
SDIO_2SDIO_3
PS0PS1PS2PS3DVDD_I/OFigure 1.
TABLE OF CONTENTS Features..............................................................................................1
Applications.......................................................................................1
Functional Block Diagram..............................................................1
General Description.........................................................................3
Specifications.....................................................................................4
Absolute Maximum Ratings............................................................8
ESD Caution..................................................................................8
Equivalent Input and Output Circuits.......................................8
Pin Configuration and Function Descriptions.............................9
Typical Performance Characteristics...........................................11
Application Circuits.......................................................................14
Theory of Operation......................................................................17
DDS Core.....................................................................................17
D/A Converter............................................................................17
Modes of Operation.......................................................................18
Channel Constraint Guidelines................................................18
Power Supplies............................................................................18
Single-Tone Mode......................................................................18
Reference Clock Modes.............................................................19
Scalable DAC Reference Current Control Mode...................20
Power-Down Functions.............................................................20
Modulation Mode.......................................................................20
Modulation Using SDIO Pins for RU/RD...............................22
Linear Sweep (Shaped) Modulation Mode.............................22
Linear Sweep—No-Dwell Mode...............................................24
Sweep and Phase Accumulator Clearing Functions..............25
Output Amplitude Control Mode............................................26
Synchronizing Multiple AD9958 Devices...................................27
Automatic Mode Synchronization...........................................27
Manual Software Mode Synchronization................................27
Manual Hardware Mode Synchronization..............................27
I/O_Update, SYNC_CLK, and System Clock Relationships28
Serial I/O Port.................................................................................29
Overview.....................................................................................29
Instruction Byte Description....................................................30
Serial I/O Port Pin Description................................................30
Serial I/O Port Function Description......................................30
MSB/LSB Transfer Description................................................30
Serial I/O Modes of Operation.................................................31
Register Maps..................................................................................34
Control Register Map................................................................34
Channel Register Map...............................................................35
Profile Register Map...................................................................35
Control Register Descriptions......................................................36
Channel Select Register (CSR).................................................36
Channel Function Register (CFR) Description......................37
Outline Dimensions.......................................................................39
Ordering Guide..........................................................................39
REVISION HISTORY
9/05—Revision 0: Initial Version GENERAL DESCRIPTION The AD9958 consists of two DDS cores that provide indepen-
dent frequency, phase, and amplitude control on each channel.
This flexibility can be used to correct imbalances between
signals due to analog processing such as filtering, amplification,
or PCB layout related mismatches. Since both channels share a
common system clock, they are inherently synchronized.
Synchronization of multiple devices is supported.
The AD9958 can perform up to a 16-level modulation of
frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is
performed by applying data to the profile pins. In addition, the
AD9958 also supports linear sweep of frequency, phase, or
amplitude for applications such as radar and instrumentation.
The AD9958 serial I/O port offers multiple configurations to
provide significant flexibility. The serial I/O port offers an SPI-
compatible mode of operation that is virtually identical to the
SPI operation found in earlier Analog Devices DDS products.
Flexibility is provided by four data pins (SDIO_0:3) that allow
four programmable modes of serial I/O operation.
The AD9958 uses advanced DDS technology that provides low
power dissipation with high performance. The device
incorporates two integrated, high speed 10-bit DACs with
excellent wideband and narrowband SFDR. Each channel has a
dedicated 32-bit frequency tuning word, 14 bits of phase offset,
and a 10-bit output scale multiplier.
The DAC outputs are supply referenced and must be termin-
ated into AVDD by a resistor or an AVDD center-tapped
transformer. Each DAC has its own programmable reference to
enable different full-scale currents for each channel.
The DDS acts as a high resolution frequency divider with the
REF_CLK as the input and the DAC providing the output. The
REF_CLK input source is common to both channels and can be
driven directly or used in combination with an integrated
REF_CLK multiplier (PLL) up to a maximum of 500 MSPS. The
PLL multiplication factor is programmable from 4 to 20, in
integer steps. The REF_CLK input also features an oscillator
circuit to support an external crystal as the REF_CLK source.
The crystal must be between 20 MHz and 30 MHz. The crystal
can be used in combination with the REF_CLK multiplier.
The AD9958 comes in a space-saving 56-lead LFCSP package.
The DDS core (AVDD and DVDD pins) is powered by a 1.8 V
supply. The digital I/O interface (SPI) operates at 3.3 V and
requires the pin labeled DVDD_I/O (Pin 49) be connected
to 3.3 V.
The AD9958 operates over the industrial temperature range of
−40°C to +85°C.
SPECIFICATIONS AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; RSET = 1.91 kΩ; external reference clock frequency = 500 MSPS (REF_CLK
multiplier bypassed), unless otherwise noted.
Table 1.
For the VCO frequency range of 160 MHz to 255 MHz there is no guarantee of operation. 2 Data latency is reference to the I/O_UPDATE> Data latency is fixed.
4 Data latency is referenced to a profile change.
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
EQUIVALENT INPUT AND OUTPUT CIRCUITS
CMOS
DIGITAL
INPUTS
AVOID OVERDRIVING
DIGITAL INPUTS.
FORWARD BIASING
DIODES MAY COUPLE
DIGITAL NOISE ON
POWER PINS.
DVDD_I/O = 3.3V
INPUTOUTPUTDAC OUTPUTS
TERMINATE OUTPUTS
INTO AVDD. DO NOT
EXCEED OUTPUTS'
VOLTAGE COMPLIANCE.IOUT
REF_CLK INPUTS
REF_CLK INPUTS ARE
INTERNALLY BIASED AND
NEED TO BE AC-COUPLED.
OSC INPUTS ARE DC-
COUPLED.
REF_CLKREF_CLK
1.5kΩ
AVDD
Figure 2.
Figure 3.
Figure 4.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NC = NO CONNECTSYNC_INSYNC_OUTMASTER_RESETPWR_DWN_CTLAVDDAGNDAVDDCH0_IOUTCH0_IOUTAGNDAVDDAGNDCH1_IOUTCH1_IOUTAVDDAVDDAVDDNCAVDDP0P1P2NCAVDDNCAVDDAVDDAVDD
I/O
I/O
TOP VIEW
(Not to Scale)
AD9958
NOTES
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS
AN ELECTRICAL CONNECTION AND MUST BE
SOLDERED TO GROUND.
2. PIN 49 IS DVDD_IO AND IS TIED TO 3.3V.05252-005
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
TYPICAL PERFORMANCE CHARACTERISTICS
(dB)
–90START 0HzSTOP 250MHz25MHz/DIV
DELTA 1 (T1)
–71.73dB
4.50901804MHz
RBW20kHzRF ATT20dB
VBW20kHz
SWT1.6sUNITdB
REF LVL
0dBm
1AP
Figure 6. fOUT = 1.1 MHz, fCLK = 500 MSPS, Wideband SFDR
(dB)
–90START 0HzSTOP 250Hz25MHz/DIV
DELTA 1 (T1)
–62.84dB
40.08016032MHz
RBW20kHzRF ATT20dB
VBW20kHz
SWT1.6sUNITdB
REF LVL
0dBm
1AP
Figure 7. fOUT = 40.1 MHz, fCLK = 500 MSPS, Wideband SFDR
(dB)
–90START 0HzSTOP 250MHz25MHz/DIV
DELTA 1 (T1)
–59.04dB
100.70140281MHz
RBW20kHzRF ATT20dB
VBW20kHz
SWT1.6sUNITdB
REF LVL
0dBm
1AP
(dB)
–90START 0HzSTOP 250MHz25MHz/DIV
DELTA 1 (T1)
–69.47dB
30.06012024MHz
RBW20kHzRF ATT20dB
VBW20kHz
SWT1.6sUNITdB
REF LVL
0dBm
1AP
Figure 9. fOUT = 15.1 MHz, fCLK = 500 MSPS, Wideband SFDR
(dB)
–90START 0HzSTOP 250MHz25MHz/DIV
DELTA 1 (T1)
–60.13dB
75.15030060MHz
RBW20kHzRF ATT20dB
VBW20kHz
SWT1.6sUNITdB
REF Lv]
0dBm
1AP
Figure 10. fOUT = 75.1 MHz, fCLK = 500 MSPS, Wideband SFDR
(dB)
–90START 0HzSTOP 250MHz25MHz/DIV
DELTA 1 (T1)
–53.84dB
–101.20240481MHz
RBW20kHzRF ATT20dB
VBW20kHz
SWT1.6sUNITdB
REF LVL
0dBm
1AP
(dB)
–90CENTER 1.1MHzSPAN 1MHz100kHz/DIV
DELTA 1 (T1)
–84.73dB
254.50901604kHz
RBW500HzRF ATT20dB
VBW500Hz
SWT20sUNITdB
REF LVL
0dBm
1AP
Figure 12. fOUT = 1.1 MHz, fCLK = 500 MSPS, NBSFDR, ±1 MHz
(dB)
CENTER 40.1MHzSPAN 1MHz100kHz/DIV
DELTA 1 (T1)
–84.10dB
120.24048096kHz
RBW500HzRF ATT20dB
VBW500Hz
SWT20sUNITdB
REF LVL
0dBmFigure 13. fOUT = 40.1 MHz, fCLK = 500 MSPS, NBSFDR, ±1 MHz
(dB)
–90CENTER 100.3MHzSPAN 1MHz100kHz/DIV
DELTA 1 (T1)–82.63dB400.80160321kHz
RBW500HzRF ATT20dB
VBW500Hz
SWT20sUNITdB
REF LVL
0dBm
1AP
(dB)
CENTER 15.1MHzSPAN 1MHz100kHz/DIV
DELTA 1 (T1)
–84.86dB
–200.40080160kHz
RBW500HzRF ATT20dB
VBW500Hz
SWT20sUNITdB
REF LVL
0dBmFigure 15. fOUT = 15.1 MHz, fCLK = 500 MSPS, NBSFDR, ±1 MHz
(dB)
CENTER 75.1MHzSPAN 1MHz100kHz/DIV
DELTA 1 (T1)
–86.03dB
262.56513026kHz
RBW500HzRF ATT20dB
VBW500Hz
SWT20sUNITdB
REF LVL
0dBmFigure 16. fOUT = 75.1 MHz, fCLK = 500 MSPS, NBSFDR, ±1 MHz
(dB)
CENTER 200.3MHzSPAN 1MHz
100kHz/DIV
DELTA 1 (T1)
–83.72dB
–400.80160321kHz
RBW500HzRF ATT20dB
VBW500Hz
SWT20sUNITdB
REF LVL
0dBm–1001001k10k100k1M10M
FREQUENCY OFFSET (Hz)
SE N
OISE (Figure 18. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1MHz,
75.1 MHz, 100.3 MHz, fCLK = 500 MHz with REF_CLK Multiplier Bypassed
–1701010MFREQUENCY OFFSET (Hz)
HAS
NOIS
(dBc
/Hz)
1001k10k100k1M
Figure 19. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1MHz,
75.1 MHz, 100.3 MHz, fCLK = 500 MHz with REF_CLK Multiplier = 5x
–1701010MFREQUENCY OFFSET (Hz)
HAS
NOIS
(dBc
/Hz)
1001k10k100k1M
Figure 20. Residual Phase Noise(SSB) with fOUT = 15.1 MHz, 40.1MHz,
75.1 MHz,100.3 MHz, fCLK = 500 MHz with REF_CLK Multiplier = 20×
FREQUENCY OFCOUPLINGSPUR(MHz)
HANNE
Bc)
50.375.3100.3125.3150.3175.3Figure 21. Channel Isolation at 500 MSPS Operation. Conditions are Channel
of Interest Fixed at 110.3 MHz, the Other Channels Are Frequency Swept.
REFERENCE CLOCK FREQUENCY (MHz)
TOTAL POWER DISSIPATION (mW)
45040035030025020015010050Figure 22. Reference Clock Frequency vs. Power Dissipation vs. Channel(s)
Power On/Off
FOUT (MHz)
DR (dBc
15.140.175.1100.3200.3Figure 23. Averaged Channel SFDR vs. fOUT
APPLICATION CIRCUITS
ANTENNARADIATINGELEMENTSFigure 24. Phase Array Radar Using Precision Frequency/Phase Control from DDS in FMCW or Pulsed Radar Applications.
DDS Provides Either Continuous Wave or Frequency Sweep.
Q BASEBAND
RF OUTPUT
REF CLK
CH 1
AD8348
AD8347
AD8346
ADL5390Figure 25. Single-Sideband-Suppressed Carrier-Up Conversion
REFERENCE05252-026
Figure 26. DDS in PLL Locking to Reference Offering Distribution with Fine Frequency and Delay Adjust Tuning
05252-027
Figure 27. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and SYNC Clock
OPTICAL FIBER CHANNELW/MULITIPLE DISCRETEWAVELENGTHS
SELECTABLEWAVELENGTH FROM EACHCHANNEL VIA DDS TUNINGAOTF
WDM SIGNAL05252-028
Figure 28. DDS Providing Stimulus for Acoustic Optical Tunable Filter
05252-029
Figure 29. Agile Clock Source with Duty Cycle Control Using the Phase Offset Value in DDS to Change the DC Voltage to Comparator
LVPECLLVDSCMOS
PROGRAMMABLE 1TO 32DIVIDERAND DELAYADJUST
CLOCK OUTPUTSELECTION(S)
n = DEPENDENT ONPRODUCT SELECTION
LVPECLLVDSCMOS05252-030
Figure 30. Clock Generation Circuit Using the AD951x Series of Clock Distribution Chips
THEORY OF OPERATION
DDS CORE The AD9958 has two DDS cores each consisting of a 32-bit
phase accumulator and phase-to-amplitude converter. Together
these digital blocks generate a digital sine wave when the phase
accumulator is clocked and the phase increment value
(frequency tuning word) is greater than 0. The phase-to-
amplitude converter simultaneously translates phase
information to amplitude information by a COS (θ) operation.
The output frequency (fO) of each DDS channel is a function of
the rollover rate of each phase accumulator. The exact
relationship is given in the following equation: 202)((≤≤=FTWwithfFTWfS
where:
fS = the system clock rate.
FTW = the frequency tuning word. 32 represents the phase accumulator’s capacity.
Since both channels share a common system clock, they are
inherently synchronized.
The DDS core architecture also supports the capability to phase
offset the output signal. This is performed by the channel phase
offset word (CPOW). The CPOW is a 14-bit register that stores
a phase offset value. This value is added to the output of the
phase accumulator to offset the current phase of the output
signal. Each channel has its own phase offset word register. This
feature can be used for placing both channels in a known phase
relationship relative to one another. The exact value of phase
offset is given by the following equation: ×⎟⎠⎜⎝=Φ360214
POW
D/A CONVERTER The AD9958 incorporates two 10-bit current output DACs. The
DAC converts a digital code (amplitude) into a discrete analog
quantity. The DAC’s current outputs can be modeled as a
current source with high output impedance (typically 100 kΩ).
Unlike many DACs, these current outputs require termination
into AVDD via a resistor or a center-tapped transformer for
expected current flow.
Each DAC has complementary outputs that provide a combined
full-scale output current (IOUT + IOUTB). The outputs always sink
current and their sum equals the full-scale current at any point
in time. The full-scale current is controlled by means of an
external resistor (RSET) and the scalable DAC current control
bits discussed in the Modes of Operation section. The resistor
RSET is connected between the DAC_RSET pin and analog
ground (AGND). The full-scale current is inversely
proportional to the resistor value as follows:
OUT
SETIR91.18=
The maximum full-scale output current of the combined DAC
outputs is 15 mA, but limiting the output to 10 mA provides
optimal spurious-free dynamic range (SFDR) performance. The
DAC output voltage compliance range is AVDD + 0.5 V to
AVDD − 0.5 V. Voltages developed beyond this range can cause
excessive harmonic distortion. Proper attention should be paid
to the load termination to keep the output voltage within its
compliance range. Exceeding this range could potentially
damage the DAC output circuitry.
LPF
1:105252-031
Figure 31. Typical DAC Output Termination Configuration
MODES OF OPERATION There are many combinations of modes (for example, single-
tone, modulation, linear sweep) that the AD9958 can perform
simultaneously. However, some modes require multiple data
pins, which can impose limitations. The following guidelines
can help determine if a specific combination of modes can be
performed simultaneously by the AD9958.
Note the SYNC_CLK must be enabled in all modes except
single-tone mode.
CHANNEL CONSTRAINT GUIDELINES 1. Single tone generation, 2-level modulation, and linear
sweep modes can be enabled on either channel and in any
combination simultaneously.
2. Both channels can perform 4-level modulation
simultaneously.
3. Either channel can perform 8-level or 16-level modulation.
The other channel can only be in single-tone mode.
4. The RU/RD function can be used on both channels in
single-tone generation mode. See the Output Amplitude
Control Mode section for the RU/RD function.
5. When Profile Pins P2 and P3 are used for RU/RD, either
channel can perform 2-level modulation with RU/RD or
both channels can perform linear frequency or phase
sweep with RU/RD.
6. When Profile Pin P3 is used for RU/RD, either channel can
be used in 8-level modulation with RU/RD. The other
channel can only be in single-tone generation mode.
7. When SDIO_1:3 pins are used for RU/RD, either or both
channels can perform 2-level modulation with RU/RD. If
one channel is not in 2-level modulation it can only be in
single-tone generation mode.
8. When the SDIO_1:3 pins are used for RU/RD, either or
both channels can perform 4-level modulation with
RU/RD. If one channel is not in 4-level modulation it can
only be in single-tone generation mode.
9. When the SDIO_1:3 pins are used for RU/RD, either
channel can perform 8-level modulation with RU/RD. The
other channel can only be in single-tone generation mode.
10. When the SDIO_1:3 pins are used for RU/RD, either
channel can perform 16-level modulation with RU/RD.
The other channel can only be in single-tone generation
mode.
11. Amplitude modulation, linear amplitude sweep modes,
and the RU/RD function cannot operate simultaneously,
POWER SUPPLIES The AVDD and DVDD supply pins provide power to the DDS
core and supporting analog circuitry. These pins connect to a
1.8 V nominal power supply.
The DVDD_I/O pin connects to a 3.3 V nominal power
supply. All digital inputs are 3.3 V logic except for the
CLK_MODE_SEL input. The CLK_MODE_SEL (Pin 24) is
an analog input and should be operated by 1.8 V logic.
SINGLE-TONE MODE Single-tone mode is the default mode of operation after a
master reset signal. In this mode, both DDS channels share a
common address location for the frequency tuning word
(Register 0x04) and phase offset word address location
(Register 0x05). Channel enable bits are provided in combi-
nation with these shared addresses. As a result, the frequency
tuning word and/or phase offset word can be independently
programmed between channels (see the following Step 1
through Step 5). The channel enable bits do not require an I/O
update to enable or disable a channel.
See the Register Map section for a description of the channel
enable bits in the channel select register or CSR (Register 0x00).
The channel enable bits are enabled or disabled immediately
after the CSR’s data byte is written.
Address sharing enables channels to be written simultaneously,
if desired. The default state enables all channel enable bits.
Therefore, the frequency tuning word and/or phase offset word
is common to both channels, but written only once through the
serial I/O port.
The following steps present a basic protocol to program a
different frequency tuning word and/or phase offset word for
each channel using the channel enable bits.
1. Power up DUT and issue a master reset. A master reset
places the part in single-tone mode and single-bit mode for
serial programming operations (refer to the Serial I/O
Modes of Operation section). Frequency tuning words and
phase offset words default to 0 at this point.
2. Enable only one channel enable bit (Register 0x00), disable
the other channel enable bit.
3. Using the serial I/O port, program the desired frequency
tuning word (Register 0x04) and/or the phase offset word
(Register 0x05) for the enabled channel.
4. Repeat Step 2 and Step 3 for each channel.
5. Send an I/O update signal. After an I/O update, both
Single-Tone Mode—Matched Pipeline Delay In single-tone mode, the AD9958 offers matched pipeline delay
to the DAC input for all frequency, phase, and amplitude
changes. This avoids having to deal with different pipeline
delays between the three input ports for such applications. The
feature is enabled by asserting the match pipeline delay bit
found in the channel function register (CSR) (Register 0x03).
This feature is available in single-tone mode only.
REFERENCE CLOCK MODES The AD9958 supports multiple reference clock configurations
to generate the internal system clock. As an alterative to
clocking the part directly with a high frequency clock source,
the system clock may be generated using the internal, PLL-
based reference clock multiplier. An on-chip oscillator circuit is
also available for providing a low frequency reference signal by
connecting a crystal to the clock input pins. Enabling these
features allows the part to operate with a low frequency clock
source and still provide a high update rate for the DDS and
DAC. However, using the clock multiplier changes the output
phase noise characteristics. For best phase noise performance, a
clean, stable clock with a high slew is required. Refer to
Figure 19 and Figure 20.
Enabling the PLL allows multiplication of the reference clock
frequency from 4× to 20×, in integer steps. The PLL
multiplication value is represented by a 5-bit multiplier value.
These bits are located in the Function Register 1 (FR1),
bits <22:18>. Refer to the Register Map.
When FR1 <22:18> is programmed with values ranging from 4
to 20 (decimal) the clock multiplier is enabled. The integer
value in the register represents the multiplication factor. The
system clock rate with the clock multiplier enabled is equal to
the reference clock rate times the multiplication factor. If FR1
<22:18> is programmed with a value less than 4 or greater than
20 the clock multiplier is disabled and the multiplication factor
is effectively 1.
Whenever the PLL clock multiplier is enabled or the
multiplication value is changed, time should be allowed to lock
the PLL (typically 1 ms).
Note that the output frequency of the PLL is restricted to a
frequency range of 100 MHz to 500 MHz. However, there is a
VCO gain bit that must be used appropriately. The VCO gain
bit defines two ranges (low/high) of frequency output. The
VCO gain bit defaults to low (see Specifications for details).
The charge pump current in the PLL defaults to 75 µA. This
setting typically produces the best phase noise characteristics.
Increasing charge pump current may degrade phase noise, but
decreases the lock time and changes the loop bandwidth.
Enabling the on-chip oscillator for crystal operation is per-
formed by driving the CLK_MODE_SEL (Pin 24) to logic high
(1.8 V logic). With the on-chip oscillator enabled, connection of
an external crystal to the REF_CLK and REF_CLKB inputs is
made producing a low frequency reference clock. The crystal’s
frequency must be in the range of 20 MHz to 30 MHz.
Table 4 summarizes the clock modes of operation. See the
Specifications section for more details.
Table 4.
Reference Clock Input Circuitry The reference clock input circuitry has two modes of operation
controlled by the logic state of Pin 24 (clock mode select). The
first mode (logic low) configures as an input buffer. In this
mode, the reference clock must be ac-coupled to the input due
to internal dc biasing. This mode supports either differential
or single-ended configurations. If single-ended mode is
chosen, the complementary reference clock input (Pin 23)
should be decoupled to AVDD or AGND via a 0.1 µF capacitor.
Figure 32 and Figure 34 exemplify typical reference clock
configurations for the AD9958.
1:1
PIN 23REFERENCE
CLOCK
SOURCE
PIN 22
0.1µF
0.1µF05252-032
Figure 32.
The reference clock inputs can also support an LVPECL or
PECL driver as the reference clock source.
PIN 23
PIN 2205252-033
Figure 33.
The second mode of operation (Pin 24 = logic high = 1.8 V)
provides an internal oscillator for crystal operation. In this
mode, both clock inputs are dc-coupled via the crystal leads and
bypassed. The range of crystal frequencies supported is from
REF_CLK
PIN 23
25MHz
XTAL
PIN 2205252-034
Figure 34.
SCALABLE DAC REFERENCE CURRENT CONTROL
MODE The RSET is common to both DACs. As a result, the full-scale
currents are equal as a default. The scalable DAC reference can
be used to set each DAC’s full-scale current independently from
one another. This is accomplished by using the CFR register bits
<9:8>. Table 5 shows how each DAC can be individually scaled
for independent channel control. This provides for binary
attenuation.
Table 5.
POWER-DOWN FUNCTIONS The AD9958 supports an externally controlled power-down
feature and the more common software programmable power-
down bits found in previous Analog Devices DDS products.
The software control power down allows the input clock
circuitry, DAC, and the digital logic (for each separate channel)
to be individually powered down via unique control bits
(CFR <7:6>). These bits are not active when the externally
controlled power-down pin (PWR_DWN_CTL) is high. When
the PWR_DWN_CTL input pin is high, the AD9958 enters a
power-down mode based on the FR1 <6> bit. When the
PWR_DWN_CTL input pin is low, the external power-down
control is inactive.
When the FR1 <6> bit is zero, and the PWR_DWN_CTL input
pin is high, the AD9958 is put into a fast recovery power-down
mode. In this mode, the digital logic and the DACs digital logic
are powered down. The DACs bias circuitry, oscillator, and
clock input circuitry is not powered down.
When the FR1 <6> bit is high and the PWR_DWN_CTL pin is
high, the AD9958 is put into the full power-down mode. In this
mode, all functions are powered down. This includes the DACs
and PLL, which take a significant amount of time to power up.
When the PLL is bypassed, the PLL is shut down to conserve
power.
When the PWR_DWN_CTL input pin is high, the individual
power down bits (CFR <7:6>) and FR1 <7>) are invalid (don’t
care) and are unused. When the PWR_DWN_CTL input pin is
low, the individual power-down bits control the power-down
modes of operation.
Note that the power-down signals are all designed such that a
Logic 1 indicates the low power mode and Logic 0 indicates the
powered-up mode.
MODULATION MODE The AD9958 can perform 2-/4-/8- or 16-level modulation of
frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is
achieved by applying data to the profile pins. Each channel can
be programmed separately, but the ability to modulate both
channels simultaneously is constrained by the limited number
of profile pins. For instance, 16-level modulation uses all four
profile pins, which inhibits modulation for the remaining
channel.
In addition, the AD9958 has the ability to ramp up or ramp
down the output amplitude before, during, or after a
modulation (FSK, PSK only) sequence. This is performed by
using the 10-bit output scalar. If the RU/RD feature is desired,
unused profile pins or unused SDIO_1:3 pins can be configured
to initiate the operation. See the Output Amplitude Control
Mode section for more details of the RU/RD feature.
In modulation mode, each channel has its own set of control
bits to determine the type (frequency, phase, or amplitude) of
modulation. Each channel has 16 profile registers for flexibility.
Register Addresses 0x0A through 0x18 are profile registers for
modulation of frequency, phase, or amplitude. Registers 0x04,
0x05, and 0x06 are dedicated registers for frequency, phase, and
amplitude, respectively. These registers contain the first
frequency, phase offset, and amplitude word.
Frequency modulation has a 32-bit resolution, phase modula-
tion is 14 bits, and amplitude is 10 bits. When modulating phase
or amplitude, the word value must be MSB-aligned in the
profile registers and the unused bits are don’t care bits.
In modulation mode, AFP bits (CFR <23:22>) and level bits
(FR1 <9:8>) are programmed to configure the modulation type
and level. See Table 6 and Table 7 settings. Note that the linear
sweep enable bit must be set to Logic 0 in direct modulation
mode.
Table 6.
