AD9956YCPZ Fast Delivery |IC PHOENIX CO.,LIMITED

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AD9956YCPZ
400 MSPS 14-Bit DAC 48-Bit FTW 1.8 V CMOS DDS Based AgileRF™ Synthesizer
2.7 GHz DDS-Based AgileRFTM SynthesizerRev. A
FEATURES
400 MSPS internal DDS clock speed
48-bit frequency tuning word
14-bit programmable phase offset
Integrated 14-bit DAC
Excellent dynamic performance
Phase noise ≤ 135 dBc/Hz @ 1 KHz offset
−80 dB SFDR @ 160 MHz (±100 KHz offset IOUT)
25 Mb/s write-speed serial I/O control
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase
frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 phase/frequency profiles
1.8 V supply for device operation
3.3 V supply for I/O and charge pump
Software controlled power-down
48-lead LFCSP package
Automatic linear frequency sweeping capability (in DDS)
Programmable charge pump current (up to 4 mA)
Phase modulation capability
Multichip synchronization
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant driver
APPLICATIONS
Agile LO frequency synthesis
FM chirp source for radar and scanning systems
Automotive radars
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
PS<2:0>RESETI/OPORT
CP_OUT
CP_RSET
PLL_LOCK/SYNC_IN
I/O_UPDATE
SYNC_OUT
REFCLK
REFCLK
DRVDRVDRV_RSET
DAC_RSET
IOUT
IOUT
I/O_RESET
PLLREF/
PLLREF
PLLOSC/
PLLOSC
04806-0-001
Figure 1.
TABLE OF CONTENTS
Product Overview.............................................................................3
Specifications.....................................................................................4
Loop Measurement Conditions..................................................9
Absolute Maximum Ratings..........................................................10
ESD Caution................................................................................10
Pin Configuration and Function Descriptions...........................11
Typical Performance Characteristics...........................................13
Typical Application Circuits..........................................................16
Application Circuit Explanations.............................................17
General Description.......................................................................18
DDS Core.....................................................................................18
PLL Circuitry..............................................................................18
CML Driver.................................................................................19
Modes of Operation.......................................................................20
DDS Modes of Operation.........................................................20
Synchronization Modes for Multiple Devices..............................20
Serial Port Operation.....................................................................22
Instruction Byte..........................................................................23
Serial Interface Port Pin Description.......................................23
MSB/LSB Transfers....................................................................23
Register Map and Description......................................................24
Control Function Register Descriptions.................................27
Outline Dimensions.......................................................................32
Ordering Guide..........................................................................32
REVISION HISTORY
9/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to the Pin Configuration................................................11
Changes to the Pin Function Descriptions.................................12
Changes to Table 5..........................................................................24
Changes to CFR2<15:12> PLLREF Divider
Control Bits (÷N)............................................................................31
Changes to CFR2<11:8> PLLREF Divider
Control Bits (÷M)...........................................................................31
Changes to Ordering Guide..........................................................32
7/04—Revision: Initial Version
PRODUCT OVERVIEW
The AD9956 is Analog Devices’ newest AgileRF synthesizer.
The device is comprised of DDS and PLL circuitry. The DDS
features a 14-bit DAC operating at up to 400 MSPS and a 48-bit
frequency tuning word (FTW). The PLL circuitry includes a
phase frequency detector with scaleable 200 MHz inputs
(divider inputs operate up to 655 MHz) and digital control over
the charge pump current. The device also includes a 655 MHz
CML-mode PECL-compliant driver with programmable slew
rates. The AD9956 uses advanced DDS technology, an internal
high speed, high performance DAC, and an advanced phase
frequency detector/charge pump combination, which, when
used with an external VCO, enables the synthesis of digitally
programmable, frequency-agile analog output sinusoidal wave-
forms up to 2.7 GHz. The AD9956 is designed to provide fast
frequency hopping and fine tuning resolution (48-bit frequency
tuning word). Information is loaded into the AD9956 via a
serial I/O port that has a device write-speed of 25 Mb/s. The
AD9956 DDS block also supports a user-defined linear sweep
mode of operation.
The AD9956 is specified to operate over the extended
automotive range of −40°C to +125°C.
SPECIFICATIONS
AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ TA = 25°C) DAC_RSET = 3.92 kΩ, CP_RSET = 3.09 kΩ,
DRV_RSET = 4.02 kΩ, unless otherwise noted.
Table 1.

1 The input impedance of the REFCLK input is 1500 Ω. However, in order to provide matching on the clock line, an external 50 Ω load is used. Driving the PLLREF input buffer, the crystal oscillator section of this input stage performs up to only 30 MHz.
3 The charge pump output compliance range is functionally 0.2 V to (CP_VDD − 0.2 V). The value listed here is the compliance range for 5% matching.
4 Measured as peak-to-peak from DRV to DRV.
5 For a 4.02 kΩ resistor from DRV_RSET to GND.
6 Assumes a 1 mA load. I/O_UPDATE/PS<2:0> are detected by the AD9956 synchronous to the rising edge of SYNC_CLK. Each latency measurement is from the first SYNC_CLK rising edge
after the I/O_UPDATE/PS<2:0> state change.
LOOP MEASUREMENT CONDITIONS
622 MHz OC-12 Clock
VCO = Sirenza 190-640T
Reference = Wenzel 500-10116 (30.3 MHz)
Loop Filter = 10 kHz BW, 60° Phase Margin
C1 = 170 nF, R1 = 14.4 Ω, C2 = 5.11 µF, R2 = 89.3 Ω,
C3 Omitted
CP_OUT = 4 mA (Scaler = ×8)
÷R = 2, ÷M = 1, ÷N = 1
105 MHz Converter Clock
VCO = Sirenza 190-845T
Reference = Wenzel 500-10116 (30.3 MHz)
Loop Filter = 10 kHz BW, 45° Phase Margin
C1 = 117 nF, R1 = 28 Ω, C2 = 1.6 µF, R2 = 57.1 Ω, C3 = 53.4 nF
CP_OUT = 4 mA (Scaler = ×8)
÷R = 8, ÷M = 1, ÷N = 1
INPUTOUTPUT
04806-0-033
Figure 2. Generic Loop Filter
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-
trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 141516171819202324
I/OCS
DD_
I/O
NC_
OUT
LL_
LOCK/S
NC_
I/O_UPDATE
PS0PS1PS2
DGND4746454443424140393837
DRV
SET
AGNDPLLOSCPLLOSCPLLREFPLLREFAV
AGND
AGND
AVDD
AGND
AVDD
IOUT
IOUT
AVDD
AGND
I/O_RESET
RESET
DVDD
DGND
NC = NO CONNECT
CP_VDD
AGND
DRV
DRV
CP_VDD
AGND
REFCLK
REFCLK
AVDD
AGND
DVDD
CP_OUT36
AD9956
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
04806-0-008
Figure 3. 48-Lead LFCSP Pin Configuration
Note that the exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. For the device to
function properly, the paddle MUST be attached to analog ground.
Table 3. 48-Lead LFCSP Pin Function Description
Note that the exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. In order for the
device to function properly, the paddle MUST be attached to analog ground.
TYPICAL PERFORMANCE CHARACTERISTICS
CENTER 10.1MHz100kHz/SPAN 1MHz
REF LVL0dBm
DELTA 1 [T1]–84.82dB–404.80961924kHz
RBWVBWSWT
RF ATT
UNIT
500Hz500Hz20s
20dB
1 AP
–100
Figure 4. AD9956 DAC Performance: 400 MSPS Clock,
10 MHz FOUT, 1 MHz Span
CENTER 40.1MHz100kHz/SPAN 1MHz
REF LVL0dBm
DELTA 1 [T1]–78.67dB–100.20040080kHz
RBWVBWSWT
RF ATT
UNIT
500Hz500Hz20s
20dB
1 AP
–100
Figure 5. AD9956 DAC Performance: 400 MSPS Clock,
40 MHz FOUT, 1 MHz Span
CENTER 100.1MHz100kHz/SPAN 1MHz
REF LVL0dBm
DELTA 1 [T1]–57.74dB–400.80160321kHz
RBWVBWSWT
RF ATT
UNIT
500Hz500Hz20s
20dB
1 AP
–100
START 0Hz16.9MHz/STOP 169MHz
REF LVL0dBm
DELTA 1 [T1]–67.45dB74.50901804MHz
RBWVBWSWT
RF ATT
UNIT
10kHz10kHz4.3s
20dB
1 AP
–100
Figure 7. AD9956 DAC Performance: 400 MSPS Clock,
10 MHz FOUT, 200 MHz Span
START 0Hz20MHz/STOP 200MHz
REF LVL0dBm
DELTA 1 [T1]–62.65dB100.20040080MHz
RBWVBWSWT
RF ATT
UNIT
10kHz10kHz5s
20dB
1 AP
–100
Figure 8. AD9956 DAC Performance: 400 MSPS Clock,
40 MHz FOUT, 200 MHz Span
START 0Hz20MHz/STOP 200MHz
REF LVL0dBm
DELTA 1 [T1]–48.78dB–400.80160321kHz
RBWVBWSWT
RF ATT
UNIT
10kHz10kHz5s
20dB
1 AP
–100
CENTER 159.5MHz100kHz/SPAN 1MHz
REF LVL0dBm
DELTA 1 [T1]–78.13dB–100.20040080kHz
RBWVBWSWT
RF ATT
UNIT
500kHz500kHz20s
20dB
1 AP
–100
Figure 10. AD9956 DAC Performance: 400 MSPS Clock,
160 MHz FOUT, 1 MHz Span
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k1M
Figure 11. AD9956 DDS/DAC Residual Phase Noise
400 MHz Clock, 10 MHz Output
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k1M
Figure 12. AD9956 DDS/DAC Residual Phase Noise
400 MHz Clock, 40 MHz Output
START 0Hz20MHz/STOP 200MHz
REF LVL0dBm
DELTA 1 [T1]–56.33dB–80.96192385MHz
RBWVBWSWT
RF ATT
UNIT
10kHz10kHz5s
20dB
1 AP
–100
Figure 13. AD9956 DAC Performance: 400 MSPS Clock,
160 MHz FOUT, 200 MHz Span
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 14. AD9956 DDS/DAC Residual Phase Noise
400 MHz Clock, 103 MHz Output
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 15. AD9956 DDS/DAC Residual Phase Noise
400 MHz Clock, 159 MHz Output
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 16. RF Divider and CML Driver Residual
Phase Noise (840 MHz In, 105 MHz Out)
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 17. RF Divider and CML Driver Residual
Phase Noise (1240 MHz In, 155 MHz Out)
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k10M1M
Figure 18. RF Divider and CML Driver Residual
Phase Noise (1680 MHz In, 210 MHz Out)
FREQUENCY (Hz)
L(f) (dBc
–170101k10010k100k100M10M1M
Figure 19. RF Divider and CML Driver Residual
Phase Noise (2488 MHz In, 622 MHz Out)
FREQUENCY (Hz)
L(f) (dBc
–1701k10010k100k10M1M
Figure 20. Total System Phase Noise for 105 MHz Converter Clock
FREQUENCY (Hz)
L(f) (dBc
–1701k10010k100k10M1M
Figure 21. Total System Phase Noise for 622 MHz OC-12 Clock
TYPICAL APPLICATION CIRCUITS
Figure 22. Dual-Clock Configuration
Figure 23. Fractional-Divider Loop
8-LEVEL FSK
(FC = 100MHz)
25MHz
Figure 24. LO and Baseband Modulation Generation

Partno	Mfg	Dc	Qty	Available	Descript
AD9956YCPZ	ADI	N/a	50	avai	400 MSPS 14-Bit DAC 48-Bit FTW 1.8 V CMOS DDS Based AgileRF™ Synthesizer