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AD9954YSV
400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer
400 MSPS 14-Bit, 1.8 V CMOS
Direct Digital Synthesizer
Rev. 0
FEATURES
400 MSPS internal clock speed
Integrated 14-bit DAC
Programmable phase/amplitude dithering
32-bit tuning word
Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)
Excellent dynamic performance
>80 dB SFDR @ 160 MHz (±100 kHz offset) AOUT
Serial I/O control
Ultrahigh speed analog comparator
Automatic linear and nonlinear frequency sweeping
capability
4 frequency/phase offset profiles
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP/EP package
Integrated 1024 word × 32-bit RAM
Support for 5 V input levels on most digital inputs
PLL REFCLK multiplier (4× to 20×)
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Multichip synchronization
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Automotive radar
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
I/O UPDATE
DAC_RSET
IOUT
IOUT
OSK
PWRDWNCTL
COMP_OUT
COMP_IN
COMP_IN
REFCLK
REFCLK
CRYSTAL OUTI/O PORTPS<1:0>
SYNC_IN
SYNC_CLK
RESETFigure 1. 48-LeadTQFP/EP
TABLE OF CONTENTS General Description.........................................................................3
AD9954—Electrical Specifications................................................4
Absolute Maximum Ratings............................................................7
Pin Configurations...........................................................................8
Pin Function Descriptions..............................................................9
Typical Performance Characteristics...........................................10
Theory of Operation......................................................................13
Component Blocks.....................................................................13
Modes of Operation...................................................................22
Serial Port Operation.................................................................30
Instruction Byte..........................................................................32
Serial Interface Port Pin Description.......................................32
MSB/LSB Transfers....................................................................32
RAM I/O Via Serial Port...........................................................32
Suggested Application Circuits.....................................................35
Outline Dimensions.......................................................................36
ESD Caution................................................................................36
Ordering Guide..........................................................................36
REVISION HISTORY Revision 0: Initial Version
GENERAL DESCRIPTION The AD9954 is a direct digital synthesizer (DDS) featuring a
14-bit DAC operating up to 400 MSPS. The AD9954 uses
advanced DDS technology, coupled with an internal high speed,
high performance DAC to form a digitally programmable,
complete high frequency synthesizer capable of generating a
frequency-agile analog output sinusoidal waveform at up to
200 MHz. The AD9954 is designed to provide fast frequency
hopping and fine tuning resolution (32-bit frequency tuning
word). The frequency tuning and control words are loaded into
the AD9954 via a serial I/O port. The AD9954 includes an
integrated 1024 × 32 static RAM to support flexible frequency
sweep capability in several modes. The AD9954 also supports a
user defined linear sweep mode of operation. The device
includes an on-chip high speed comparator for applications
requiring a square wave output.
The AD9954 is specified to operate over the extended industrial
temperature range of –40°C to +105°C.
AD9954—ELECTRICAL SPECIFICATIONS
Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, RSET = 3.92 kΩ, External Reference Clock
Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.
1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise per-
formance of the device.
2 Represents the cycle-to-cycle residual jitter from the comparator alone. Represents the cycle-to-cycle residual jitter from the DDS core driving the comparator.
4 Wake-up time refers to the recovery from analog power-down modes (see section on Power-Down Modes of Operation). The longest time required is for the reference
clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DAC_BP and that the recommended PLL loop filter values are used. SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK fre-
quency is the same as the external reference clock frequency. SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.
7 This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3. Explanation of Test Levels IOUT
MUSTTERMINATE
OUTPUTSTOAVDDFOR
CURRENTFLOW.DO
NOTEXCEEDTHE
OUTPUTVOLTAGE
COMPLIANCERATING.
DACOUTPUTS
AVDD
COMPARATOR
OUTPUT
DVDD_I/O
INPUT
DIGITAL
INPUTS
AVOIDOVERDRIVING
DIGITALINPUTS.
FORWARDBIASING
ESDDIODESMAY
COUPLEDIGITALNOISE
ONTOPOWERPINS.
COMPINCOMPIN
COMPARATOR
INPUTS
Figure 2. Equivalent Input and Output Circuits
PIN CONFIGURATIONS
I/OUPDATE
DVDD
DGND
AVDD
AGND
AVDD
AGND
OSC/REFCLK
OSC/REFCLK
CRYSTALOUT
CLKMODESELECT
LOOP_FILTER
AGND
AGND
AGND
IOUT
IOUT
DACBP
AGND
OSKPS1PS0S
NC_
CLK
NC_
DD_
I/O
DGNDSDIOSYN
RESET
PWRDWNCTL
DVDD
DGND
AGND
COMP_IN
COMP_IN
AVDD
COMP_OUT
AVDD
AGND
AVDDDAC_
SET
Figure 3. 48-Lead EP_TQFP
Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to
analog ground. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or 3.3 V. The DVDD pins (Pin 2 and Pin 34) can only be
powered to 1.8 V. PIN FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions—48-Lead TQFP/EP
TYPICAL PERFORMANCE CHARACTERISTICS
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–70.68dBFigure 4. FOUT = 1 MHz FCLK = 400 MSPS, WBSFDR
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–69.12dBFigure 5. FOUT = 10 MHz, FCLK = 400 MSPS, WBSFDR
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–68.44dBFigure 6. FOUT = 40 MHz, FCLK = 400 MSPS, WBSFDR
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–61.55dBFigure 7. FOUT = 80 MHz FCLK = 400 MSPS, WBSFDR
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–56.2dBFigure 8 FOUT = 120 MHz, FCLK = 400 MSPS, WBSFDR
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–53.17dBFigure 9. FOUT = 160 MHz, FCLK = 400 MSPS, WBSFDR
CENTER 1.105MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
W1 S2
S3 FC
REF–4dBm
LOG
10dB/
ATTEN 10dB
–5.679dBmFigure 10. FOUT = 1.1 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
CENTER 10MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–93.01dBFigure 11. FOUT = 10 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
CENTER 39.9MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/Figure 12. FOUT = 39.9 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
CENTER 80.25MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
W1 S2
S3 FC
REF–4dBm
LOG
10dB/Figure 13. FOUT = 80.3 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
CENTER 120.2MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
W1 S2
S3 FC
REF–4dBm
LOG
10dB/Figure 14. FOUT = 120.2 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
CENTER 160.5MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
W1 S2
S3 FC
REF–4dBm
LOG
10dB/Figure 15. FOUT = 160 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
Figure 16. Residual Phase Noise with FOUT = 159.5 MHz. FCLK = 400 MSPS
(Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue)
Figure 17. Residual Phase Noise with FOUT = 9.5 MHz; FCLK = 400 MSPS (Green),
4 ×100 MSPS (Red), and 20 × 20 MSPS (Blue)
A CH1 708mVFigure 18. Comparator Rise and Fall Time at 160 MHz
A CH1 708mVFigure 19. Residual Peak-to-Peak Jitter of DDS
and Comparator Operating Together at 160 MHz
THEORY OF OPERATION
COMPONENT BLOCKS
DDS Core The output frequency (fO) of the DDS is a function of the fre-
quency of system clock (SYSCLK), the value of the frequency
tuning word (FTW), and the capacity of the accumulator (232, in
this case). The exact relationship is given below with fS defined
as the frequency of SYSCLK.
()()3132202/≤≤=FTWwithfFTWfSO 1–222/–323132<<×=FTWwithffSO
The value at the output of the phase accumulator is translated to
an amplitude value via the COS(x) functional block and routed
to the DAC.
In certain applications it is desirable to force the output signal to
zero phase. Simply setting the FTW to 0 does not accomplish
this; it only results in the DDS core holding its current phase
value. Thus, a control bit is required to force the phase accumu-
lator output to zero.
At power-up, the clear phase accumulator bit is set to Logic 1,
but the buffer memory for this bit is cleared (Logic 0). There-
fore, upon power-up, the phase accumulator will remain clear
until the first I/O UPDATE is issued.
Phase-Locked Loop (PLL) The PLL allows multiplication of the REFCLK frequency. Con-
trol of the PLL is accomplished by programming the 5-bit
REFCLK multiplier portion of Control Function Register No. 2,
Bits <7:3>.
When programmed for values ranging from 0x04 to 0x14
(4 decimal to 20 decimal), the PLL multiplies the REFCLK input
frequency by the corresponding decimal value. However, the
maximum output frequency of the PLL is restricted to
400 MHz. Whenever the PLL value is changed, the user should
be aware that time must be allocated to allow the PLL to lock
(approximately 1 ms).
The PLL is bypassed by programming a value outside the range
of 4 to 20 (decimal). When bypassed, the PLL is shut down to
conserve power.
Clock Input The AD9954 supports various clock methodologies. Support for
differential or single-ended input clocks, and enabling of an on-
chip oscillator, and/or a phase-locked loop (PLL) multiplier are
all controlled via user programmable bits. The AD9954 may be
configured in one of six operating modes to generate the system
clock. The modes are configured using the CLKMODESELECT
pin, CFR1<4> and CFR2<7:3>. Connecting the external pin
CLKMODESELECT to Logic High enables the on-chip crystal
oscillator circuit. With the on-chip oscillator enabled, users of
the AD9954 connect an external crystal to the REFCLK and
REFCLKB inputs to produce a low frequency reference clock in
the range of 20 MHz to 30 MHz. The signal generated by the
oscillator is buffered before it is delivered to the rest of the chip.
This buffered signal is available via the CRYSTAL OUT pin. Bit
CFR1<4> can be used to enable or disable the buffer, turning on
or off the system clock. The oscillator itself is not powered
down in order to avoid long startup times associated with turn-
ing on a crystal oscillator. Writing CFR2<9> to Logic High
enables the crystal oscillator output buffer. Logic Low at
CFR2<9> disables the oscillator output buffer.
Connecting CLKMODESELECT to Logic Low disables the on-
chip oscillator and the oscillator output buffer. With the oscilla-
tor disabled, an external oscillator must provide the REFCLK
and/or REFCLKB signals. For differential operation, these pins
are driven with complementary signals. For single-ended opera-
tion, a 0.1 µF capacitor should be connected between the
unused pin and the analog power supply. With the capacitor in
place, the clock input pin bias voltage is 1.35 V. In addition, the
PLL may be used to multiply the reference frequency by an
integer value in the range of 4 to 20. Table 5 summarizes the
clock modes of operation. Note the PLL multiplier is controlled
via the CFR2<7:3> bits, independent of the CFR1<4> bit.
Table 5.Clock Input Modes of Operation
DAC Output The AD9954 incorporates an integrated 14-bit current output
DAC. Unlike most DACs, this output is referenced to AVDD,
not AGND. Two complementary outputs provide a combined full-scale
output current (IOUT). Differential outputs reduce the amount of
common-mode noise that might be present at the DAC output,
offering the advantage of an increased signal-to-noise ratio. The
full-scale current is controlled by means of an external resistor
(RSET) connected between the DAC_RSET pin and the DAC
ground (AGND_DAC). The full-scale current is proportional to
the resistor value as follows
OUTSETIR/19.39=
The maximum full-scale output current of the combined DAC
outputs is 15 mA, but limiting the output to 10 mA provides the
best spurious-free dynamic range (SFDR) performance. The DAC
output compliance range is AVDD + 0.5 V to AVDD – 0.5 V. Volt-
ages developed beyond this range will cause excessive DAC distor-
tion and could potentially damage the DAC output circuitry.
Proper attention should be paid to the load termination to keep the
output voltage within this compliance range.
Comparator Many applications require a square wave signal rather than a
sine wave. For example, in most clocking applications a high
slew rate helps to reduce phase noise and jitter. To support these
applications, the AD9954 includes an on-chip comparator. The
comparator has a bandwidth greater than 200 MHz and a
common-mode input range of 1.3 V to 1.8 V. By setting the
comparator power-down bit, CFR1<6>, the comparator can be
turned off to save on power consumption.
Linear Sweep Block Linear sweep is a mode of operation whereby changes from a
start frequency (F0) to a terminal frequency (F1) are not instan-
taneous but instead are accomplished in a sweep or ramped
fashion. Frequency ramping, whether linear or nonlinear, neces-
sitates that many intermediate frequencies between F0 and F1
will be output in addition to the primary F0 and F1 frequencies.
The linear sweep block is comprised of the falling and rising
delta frequency tuning words, the falling and rising delta fre-
quency ramp rates, and the frequency accumulator. The linear
sweep enable bit CFR1 <21> enables the linear sweep block. In
addition, the linear sweep no dwell bit controls the linear sweep
block’s behavior upon reaching the terminal frequency in a
sweep. The actual method for programming a frequency sweep
is covered in the Modes of Operation section.
Serial IO Port The AD9954 serial port is a flexible, synchronous serial communi-
cations port that allows easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O port is com-
patible with most synchronous transfer formats, including both the
Motorola 6905/11 SPI and Intel 8051 SSR protocols.
The interface allows read/write access to all registers that configure
the AD9954. MSB first or LSB first transfer formats are supported.
In addition, the AD9954’s serial interface port can be configured as
a single pin I/O (SDIO), which allows a 2-wire interface or two
unidirectional pins for in/out (SDIO/SDO), which enables a 3-wire
interface. Two optional pins, IOSYNC and CS, enable greater flexi-
bility for system design in the AD9954.
Register Maps and Descriptions The register maps are listed in Table 7 and Table 8. The appro-
priate register map depends on the state of the linear sweep
enable bit because certain registers are remapped depending
on which mode the part is operating in. Specifically, Registers 0x07, 0x08, 0x09, and 0x0A act as the RAM segment control
words for each of the RAM profile slices when the linear sweep
enable bit is false. When the linear sweep enable bit is true, 0x07
becomes the negative linear sweep control word and 0x08
becomes the positive linear sweep control word. The 0x09 and
0x0A registers are not used in linear sweep mode. Because the
linear sweep operation takes precedence over RAM operations,
ADI recommends that the RAM enable bit CFR1<31> be set to
zero when the linear sweep enable bit CFR1<21> is true to
conserve power. The serial address numbers associated with
each of the registers are shown in hexadecimal format. Angle
brackets <> are used to reference specific bits or ranges of bits.
For example, <3> designates Bit 3, while <7:3> designates the
range of bits from 7 down to 3, inclusive.
Table 6. Register Mapping Based on Linear Sweep Enable Bit Table 7. Register Map—When Linear Sweep Enable Bit Is False (CFR1<21> = 0). Note that the RAM enable Bit CFR1<31> only activates the RAM itself not the RAM segment control words.
Table 8. Register Map–When Linear Sweep Enable Bit Is True (CFR1<21> = 1). Note that the RAM enable Bit CFR1<31> only activates the RAM itself not the RAM segment control words.
Control Register Bit Descriptions
Control Function Register No.1 (CFR1) The CFR1 is used to control the various functions, features,
and modes of the AD9954. The functionality of each bit is
detailed below.
CFR1<31>: RAM Enable Bit
CFR1<31> = 0 (default). When CFR1<31> is inactive, the RAM
is disabled for operation. Either single-tone mode of
operation or linear sweep mode of operation is enabled.
CFR1<31> = 1. If CFR1<31> is active, the RAM is
enabled for operation. Access control for normal operation is
controlled via the mode control bits of the RSCW for the cur-
rent profile.
CFR1<30>: RAM Destination Bit
CFR1<30> = 0 (default). If CFR1<31> is active, a Logic 0 on the
RAM destination bit (CFR1<30> = 0) configures the AD9954
such that the RAM output drives the phase accumulator (i.e.,
the frequency tuning word). If CFR1<31> is inactive,
CFR1<30> is a Don’t Care.
CFR1<30> = 1. If CFR1<31> is active, a Logic 1 on the RAM
destination bit (CFR1<30> = 1) configures the AD9954 such
that the RAM output drives the phase-offset adder (i.e., sets the
phase offset of the DDS core).
CFR1<29:27>: Internal Profile Control Bits
These bits cause the profile bits to be ignored when the RAM is
being used and puts the AD9954 into an automatic profile loop
sequence that allows the user to implement a frequency/phase
composite sweep that runs without external inputs. See the
Internal Profile Control section for more details.
CFR1<26>: Amplitude Ramp Rate Load Control Bit
CFR1<26> = 0 (default). The amplitude ramp rate timer is
loaded only upon timeout (timer == 1) and is not loaded due to
an I/O UPDATE input signal.
CFR1<25>: Shaped On-Off Keying Enable Bit
CFR1<25> = 0 (default) Shaped on-off keying is
bypassed.
CFR1<25> = 1. Shaped on-off keying is enabled. When enabled,
CFR1<24> controls the mode of operation for this function.
CFR1<24>: Auto Shaped On-Off Keying Enable Bit (Only Valid
When CFR1<25> Is Active High)
CFR1<24> = 0 (default). When CFR1<25> is active, a Logic 0
on CFR1<24> enables the manual shaped on-off keying opera-
tion. Each amplitude sample sent to the DAC is multiplied by
the amplitude scale factor. See the Shaped On-Off Keying sec-
tion for details.
CFR1<24> = 1. When CFR1<25> is active, a Logic 1 on
CFR1<24> enables the auto shaped on-off keying operation.
Toggling the OSK pin high will cause the output scalar to ramp
up from zero scale to the amplitude scale factor at a rate deter-
mined by the amplitude ramp rate. Toggling the OSK pin low
will cause the output to ramp down from the amplitude scale
factor to zero scale at the amplitude ramp rate. See the Shaped
On-Off Keying section for details.
CFR1<23>: Automatic Synchronization Enable Bit
CFR1<23> = 0 (default). The automatic synchronization feature
of multiple AD9954s is inactive.
CFR1<23> = 1. The automatic synchronization feature of mul-
tiple AD9954s is active. The device will synchronize its internal
synchronization clock (SYNC_CLK) to align to the signal pre-
sent on the sync-in input. See the Synchronizing Multiple
AD9954s section for details.
CFR1<22>: Software Manual Synchronization of Multiple
AD9954
CFR1<22> = 0 (default). The manual synchronization feature is
inactive.
