AD9953YSV ,400 MSPS 14-Bit DAC 1.8 V CMOS Direct Digital Synthesizer with 1024x32 RAMAPPLICATIONS Excellent dynamic performance Agile VHF/UHF LO frequency synthesis >80 dB SFDR @ 160 M ..
AD9954YSV ,400 MSPS 14-Bit, 1.8 V CMOS Direct Digital SynthesizerGENERAL DESCRIPTION the AD9954 via a serial I/O port. The AD9954 includes an The AD9954 is a dire ..
AD9956YCPZ ,400 MSPS 14-Bit DAC 48-Bit FTW 1.8 V CMOS DDS Based AgileRF™ SynthesizerGeneral Description ........ 18 Control Function Register Descriptions ...... 27 DDS Core.... 18 Ou ..
AD9958BCPZ ,2-Channel 500 MSPS DDS with 10-Bit DACsCharacteristics ....... 11 Instruction Byte Description ....... 30 Application Circuits ........ 14 ..
AD9961BCPZ , 10-/12-Bit, Low Power, Broadband MxFE
AD9963BCPZ , 10-/12-Bit, Low Power, Broadband MxFE
ADSP-2181BST-133 ,DSP Microcomputerapplications.and Data StorageIndependent ALU, Multiplier/Accumulator, and BarrelThe ADSP-2181 combi ..
ADSP-2181BST-133 ,DSP Microcomputeroverview of ADSP-2181• Receive and transmit data through the two serial portsfunctionality. For add ..
ADSP2181BST-133 ,DSP MicrocomputerGENERAL DESCRIPTION16K Words On-Chip Program Memory RAMThe ADSP-2181 is a single-chip microcomputer ..
ADSP-2181BSZ-133 , DSP Microcomputer
ADSP-2181KS-115 ,DSP Microcomputerfeatures:that the output of any unit may be the input of any unit on the• 33 MHz ADSP-2181next cycl ..
ADSP2181KS133 ,DSP Microcomputerfeatures:that the output of any unit may be the input of any unit on the• 33 MHz ADSP-2181next cycl ..
AD9953YSV
400 MSPS 14-Bit DAC 1.8 V CMOS Direct Digital Synthesizer with 1024x32 RAM
400 MSPS, 14-Bit, 1.8 V CMOS
Direct Digital Synthesizer
Rev. 0
FEATURES
400 MSPS internal clock speed
Integrated 14-bit DAC
32-bit tuning word
Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)
Excellent dynamic performance
>80 dB SFDR @ 160 MHz (±100 kHz offset) AOUT
Serial I/O control
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP/EP package
Support for 5 V input levels on most digital inputs
PLL REFCLK multiplier (4× to 20×)
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Multichip synchronization
APPLICATIONS
Agile VHF/UHF LO frequency synthesis
FM chirp source for radar and scanning systems
Nonlinear-shaped PSK/FSK modulator
Test and measurement equipment
FUNCTIONAL BLOCK DIAGRAM
I/O UPDATE
DAC_RSET
IOUT
IOUT
OSK
PWRDWNCTL
REFCLK
REFCLK
CRYSTAL OUTI/O PORTPS<1:0>
SYNC_IN
SYNC_CLK
RESETFigure 1.
TABLE OF CONTENTS General Description.........................................................................3
Electrical Specifications...................................................................4
Absolute Maximum Ratings............................................................6
Pin Configuration.............................................................................7
Pin Function Descriptions..............................................................8
Typical Performance Characteristics.............................................9
Theory of Operation......................................................................12
Component Blocks.....................................................................12
Modes of Operation...................................................................19
Programming AD9953 Features...............................................22
Serial Port Operation.................................................................25
Instruction Byte..........................................................................27
Serial Interface Port Pin Description.......................................27
MSB/LSB Transfers....................................................................27
Suggested Application Circuits.....................................................29
Outline Dimensions.......................................................................30
ESD Caution................................................................................30
Ordering Guide..........................................................................30
REVISION HISTORY Revision 0: Initial Version
GENERAL DESCRIPTION The AD9953 is a direct digital synthesizer (DDS) featuring a
14-bit DAC operating up to 400 MSPS. The AD9953 uses
advanced DDS technology, coupled with an internal high speed,
high performance DAC to form a digitally programmable,
complete high frequency synthesizer capable of generating a
frequency-agile analog output sinusoidal waveform at up to
200 MHz. The AD9953 includes an integrated 1024 × 32 static
RAM to support flexible frequency sweep capability in several
modes. The AD9953 is designed to provide fast frequency hop-
ping and fine tuning resolution (32-bit frequency tuning word).
The frequency tuning and control words are loaded into the
AD9953 via a serial I/O port.
The AD9953 is specified to operate over the extended industrial
temperature range of –40°C to +105°C.
ELECTRICAL SPECIFICATIONS
Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, RSET = 3.92 kΩ, External Reference Clock
Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND. 1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise
performance of the device.
2 Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions of the AD9953 section). The longest time required is for the
reference clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values
are used. SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency. SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.
5 This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
IOUT
MUSTTERMINATEOUTPUTS TO AVDD. DONOT EXCEED THEOUTPUT VOLTAGECOMPLIANCE RATING.
DACOUTPUTS
DVDD_I/O
INPUT
DIGITALINPUTS
AVOIDOVERDRIVINGDIGITAL INPUTS.FORWARD BIASINGESD DIODES MAYCOUPLE DIGITAL NOISEONTO POWER PINS.03374-0-032
Figure 2. Equivalent Input and Output Circuits
PIN CONFIGURATION
I/O UPDATE
DVDD
DGND
AVDD
AGND
AVDD
AGND
OSC/REFCLK
OSC/REFCLK
CRYSTAL OUT
CLKMODESELECT
LOOP_FILTER
AGND
AGND
AGND
IOUT
IOUT
DACBP
AGND
OSKPS1PS0S
NC_
CLK
NC_
DD_
I/O
DGNDSDIOSYN
RESET
PWRDWNCTL
DVDD
DGND
AGND
AGND
AGND
AVDD
AGND
AVDD
AGND
AVDDDAC_
SET
Figure 3. 48-Lead TQFP/EP
Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to
analog ground. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or 3.3 V; however, the DVDD pins (Pin 2 and Pin 34) can only
be powered to 1.8 V. PIN FUNCTION DESCRIPTIONS
Table 3. 48-Lead TQFP/EP TYPICAL PERFORMANCE CHARACTERISTICS
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–70.68dBFigure 4. FOUT = 1 MHz FCLK = 400 MSPS, WBSFDR
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–69.12dBFigure 5. FOUT = 10 MHz, FCLK = 400 MSPS, WBSFDR
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–68.44dBFigure 6. FOUT = 40 MHz, FCLK = 400 MSPS, WBSFDR
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–61.55dBFigure 7. FOUT = 80 MHz FCLK = 400 MSPS, WBSFDR
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–56.2dBFigure 8. FOUT = 120 MHz, FCLK = 400 MSPS, WBSFDR
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–53.17dBFigure 9. FOUT = 160 MHz, FCLK = 400 MSPS, WBSFDR
CENTER 1.105MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
W1 S2
S3 FC
REF–4dBm
LOG
10dB/
ATTEN 10dB
–5.679dBmFigure 10. FOUT = 1.1 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
CENTER 10MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/
ATTEN 10dB
–93.01dBFigure 11. FOUT = 10 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
CENTER 39.9MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
W1 S2
S3 FC
REF 0dBm
LOG
10dB/Figure 12. FOUT = 39.9 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
CENTER 80.25MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
W1 S2
S3 FC
REF–4dBm
LOG
10dB/Figure 13. FOUT = 80.3 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
CENTER 120.2MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
W1 S2
S3 FC
REF–4dBm
LOG
10dB/
ATTEN 10dB
–6.825dBmFigure 14. FOUT = 120.2 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
CENTER 160.5MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
W1 S2
S3 FC
REF–4dBm
LOG
10dB/Figure 15. FOUT = 160 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
Figure 16. Residual Phase Noise with FOUT = 159.5 MHz, FCLK = 400 MSPS
(Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue)
A CH1 708mVFigure 17. Residual Peak-to-Peak Jitter of DDS
and Comparator Operating Together at 160 MHz
Figure 18. Residual Phase Noise with FOUT = 9.5 MHz, FCLK = 400 MSPS (Green),
4 ×100 MSPS (Red), and 20 × 20 MSPS (Blue)
A CH1 708mVFigure 19. Comparator Rise and Fall Time at 160 MHz
THEORY OF OPERATION
COMPONENT BLOCKS
DDS Core The output frequency (fO) of the DDS is a function of the
frequency of the system clock (SYSCLK), the value of the
frequency tuning word (FTW), and the capacity of the accumu-
lator (232, in this case). The exact relationship is given below
with fS defined as the frequency of SYSCLK.
()()3132202/≤≤=FTWwithfFTWfSO ()1–222/–1323132<<×=FTWwithFTWffSO
The value at the output of the phase accumulator is translated to
an amplitude value via the COS(x) functional block and routed
to the DAC.
In certain applications, it is desirable to force the output signal
to zero phase. Simply setting the FTW to 0 does not accomplish
this; it only results in the DDS core holding its current phase
value. Thus, a control bit is required to force the phase accumu-
lator output to zero.
At power-up, the clear phase accumulator bit is set to Logic 1,
but the buffer memory for this bit is cleared (Logic 0). There-
fore, upon power-up, the phase accumulator will remain clear
until the first I/O UPDATE is issued.
Phase-Locked Loop (PLL) The PLL allows multiplication of the REFCLK frequency. Con-
trol of the PLL is accomplished by programming the 5-bit
REFCLK multiplier portion of Control Function Register No. 2,
Bits <7:3>.
When programmed for values ranging from 0x04 to 0x14
(4 decimal to 20 decimal), the PLL multiplies the REFCLK input
frequency by the corresponding decimal value. However, the
maximum output frequency of the PLL is restricted to
400 MHz. Whenever the PLL value is changed, the user should
be aware that time must be allocated to allow the PLL to lock
(approximately 1 ms).
The PLL is bypassed by programming a value outside the range
of 4 to 20 (decimal). When bypassed, the PLL is shut down to
conserve power.
Clock Input The AD9953 supports various clock methodologies. Support for
differential or single-ended input clocks and enabling of an
on-chip oscillator and/or a phase-locked loop (PLL) multiplier
is all controlled via user programmable bits. The AD9953 may
be configured in one of six operating modes to generate the
system clock. The modes are configured using the CLKMODE-
SELECT pin, CFR1<4>, and CFR2<7:3>. Connecting the exter-
nal pin CLKMODESELECT to Logic High enables the on-chip
crystal oscillator circuit. With the on-chip oscillator enabled,
users of the AD9953 connect an external crystal to the REFCLK
and REFCLKB inputs to produce a low frequency reference
clock in the range of 20 MHz to 30 MHz. The signal generated
by the oscillator is buffered before it is delivered to the rest of
the chip. This buffered signal is available via the CRYSTAL
OUT pin. Bit CFR1<4> can be used to enable or disable the
buffer, turning on or off the system clock. The oscillator itself is
not powered down in order to avoid long start-up times associ-
ated with turning on a crystal oscillator. Writing CFR2<9> to
Logic High enables the crystal oscillator output buffer. Logic
Low at CFR2<9> disables the oscillator output buffer.
Connecting CLKMODESELECT to Logic Low disables the
on-chip oscillator and the oscillator output buffer. With the
oscillator disabled, an external oscillator must provide the
REFCLK and/or REFCLKB signals. For differential operation,
these pins are driven with complementary signals. For single-
ended operation, a 0.1 µF capacitor should be connected
between the unused pin and the analog power supply. With the
capacitor in place, the clock input pin bias voltage is 1.35 V. In
addition, the PLL may be used to multiply the reference
frequency by an integer value in the range of 4 to 20. Table 4
summarizes the clock modes of operation. Note that the PLL
multiplier is controlled via the CFR2<7:3> bits, independent of
the CFR1<4> bit.
Table 4. Clock Input Modes of Operation
DAC Output The AD9953 incorporates an integrated 14-bit current output
DAC. Unlike most DACs, this output is referenced to AVDD,
not AGND. Two complementary outputs provide a combined full-scale
output current (IOUT). Differential outputs reduce the amount of
common-mode noise that might be present at the DAC output,
offering the advantage of an increased signal-to-noise ratio. The
full-scale current is controlled by an external resistor (RSET)
connected between the DAC_RSET pin and the DAC ground
(AGND_DAC). The full-scale current is proportional to the
resistor value as follows:
OUTSETIR/19.39=
The maximum full-scale output current of the combined DAC
outputs is 15 mA, but limiting the output to 10 mA provides the
best spurious-free dynamic range (SFDR) performance. The DAC
output compliance range is AVDD + 0.5 V to AVDD – 0.5 V.
Voltages developed beyond this range will cause excessive DAC
distortion and could potentially damage the DAC output circuitry.
Proper attention should be paid to the load termination to keep the
output voltage within this compliance range.
Serial IO Port The AD9953 serial port is a flexible, synchronous serial communi-
cations port that allows easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O port is com-
patible with most synchronous transfer formats, including both the
Motorola 6905/11 SPI® and Intel® 8051 SSR protocols.
The interface allows read/write access to all registers that configure
the AD9953. MSB first or LSB first transfer formats are supported.
The AD9953’s serial interface port can be configured as a single pin
I/O (SDIO), which allows a 2-wire interface or two unidirectional
pins for in/out (SDIO/SDO), which in turn enables a 3-wire inter-
face. Two optional pins, IOSYNC and CS, enable greater flexibility
for system design in the AD9953.
Register Map and Descriptions The register map is listed in Table 5.
Table 5. Register Map Control Register Bit Descriptions
Control Function Register. No. 1 (CFR1) The CFR1 is used to control the various functions, features, and
modes of the AD9953. The functionality of each bit is below.
CFR1<31>: RAM Enable Bit
CFR1<31> = 0 (default). The RAM is powered down to con-
serve power. Single-tone mode of operation is active.
CFR1<31> = 1. If CFR1<31> is active, the RAM is enabled for
operation. Access control for normal operation is controlled via
the mode control bits of the RSCW for the current profile.
CFR1<30>: RAM Destination Bit
CFR1<30> = 0 (default). If CFR1<31> is active, a Logic 0 on the
RAM destination bit (CFR1<30> = 0) configures the AD9953
such that the RAM output drives the phase accumulator (i.e.,
the frequency tuning word). If CFR1<31> is inactive,
CFR1<30> is a Don’t Care.
CFR1<30> = 1. If CFR1<31> is active, a Logic 1 on the RAM
destination bit (CFR1<30> = 1) configures the AD9953 such
that the RAM output drives the phase-offset adder (i.e., sets the
phase offset of the DDS core).
CFR1<29:27>: Not Used
CFR1<26>: Amplitude Ramp Rate Load Control Bit
CFR1<26> = 0 (default). The amplitude ramp rate timer is
loaded only upon timeout (timer == 1) and is not loaded due to
an I/O UPDATE input signal.
CFR1<26> = 1. The amplitude ramp rate timer is loaded upon
timeout (timer == 1) or at the time of an I/O UPDATE input signal.
CFR1<25>: Shaped On-Off Keying Enable Bit
CFR1<25> = 0 (default). Shaped on-off keying is bypassed.
CFR1<25> = 1. Shaped on-off keying is enabled. When enabled,
CFR1<24> controls the mode of operation for this function.
CFR1<24>: Auto Shaped On-Off Keying Enable Bit (Only Valid
when CFR1<25> Is Active High)
CFR1<24> = 0 (default). When CFR1<25> is active, a Logic 0
on CFR1<24> enables the manual shaped on-off keying opera-
tion. Each amplitude sample sent to the DAC is multiplied by
the amplitude scale factor. See the Shaped On-Off Keying sec-
tion for details.
CFR1<24> = 1. When CFR1<25> is active, a Logic 1 on
CFR1<24> enables the auto shaped on-off keying operation.
Toggling the OSK pin high will cause the output scalar to ramp
will cause the output to ramp down from the amplitude scale
factor to zero scale at the amplitude ramp rate. See the Shaped
On-Off Keying section for details.
CFR1<23>: Automatic Synchronization Enable Bit
CFR1<23> = 0 (default). The automatic synchronization feature
of multiple AD9953s is inactive.
CFR1<23> = 1. The automatic synchronization feature of mul-
tiple AD9953s is active. The device will synchronize its internal
synchronization clock (SYNC_CLK) to align to the signal pre-
sent on the SYNC_IN input. See the Synchronizing Multiple
AD9953s section for details.
CFR1<22>: Software Manual Synchronization of Multiple
AD9953s
CFR1<22> = 0 (default). The manual synchronization feature is
inactive.
CFR1<22> = 1. The software controlled manual synchroniza-
tion feature is executed. The SYNC_CLK rising edge is
advanced by one SYNC_CLK cycle and this bit is cleared. To
advance the rising edge multiple times, this bit needs to be set
for each advance. See the Synchronizing Multiple AD9953s sec-
tion for details.
CFR1<21:14>: Not Used
CFR1<13>: Auto-Clear Phase Accumulator Bit
CFR1<13> = 0 (default). The current state of the phase accumula-
tor remains unchanged when the frequency tuning word is applied.
CFR1<13> = 1. This bit automatically synchronously clears
(loads 0s into) the phase accumulator for one cycle upon recep-
tion of an I/O UPDATE signal.
CFR1<12>: Sine/Cosine Select Bit
CFR1<12> = 0 (default). The angle-to-amplitude conversion
logic employs a COSINE function.
CFR1<12> = 1. The angle-to-amplitude conversion logic
employs a SINE function.
CFR1<11>: Not Used
CFR1<10>: Clear Phase Accumulator
CFR1<10> = 0 (default). The phase accumulator functions as
normal.
CFR1<10> = 1. The phase accumulator memory elements are
cleared and held clear until this bit is cleared.
