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AD9949AKCPZ
12-Bit CCD Signal Processor with Precision Timing™ Core
12-Bit CCD Signal Processor with
Precision Timing Core
Rev. A
FEATURES
New AD9949A supports CCD line length >4096 pixels
Correlated double sampler (CDS)
0 dB to 18 dB pixel gain amplifier (PxGA®)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
12-bit, 36 MSPS analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing driver
Precision Timing™ core with < 600 ps resolution
On-chip 3 V horizontal and RG drivers
40-lead LFCSP package
APPLICATIONS
Digital still cameras
High speed digital imaging applications
GENERAL DESCRIPTION The AD9949 is a highly integrated CCD signal processor for
digital still camera applications. Specified at pixel rates of up to
36 MHz, the AD9949 consists of a complete analog front end
with A/D conversion, combined with a programmable timing
driver. The Precision Timing core allows adjustment of high
speed clocks with < 600 ps resolution.
The analog front end includes black level clamping, CDS, PxGA,
VGA, and a 36 MSPS, 12-bit ADC. The timing driver provides
the high speed CCD clock drivers for RG and H1 to H4. Opera-
tion is programmed using a 3-wire serial interface.
Packaged in a space-saving, 40-lead LFCSP package, the
AD9949 is specified over an operating temperature range of
−20°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
DOUTCCDIN
REFTREFB
SDATASCKSL
HBLK
H1 TO H4VD
CLI
CLP/PBLKFigure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
General Specifications.................................................................3
Digital Specifications...................................................................3
Analog Specifications...................................................................4
Timing Specifications..................................................................5
Absolute Maximum Ratings............................................................6
Thermal Characteristics..............................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Descriptions.............................7
Terminology......................................................................................8
Equivalent Input/Output Circuits..................................................9
Typical Performance Characteristics...........................................10
System Overview............................................................................11
Serial Interface Timing..................................................................12
Complete Register Listing.........................................................13
Precision Timing High Speed Timing Generation......................18
Timing Resolution......................................................................18
High Speed Clock Programmability........................................18
H-Driver and RG Outputs........................................................19
Digital Data Outputs..................................................................19
Horizontal Clamping and Blanking.............................................21
Individual CLPOB and PBLK Sequences................................21
Individual HBLK Sequences.....................................................21
Generating Special HBLK Patterns..............................................23
Horizontal Sequence Control...................................................23
External HBLK Signal................................................................23
H-Counter Synchronization.....................................................24
Power-Up Procedure......................................................................25
Recommended Power-Up Sequence.......................................25
Analog Front End Description and Operation...........................26
DC Restore..................................................................................26
Correlated Double Sampler......................................................26
PxGA............................................................................................26
Variable Gain Amplifier............................................................29
ADC.............................................................................................29
Optical Black Clamp..................................................................29
Digital Data Outputs..................................................................30
Applications Information..............................................................31
Circuit Configuration................................................................31
Grounding and Decoupling Recommendations....................31
Driving the CLI Input................................................................32
Horizontal Timing Sequence Example....................................32
Outline Dimensions.......................................................................35
Ordering Guide..........................................................................35
REVISION HISTORY
9/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Features..........................................................................1
Changes to Analog Specifications..................................................4
Changes to Terminology Section...................................................9
Added H-Counter Behavior Section............................................12
Changes to Table 7..........................................................................14
Changes to Table 12........................................................................17
Changes to Table 15........................................................................17
Changes to H-Counter Sync Section...........................................24
Changes to Recommended Power-Up Sequence Section.........25
Changes to Ordering Guide..........................................................35
5/03—Revision 0: Initial Version
SPECIFICATIONS
GENERAL SPECIFICATIONS
Table 1. 1 The total power dissipated by the HVDD supply may be approximated using the equation UsedOutputsHofHVDDFrequencyPixelHVDDPowerHVDDTotal××=
Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply, reduces the power dissipation.
DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = DVDD= DRVDD = HVDD = RGVDD = 2.7 V, CL = 20 pF, unless otherwise noted.
Table 2.
ANALOG SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 36 MHz, typical timing specifications, unless otherwise noted.
Table 3. Input signal characteristics defined as follows:
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
INPUT SIGNAL RANGE03751-002
TIMING SPECIFICATIONS CL = 20 pF, fCLI = 36 MHz, unless otherwise noted.
Table 4. Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
ABSOLUTE MAXIMUM RATINGS
Table 5. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device
reliability.
THERMAL CHARACTERISTICS
Thermal Resistance 40-Lead LFCSP Package: θJA = 27°C/W1.
θJA is measured using a 4-layer PCB with the exposed paddle soldered to the
board.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-
trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9949
TOP VIEWD1D7D5
DRVDDDRVSSD32
VSSH3
VSSH1
(MS
) D1121314151617181920
30REFBRGVDD
TCVSSTCVDD
CLIAVDD
CCDINAVSS
REFT29393837363534333231D0
(LS
P/PB
HBLKDV
VSSVDSC
PIN 1INDICATOR
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions TERMINOLOGY
Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes, respectively, must
be present over all operating conditions.
Integral Nonlinearity (INL) The deviation of each individual code measured from a true
straight line from zero to full scale. The point used as zero scale
occurs 0.5 LSB before the first code transition. Positive full scale
is defined as a level 1 LSB and 0.5 LSB beyond the last code
transition. The deviation is measured from the middle of each
particular output code to the true straight line.
Peak Nonlinearity Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9949 from a straight line.
The point used as zero scale occurs 0.5 LSB before the first code
transition. Positive full scale is defined as a level 1 LSB and 0.5
LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the straight
line reference. The error is then expressed as a percentage of the
2 V ADC full-scale signal. The input signal is appropriately
gained up to fill the ADC’s full-scale range.
Total Output Noise The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be con-
verted to an equivalent voltage, using the relationship
1 LSB = (ADC full scale/2n codes)
where n is the bit resolution of the ADC. For the AD9949, 1 LSB
is approximately 0.488 mV.
Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
EQUIVALENT INPUT/OUTPUT CIRCUITS
AVDD
AVSSAVSS03751-004
Figure 3. CCDIN (Pin 27)
AVDD
AVSSCLIFigure 4. CLI (Pin 25)
DVSSDRVDD
DVSSDRVSS
DATA
THREE-STATEDOUT03751-006
Figure 5. Data Outputs D0 to D11 (Pins 1 to 4, 7 to 13, 40)
DVDD
DVSS
Figure 6. Digital Inputs (Pins 31 to 35, 38)
HVDD OR RGVDD
HVSS OR RGVSSDOUT
Figure 7. H1 to H4 and RG (Pins 14 to 15, 18 to 19, 21)
TYPICAL PERFORMANCE CHARACTERISTICS 03751-009
ADC OUTPUT CODE
DNL (LS
–1.0Figure 8. Typical DNL
03751-010
VGA GAIN CODE (LSB)
TPU
ISE (Figure 9. Output Noise vs. VGA Gain
03751-011
SAMPLE RATE (MHz)182430
POW
ISSIPA
TION
150Figure 10. Power Curves
SYSTEM OVERVIEW
SERIAL
INTERFACEFigure 11. Typical Application
Figure 11 shows the typical system application diagram for the
AD9949. The CCD output is processed by the AD9949’s AFE
circuitry, which consists of a CDS, a PxGA, a VGA, a black level
clamp, and an ADC. The digitized pixel information is sent to
the digital image processor chip, where all postprocessing and
compression occurs. To operate the CCD, CCD timing
parameters are programmed into the AD9949 from the image
processor through the 3-wire serial interface. From the system
master clock, CLI, provided by the image processor, the AD9949
generates the high speed CCD clocks and all internal AFE
clocks. All AD9949 clocks are synchronized with VD and HD.
The AD9949’s horizontal pulses (CLPOB, PBLK, and HBLK) are
programmed and generated internally.
The H-drivers for H1 to H4 and RG are included in the
AD9949, allowing these clocks to be directly connected to the
CCD. The H-drive voltage of 3 V is supported in the AD9949.
Figure 12 shows the horizontal and vertical counter dimensions
for the AD9949. All internal horizontal clocking is programmed
using these dimensions to specify line and pixel locations.
H-Counter Behavior When the maximum horizontal count of 4096 pixels is
exceeded, the H-counter in the AD9949 rolls over to zero and
continues counting. It is, therefore, recommended that the
maximum counter value not be exceeded.
However, the newer AD9949A version behaves differently. In
the AD9949A, the internal H-counter holds at its maximum
count of 4095 instead of rolling over. This feature allows the
AD9949A to be used in applications containing a line length
greater than 4096 pixels. Although no programmable values for
the horizontal blanking or clamping are available beyond pixel
4095, the H, RG, and AFE clocking continues to operate,
sampling the remaining pixels on the line.
03751-013
Figure 12. Vertical and Horizontal Counters
CLIFigure 13. Maximum VD/HD Dimensions
SERIAL INTERFACE TIMING The AD9949’s internal registers are accessed through a 3-wire
serial interface. Each register consists of an 8-bit address and a
24-bit data-word. Both the 8-bit address and 24-bit data-word
are written starting with the LSB. To write to each register, a
32-bit operation is required, as shown in Figure 14. Although
many registers are less than 24 bits wide, all 24 bits must be
written for each register. If the register is only 16 bits wide, then
the upper eight bits may be filled with zeros during the serial
write operation. If fewer than 24 bits are written, the register
will not be updated with new data.
Figure 15 shows a more efficient way to write to the registers by
using the AD9949’s address auto-increment capability. Using
this method, the lowest desired address is written first, followed
by multiple 24-bit data-words. Each new 24-bit data-word is
written automatically to the next highest register address. By
eliminating the need to write each 8-bit address, faster register
loading is achieved. Address auto-increment may be used start-
ing with any register location and may be used to write to as few
as two registers or as many as the entire register space.
SCK
NOTES
1. INDIVIDUAL SDATA BITS ARE LATCHED ON SCK RISING EDGES.
2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA.3. IF THE REGISTER LENGTH IS <24 BITS, THEN DON’T CARE BITS MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH.
4. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
8-BIT ADDRESS24-BIT DATAtLS
tDStDH
tLH
Figure 14. Serial Write Operation
SDATA
SCK
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE....
...DATA FOR NEXT
REGISTER ADDRESS
...03751-016
Figure 15. Continuous Serial Write Operation
COMPLETE REGISTER LISTING 1. All addresses and default values are expressed in
hexadecimal.
2. All registers are VD/HD updated as shown in Figure 14,
except for the registers indicated in Table 7, which are SL
updated.
Table 7. SL-Updated Registers Table 8. AFE Register Map
Table 9. Miscellaneous Register Map Table 10. CLPOB Register Map
Table 11. PBLK Register Map Table 12. HBLK Register Map
Table 13. H1 to H2, RG, SHP, SHD Register Map Table 14. AFE Operation Register Detail
Table 15. AFE Control Register Detail PRECISION TIMING HIGH SPEED TIMING GENERATION The AD9949 generates flexible high speed timing signals using
the Precision Timing core. This core is the foundation for gener-
ating the timing used for both the CCD and the AFE; the reset
gate (RG), horizontal drivers (H1 to H4), and the SHP/SHD
sample clocks. A unique architecture makes it routine for the
system designer to optimize image quality by providing precise
control over the horizontal CCD readout and the AFE
correlated double sampling.
TIMING RESOLUTION The Precision Timing core uses a 1× master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 16 illustrates how the internal timing
core divides the master clock period into 48 steps or edge posi-
tions. Therefore, the edge resolution of the Precision Timing core
is (tCLI/48). For more information on using the CLI input, refer
to the Applications Information section.
HIGH SPEED CLOCK PROGRAMMABILITY Figure 17 shows how the high speed clocks, RG, H1 to H4, SHP,
and SHD, are generated. The RG pulse has programmable rising
and falling edges and may be inverted using the polarity control.
The horizontal clocks H1 and H3 have programmable rising
and falling edges, and polarity control. The H2 and H4 clocks
are always inverses of H1 and H3, respectively. Table 16 summa-
rizes the high speed timing registers and their parameters.
Each edge location setting is 6 bits wide, but only 48 valid edge
locations are available. Therefore, the register values are mapped
into four quadrants, with each quadrant containing 12 edge
locations. Table 17 shows the correct register values for the
corresponding edge locations.
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6 ns TYP).
P[0]P[48] = P[0]P[12]P[24]P[36]
1 PIXEL
PERIOD
CLI
POSITION03751-017
Figure 16. High Speed Clock Resolution from CLI Master Clock Input
H1/H3
H2/H4
PROGRAMMABLE CLOCK POSITIONS:
1. RG RISING EDGE.
2. RG FALLING EDGE.
3. SHP SAMPLE LOCATION.
4. SHD SAMPLE LOCATION.
5. H1/H3 RISING EDGE POSITION6. H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3).03751-018
Figure 17. High Speed Clock Programmable Locations
