AD9948KCP-AD9948KCPRL Fast Delivery |IC PHOENIX CO.,LIMITED

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AD9948KCP-AD9948KCPRL
10-Bit CCD Signal Processor with Precision Timing⑩ Core
REV.0
10-Bit CCD Signal Processor with
Precision Timing™ Core
FUNCTIONAL BLOCK DIAGRAM
DOUTCCDIN
REFTREFB
SDATASCKSL
HBLK
H1–H4
HD VD
CLI
CLP/PBLK
FEATURES
Correlated Double Sampler (CDS)
0 dB to 18 dB Pixel Gain Amplifier (PxGA®)
6 dB to 42 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 25 MSPS A/D Converter
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Driver
Precision Timing Core with 800 ps Resolution
On-Chip 3 V Horizontal and RG Drivers
40-Lead LFCSP Package
APPLICATIONS
Digital Still Cameras
High Speed Digital Imaging Applications
GENERAL DESCRIPTION
The AD9948 is a highly integrated CCD signal processor for
digital still camera applications. Specified at pixel rates of up to
25 MHz, the AD9948 consists of a complete analog front end
with A/D conversion, combined with a programmable timing
driver. The Precision Timing core allows adjustment of high
speed clocks with 800 ps resolution.
The analog front end includes black level clamping, CDS, PxGA,
VGA, and a 25 MHz 10-bit A/D converter. The timing driver
provides the high speed CCD clock drivers for RG and H1–H4.
Operation is programmed using a 3-wire serial interface.
Packaged in a space-saving 40-lead LFCSP package, the
AD9948 is specified over an operating temperature range of
–20°C to +85°C.
AD9948–SPECIFICATIONS
DIGITAL SPECIFICATIONS
Specifications subject to change without notice.
GENERAL SPECIFICATIONS
*The total power dissipated by the HVDD supply may be approximated using the equation
Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation.
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = DRVDD = HVDD = RGVDD = 2.7 V, CL = 20 pF, unless otherwise noted.)
AD9948
ANALOG SPECIFICATIONS
*Input signal characteristics defined as follows:
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 25 MHz, Typical Timing Specifications,
unless otherwise noted.)
AD9948
TIMING SPECIFICATIONS
*Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
(CL = 20 pF, fCLI = 25 MHz, Serial Timing in Figure 3, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ORDERING GUIDE
Model
AD9948KCP
AD9948KCPRL
AD9948KCPZ*
AD9948KCPZRL*
*This is a lead free product.
THERMAL CHARACTERISTICS
Thermal Resistance
40-Lead LFCSP Package
�JA = 27°C/W*
*�JA is measured using a 4-layer PCB with the exposed paddle
soldered to the board.
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
TOP VIEW
AD9948
PIN 1
IDENTIFIER
30 REFB
29 REFT
28 AVSS
27 CCDIN
26 AVDD
25 CLI
24 TCVDD
23 TCVSS
22 RGVDD
21 RG
NC 1
(LSB) D0 2
D1 3
D2 4
DRVSS 5
DRVDD 6
D3 7
D4 8
D5 9
D6 10
40 NC39 CLP/PBLK38 HBLK37 DVDD36 DVSS35 HD34 VD33 SCK32 SDI31 SL
D7 11D8 12
(MSB) D9 13
H1 14H2 15
HVSS 1
HVDD 17
H3 18H4 19
RGVSS 20
AD9948
EQUIVALENT CIRCUITS
Circuit 1. CCDIN (Pin 27)
Circuit 2. CLI (Pin 25)
DVSSDRVDD
DVSSDRVSS
DATA
THREE-
STATEDOUT
Circuit 3. Data Outputs D0–D9 (Pins 2–4, 7–13)
Circuit 4. Digital Inputs (Pins 31–35, 38)
HVDD or RGVDD
HVSS or RGVSS
DATA
ENABLEOUTPUT
Circuit 5. H1–H4 and RG (Pins 14, 15, 18, 19, 21)
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed to
10-bit resolution indicates that all 1024codes, respectively,
must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9948 from a true straight
line. The point used as zero scale occurs 0.5 LSB before the
first code transition. Positive full scale is defined as a level 1 LSB
and 0.5LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of
the 2V ADC full-scale signal. The input signal is always appro-
priately gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated in
LSB, and represents the rms noise level of the total signal chain
at the specified gain setting. The output noise can be converted
to an equivalent voltage, using the relationship
where n is the bit resolution of the ADC. For the AD9948,
1LSB is approximately 1.95mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
ADC OUTPUT CODE
DNL (LSB)
TPC 1. Typical DNL
VGA GAIN CODE (LSB)1000400
OUTPUT NOISE (LSB)
7.5
TPC 2. Output Noise vs. VGA Gain
TPC 3. Power Curves
AD9948
SYSTEM OVERVIEW
Figure 1.Typical Application
Figure 1 shows the typical system application diagram for the
AD9948. The CCD output is processed by the AD9948’s AFE
circuitry, which consists of a CDS, a PxGA, a VGA, a black level
clamp, and an A/D converter. The digitized pixel information is
sent to the digital image processor chip, where all postprocessing
and compression occurs. To operate the CCD, CCD timing
parameters are programmed into the AD9948 from the image
processor through the 3-wire serial interface. From the system
master clock, CLI, provided by the image processor, the AD9948
generates the high speed CCD clocks and all internal AFE clocks.
All AD9948 clocks are synchronized with VD and HD. All of
the AD9948’s horizontal pulses (CLPOB, PBLK, and HBLK)
are programmed and generated internally.
The H-drivers for H1–H4 and RG are included in the AD9948,
allowing these clocks to be connected directly to the CCD.
H-drive voltage of 3 V is supported in the AD9948.
Figure 2a shows the horizontal and vertical counter dimensions
for the AD9948. All internal horizontal clocking is programmed
using these dimensions to specify line and pixel locations.
Figure 2a.Vertical and Horizontal Counters
Figure 2b. Maximum VD/HD Dimensions
SERIAL INTERFACE TIMING
All of the internal registers of the AD9948 are accessed through
a 3-wire serial interface. Each register consists of an 8-bit address
and a 24-bit data-word. Both the 8-bit address and 24-bit data-
word are written starting with the LSB. To write to each register,
a 32-bit operation is required, as shown in Figure3a. Although
many registers are less than 24 bits wide, all 24 bits must be
written for each register. If the register is only 16 bits wide, then
the upper eight bits are don’t cares and may be filled with zeros
during the serial write operation. If fewer than 24 bits are written,
the register will not be updated with new data.
Figure3b shows a more efficient way to write to the registers by
using the AD9948’s address auto-increment capability. Using
this method, the lowest desired address is written first, followed
by multiple 24-bit data-words. Each new 24-bit data-word will
be written automatically to the next highest register address. By
eliminating the need to write each 8-bit address, faster register
loading is achieved. Address auto-increment may be used start-
ing with any register location, and may be used to write to as
few as two registers or as many as the entire register space.
COMPLETE REGISTER LISTING
All addresses and default values are expressed in hexadecimal.
All registers are VD/HD updated as shown in Figure 3a, except
for the registers indicated in Table I, which are SL updated.
Table I.SL-Updated Registers
Figure 3a.Serial Write Operation
AD9948
Table II.AFE Register Map
Table III.Miscellaneous Register Map
Table IV.CLPOB Register Map
Table V.PBLK Register Map
AD9948
Table VI.HBLK Register Map
Table VII.H1–H2, RG, SHP, SHD Register Map
Table VIII.AFE Operation Register Detail
Table IX.AFE Control Register Detail
AD9948
PRECISION TIMING HIGH SPEED TIMING GENERATION
The AD9948 generates flexible high speed timing signals using
the Precision Timing core. This core is the foundation for gener-
ating the timing used for both the CCD and the AFE; the reset
gate RG, horizontal drivers H1–H4, and the SHP/SHD sample
clocks. A unique architecture makes it routine for the system
designer to optimize image quality by providing precise control
over the horizontal CCD readout and the AFE correlated
double sampling.
Timing Resolution
The Precision Timing core uses a 1× master clock input (CLI)
as a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 4 illustrates how the internal timing core
divides the master clock period into 48 steps or edge positions.
Therefore, the edge resolution of the Precision Timing core is
(tCLI/48). For more information on using the CLI input, refer to
the Applications Information section.
High Speed Clock Programmability
Figure 5 shows how the high speed clocks, RG, H1–H4, SHP,
and SHD, are generated. The RG pulse has programmable rising
and falling edges, and may be inverted using the polarity control.
The horizontal clocks H1 and H3 have programmable rising and
falling edges, and polarity control. The H2 and H4 clocks are
always inverses of H1 and H3, respectively. Table X summarizes
the high speed timing registers and their parameters.
Each edge location setting is 6 bits wide, but only 48 valid edge
locations are available. Therefore, the register values are mapped
into four quadrants, with each quadrant containing 12 edge
locations. Table XI shows the correct register values for the
corresponding edge locations.
Figure 4.High Speed Clock Resolution From CLI Master Clock Input
Figure 5.High Speed Clock Programmable Locations
Table X. H1CONTROL, RGCONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters

Partno	Mfg	Dc	Qty	Available	Descript
AD9948KCP	AD	N/a	642	avai	10-Bit CCD Signal Processor with Precision Timing⑩ Core
AD9948KCPRL	AD	N/a	5086	avai	10-Bit CCD Signal Processor with Precision Timing⑩ Core