AD9945KCPRL7 ,Complete 12-Bit 40 MHz CCD Signal ProcessorSPECIFICATIONS (T to T , AVDD = DVDD = DRVDD = 3.0 V, f = 40 MHz, unless otherwise noted.)MIN MAX S ..
AD9945KCPZ , Complete 12-Bit 40 MHz CCD Signal Processor
AD9945KCPZ , Complete 12-Bit 40 MHz CCD Signal Processor
AD9945KCPZRL7 , Complete 12-Bit 40 MHz CCD Signal Processor
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AD9945KCP-AD9945KCPRL7
Complete 12-Bit 40 MHz CCD Signal Processor
REV.A
Complete 12-Bit 40 MHz
CCD Signal Processor
FEATURES
40 MSPS Correlated Double Sampler (CDS)
6 dB to 40 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Optical Black Clamp Circuit
Preblanking Function
12-Bit 40 MSPS A/D Converter
No Missing Codes Guaranteed
3-Wire Serial Digital Interface
3 V Single-Supply Operation
Low Power: 140 mW @ 3 V Supply
Space-Saving 32-Lead 5 mm � 5 mm LFCSP
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
PC Cameras
Portable CCD Imaging Devices
CCTV Cameras
FUNCTIONAL BLOCK DIAGRAM
DATACLKSHDSHP
DOUTCCDIN
PBLKREFTREFB
AVDD
DVDD
DVSS
AVSS
DRVDD
DRVSS
SDATASCKSL
CLPOB
GENERAL DESCRIPTIONThe AD9945 is a complete analog signal processor for CCD
applications. It features a 40 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9945’s signal chain
consists of a correlated double sampler (CDS), a digitally con-
trolled variable gain amplifier (VGA), a black level clamp, and a
12-bit A/D converter.
The internal registers are programmed through a 3-wire serial digital
interface. Programmable features include gain adjustment, black
level adjustment, input clock polarity, and power-down modes.
The AD9945 operates from a single 3 V power supply, typi-
cally dissipates 140 mW, and is packaged in a space-saving
32-lead LFCSP.
AD9945–SPECIFICATIONS
GENERAL SPECIFICATIONSPOWER SUPPLY VOLTAGE
Specifications subject to change without notice.
DIGITAL SPECIFICATIONSLOGIC OUTPUTS
Specifications subject to change without notice.
(DRVDD = DVDD = 2.7 V, CL = 20 pF, unless otherwise noted.)
(TMIN to TMAX, AVDD = DVDD = DRVDD= 3.0 V, fSAMP = 40 MHz, unless otherwise noted.)
AD9945BLACK LEVEL CLAMP
A/D CONVERTER
*Input Signal Characteristics defined as follows:
Specifications subject to change without notice.
SYSTEM SPECIFICATIONS(TMIN to TMAX, AVDD = DVDD = DRVDD = 3.0 V, fSAMP = 40 MHz, unless otherwise noted.)
AD9945
TIMING SPECIFICATIONSDATA OUTPUTS
SERIAL INTERFACE
*Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
(CL = 20 pF, fSAMP = 40 MHz, CCD Mode Timing in Figures 8 and 9, Serial Timing in Figures 4 and 5.)
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9945 features proprietary ESD protection circuitry, permanent damage may occur on devices
ABSOLUTE MAXIMUM RATINGS*
ParameterAVDD
DVDD
DRVDD
Digital Outputs
SHP, SHD, DATACLK
CLPOB, PBLK
SCK, SL, SDATA
REFT, REFB, CCDIN
Junction Temperature
Lead Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
ORDERING GUIDE
ModelAD9945KCP
AD9945KCPRL
AD9945KCPRL7
AD9945KCPZ
AD9945KCPZRL7
1LFCSP = Lead Frame Chip Scale Package
2Z = Pb-free part.
THERMAL CHARACTERISTICS
Thermal Resistance32-Lead LFCSP Package
θJA = 27.7 °C/W
PIN CONFIGURATION
TOP VIEW
24 REFB
23 REFT
22 CCDIN
21 AVSS
D2 1
D3 2
D4 3
32 D1
20 AVDD
19 SHD
18 SHP
17 CLPOB
D10
D11 10
DRVDD 11DRVSS 12
DVDD 13
DATACLK
1
DVSS 15
PBLK 1
D5 4
D6 5
D7 6
D8 7
D9 8
31 D030 NC29 NC28 NC27 SCK26 SDATA25 SL
AD9945
PIN 1
INDICATOR
PIN FUNCTION DESCRIPTIONSTYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
AD9945
EQUIVALENT INPUT CIRCUITSFigure 1.Digital Inputs—SHP, SHD,
DATACLK, CLPOB, PBLK, SCK, SL, SDATA
DVDD
DVSSDRVSS
DRVDD
THREE-
STATE
DATA
DOUTFigure 3. CCDIN (Pin 22)
DEFINITIONS OF SPECIFICATIONS
Differential Nonlinearity (DNL)An ideal ADC exhibits code transitions that are exactly 1LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes must be present
over all operating conditions.
Peak NonlinearityPeak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9945 from a true straight
line. The point used as zero scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 11/2LSB
beyond the last code transition. The deviation is measured from
the middle of each particular output code to the true straight line.
The error is then expressed as a percentage of the 2V ADC full-
scale signal. The input signal is always appropriately gained up to
fill the ADC’s full-scale range.
Total Output NoiseThe rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated in
LSB and represents the rms noise level of the total signal chain
at the specified gain setting. The output noise can be converted
to an equivalent voltage, using the relationship
1 LSB = (ADC Full Scale/2N codes)
where N is the bit resolution of the ADC. For the AD9945,
1 LSB is 0.5mV.
Power Supply Rejection (PSR)The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9945’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
Internal Delay for SHP/SHDThe internal delay (also called aperture delay) is the delay that
occurs from the time when a sampling edge is applied to the
AD9945 until the actual sample of the input signal is held. Both
SHP and SHD sample the input signal during the transition from
low to high, so the internal delay is measured from each clock’s
rising edge to the instant the actual internal sample is taken.
TPC 1.Power vs. Sampling Rate
TPC 2.Typical DNL Performance
AD9945
INTERNAL REGISTER DESCRIPTION
Table I.Internal Register MapNOTE: All register values default to 0x000 at power-up except clamp level, which defaults to 128 decimal (128 LSB clamp level).
