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AD9901KP-AD9901KQ
Ultrahigh Speed Phase/Frequency Discriminator
REV.B
Ultrahigh Speed
Phase/Frequency Discriminator
GENERAL DESCRIPTIONThe AD9901 is a digital phase/frequency discriminator capable
of directly comparing phase/frequency inputs up to 200 MHz.
Processing in a high speed trench-oxide isolated process, com-
bined with an innovative design, gives the AD9901 a linear
detection range, free of indeterminate phase detection zones
common to other digital designs.
With a single +5 V supply, the AD9901 can be configured to
operate with TTL or CMOS logic levels; it can also operate
with ECL inputs when operated with a –5.2 V supply. The
open-collector outputs allow the output swing to be matched to
post-filtering input requirements. A simple current setting resis-
tor controls the output stage current range, permitting a reduc-
tion in power when operated at lower frequencies.
FEATURES
Phase and Frequency Detection
ECL/TTL/CMOS Compatible
Linear Transfer Function
No “Dead Zone”
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Low Phase Noise Reference Loops
Fast-Tuning “Agile” IF Loops
Secure “Hopping” Communications
Coherent Radar Transmitter/Receiver ChainsA major feature of the AD9901 is its ability to compare
phase/frequency inputs at standard IF frequencies without
prescalers. Excessive phase uncertainty which is common with
standard PLL configurations is also eliminated. The AD9901
provides the locking speed of traditional phase/frequency dis-
criminators, with the phase stability of analog mixers.
The AD9901 is available as a commercial temperature range
device, 0°C to +70°C, and as a military temperature device,
–55°C to +125°C. The commercial versions are packaged in a
14-lead ceramic DIP and a 20-lead PLCC.
The AD9901 Phase/Frequency Discriminator is available in
versions compliant with MIL-STD-883. Refer to the Analog
Devices Military Products Databook or current AD9901/883B
data sheet for specifications.
FUNCTIONAL BLOCK DIAGRAM
XOR
OUTPUT
OUTPUTREFERENCE
INPUT
OSCILLATOR
INPUT
PHASE-LOCKED LOOP
AD9901–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1Positive Supply Voltage (+VS for TTL Operation) . . . . .+7 V
Negative Supply Voltage (–VS for ECL Operation) . . . . .–7 V
Input Voltage Range (TTL Operation) . . . . . . .0 V to +5.5 V
Differential Input Voltage (ECL Operation) . . . . . . . . . .4.0 V
ISET Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 mA
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 mA
ELECTRICAL CHARACTERISTICSOUTPUT CHARACTERISTICS
NOTESAbsolute maximum ratings are limiting values, to be applied individually, and beyond which the service ability of the circuit may be impaired. Functional operability
is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.Maximum junction temperature should not exceed +175°C for ceramic packages, +150°C for plastic packages. Junction temperature can be calculated by:
tJ = PD (qJA) +tA = PD (qJC) +tC
where:
PD = power dissipationJA = thermal impedance from junction to air (°C/W)qJC = thermal impedance from junction to case (°C/W)
tA = ambient temperature (°C)
tC = case temperature (°C)
typical thermal impedances:
AD9901 Ceramic DIP = qJA = 74°C/W; qJC = 21°C/W
AD9901 LCC = qJA = 80°C/W; qJC = 19°C/W
AD9901 PLCC = qJA = 88.2°C/W; qJC = 45.2°C/W3VL = +0.4 V; VH = +2.4 V.RSET = 47.5 W; RL = 182 W.
Operating Temperature Range
AD9901KQ/KP . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature2
Plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C
(6VS = +5.0 V [for TTL] or –5.2 V [for ECL], unless otherwise noted)
INPUT/OUTPUT EQUIVALENT CIRCUITS
(Based on DIP Pinouts)TTL InputECL InputOutput
DIE LAYOUT AND MECHANICAL INFORMATIONDie Dimensions . . . . . . . . . . . . . . . . .63 · 118 · 16 (–2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 · 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gold Eutectic
Bond Wire . . . . . . . .1.25 mil Aluminum; Ultrasonic Bonding
ORDERING GUIDE
AD9901 BURN-IN CIRCUIT
(Based on DIP ECL Pinouts)
DA3
DA2
–VS (–5.2V)
ECL HIGH
ECL LOW
DA2
ECL HIGH
ECL LOW
DA3
ALL RESISTORS 65%
ALL CAPACITORS 620%
ALL SUPPLY VOLTAGES 65%
VMID = –1.3V 65%
STATIC: DA2 = ECL HIGH; DA3 = ECL LOW
DYNAMIC: ECL HIGH
5/12
+5.0V
VCO/REF, INPUT4/13
3/14
–5.2V
VCO/REF, INPUT
VCO/REF, INPUT
AD9901
TTL/CMOS MODE FUNCTIONAL PIN DESCRIPTIONSGROUNDGround connections for AD9901. Connect
all grounds together and to low impedance
ground plane as close to the device as
possible.
+VSPositive supply connection; nominally +5.0 V
for TTL operation.
BIASConnect to +VS (+5 V) for TTL operation.
VCO INPUTTTL compatible input; normally connected
to the VCO output signal. VCO INPUT and
REFERENCE INPUT are equivalent to one
another.
OUTPUTThe noninverted output. In TTL/CMOS
mode, the output swing is approximately
+3.2 V to +5 V.
RSETExternal RSET connection. The current
through the RSET resistor is equal to the maxi-
mum full-scale output current. RSET should
be connected to ground through an external
resistor in TTL mode. ISET = 0.47 V/RSET =
ILOAD (max).
OUTPUTThe inverted output. In TTL/CMOS mode,
the output swing is approximately +3.2 V to
+5 V.
REFERENCETTL compatible input, normally connected
INPUTto the reference input signal. The VCO
INPUT and the REFERENCE INPUT are
equivalent.
+VS
+VSFigure 1.TTL Mode (Based on DIP Pinouts)
ECL MODE FUNCTIONAL PIN DESCRIPTIONS–VSNegative supply connection, nominally
–5.2 V for ECL operation.
BIASConnect to –5.2 V for ECL operation.
VCO INPUTInverted side of ECL compatible differential
input, normally connected to the VCO output
signal.
VCO INPUTNoninverted side of ECL-compatible
differential input, normally connected to the
VCO output signal.
OUTPUTThe noninverted output. In ECL mode, the
output swing is approximately 0 V to –1.8 V.
GROUNDGround connections for AD9901. Connect
all grounds together and to low-impedance
ground plane as close to the device as
possible.
RSETExternal RSET connection. The current
through the RSET resistor is equal to the maxi-
mum full-scale output current. RSET should
be connected to –VS through an external
resistor in ECL mode. ISET = 0.47 V/RSET =
ILOAD (max).
OUTPUTThe inverted output. In ECL mode, the out-
put swing is approximately 0 V to –1.8 V.
REFERENCENoninverted side of ECL-compatible
INPUTdifferential input, normally connected to the
reference input signal. The VCO INPUT and
the REFERENCE INPUT are equivalent to
one another.
REFERENCEInverted side of ECL-compatible differentialINPUTinput, normally connected to the reference
input signal. The VCO INPUT and theREFERENCE INPUT are equivalent.
REFERENCE
–VSFigure 2.ECL Mode (Based on DIP Pinouts)
TTL DIP Pinouts
GROUND
BIAS
GROUND
GROUND
VCO INPUT
OUTPUT
+VS
GROUND
GROUND
REFERENCE INPUT
+VS
OUTPUT
RSET
GROUND
TTL LCC Pinouts19123
910111213NC = NO CONNECT
GROUNDREFERENCE INPUT
BIAS
OUTPUT
GROUNDNCGROUNDGROUND
GROUND
SETNC
GROUND+VSNC
VCO INPUTOUTPUT
TTL PLCC Pinouts
NC = NO CONNECT
GROUNDREFERENCE INPUT
BIAS
GROUNDNC
VCO INPUT+VS
OUTPUTNCOUTPUT
GROUND
GROUND
GROUND
GROUND
SET
PIN CONFIGURATIONS
ECL DIP Pinouts
–VS
BIAS
VCO INPUT
VCO INPUT
–VS
OUTPUT
GROUND
REFERENCE INPUT
REFERENCE INPUT
–VS
GROUND
OUTPUT
RSET
–VS
ECL LCC Pinouts19123
910111213NC = NO CONNECT
VCO INPUT–VS
BIAS
OUTPUTREFERENCE INPUTREFERENCE INPUT
GROUND
SETNC
VCO INPUTGROUNDNC
–VSOUTPUT
ECL PLCC Pinouts
NC = NO CONNECT
VCO INPUT–VS
BIAS
VCO INPUTNC
–VSGROUND
OUTPUTNCOUTPUT
REFERENCE INPUT
REFERENCE INPUT
AD9901
THEORY OF OPERATIONA phase detector is one of three basic components of a phase-
locked loop (PLL); the other two are a filter and a tunable oscil-
lator. A basic PLL control system is shown in Figure 3.
AD9901
REFERENCE
INPUT
OSCILLATOR
OUTPUT
OPTIONAL 1/N PRESCALER
TYPICAL OF DIGITAL PLLsFigure 3.Phase-Locked Loop Control System
The function of the phase detector is to generate an error signal
that is used to retune the oscillator frequency whenever its out-
put deviates from a reference input signal. The two most com-
mon methods of implementing phase detectors are (1) an analog
mixer and (2) a family of sequential logic circuits known as
digital phase detectors.
The AD9901 is a digital phase detector. As illustrated in the
block diagram of the unit, straightforward sequential logic de-
sign is used. The main components include four “D” flip-flops,
an exclusive-OR gate (XOR) and some combinational output
logic. The circuit operates in two distinct modes: as a linear
phase detector and as a frequency discriminator.
When the reference and oscillator are very close in frequency,
only the phase detection circuit is active. If the two inputs are
substantially different in frequency, the frequency discrimina-
tion circuit overrides the phase detector portion to drive the
oscillator frequency toward the reference frequency and put it
within range of the phase detector.
Input signals to the AD9901 are pulse trains, and its output
duty cycle is proportional to the phase difference of the oscilla-
tor and reference inputs. Figures 4, 5 and 6 illustrate, respec-
tively, the input/output relationships at lock; with the
DC MEAN VALUE
REFERENCE
INPUT
OSCILLATOR
INPUT
REFERENCE
FLIP-FLOP
OUTPUT
OSCILLATOR
FLIP-FLOP
OUTPUT
XORGATE
OUTPUTFigure 4.AD9901 Timing Waveforms at “Lock”
REFERENCE
INPUT
OSCILLATOR
INPUT
REFERENCE
FLIP-FLOP
OUTPUT
OSCILLATOR
FLIP-FLOP
DC MEAN VALUE
REFERENCE
INPUT
OSCILLATOR
INPUT
REFERENCE
FLIP-FLOP
OUTPUT
OSCILLATOR
FLIP-FLOP
OUTPUT
XORGATE
OUTPUTFigure 6.Timing Waveforms (fOUT Lags fIN)
oscillator leading the reference frequency; and with the oscillator
lagging. This output pulse train is low-pass filtered to extract the
dc mean value [Kf (fI – fO)] where Kf is a proportionality con-
stant (phase gain).
At or near lock (Figures 4, 5 and 6), only the two input flip-
flops and the exclusive-OR gate (the phase detection circuit) are
active. The input flip-flops divide both the reference and oscilla-
tor frequencies by a factor of two. This insures that inputs to the
exclusive-OR are square waves, regardless of the input duty
cycles of the frequencies being compared. This division-by-two
also moves the nonlinear detection range to the ends of the
range rather than near lock, which is the case with conventional
digital phase detectors.
Figure 7 illustrates the constant gain near lock.
PHASE DIFFERENCE AT INPUTS
–2p0
OUTPUT VOLTAGE SWINGFigure 7.Phase Gain Plot
When the two square waves are combined by the XOR, the
output has a 50% duty cycle if the reference and oscillator in-
puts are exactly 180° out of phase; under these conditions, the
AD9901 is operating in a locked mode. Any shift in the phase
relationship between these input signals causes a change in the
output duty cycle. Near lock, the frequency discriminator flip-
flops provide constant HIGH levels to gate the XOR output to
the final output.
The duty cycle of the AD9901 is a direct measure of the phase
difference between the two input signals when the unit is near
lock. The transfer function can be stated as [Kf(fI – fO](V/RAD),
where Kf is the allowable output voltage range of the AD9901
divided by 2 p.
