AD9888KS-100 ,100/140/170/205 MSPS Analog Flat Panel InterfaceSPECIFICATIONSD DD1Test AD9888KS-100/-140 AD9888KS-170 AD9888KS-205Parameter Temp Level Min Typ Max ..
AD9888KS-140 ,100/140/170/205 MSPS Analog Flat Panel InterfaceSPECIFICATIONSD DD1Test AD9888KS-100/-140 AD9888KS-170 AD9888KS-205Parameter Temp Level Min Typ Max ..
AD9888KS-170 ,100/140/170/205 MSPS Analog Flat Panel InterfaceSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVEL ..
AD9888KS-205 ,100/140/170/205 MSPS Analog Flat Panel InterfaceGENERAL DESCRIPTION The AD9888’s on-chip PLL generates a pixel clock from HSYNCThe AD9888 is a comp ..
AD9888KSZ-170 , 100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface
AD9889BBSTZ-165 , High Performance HDMI/DVI Transmitter
ADSP21160MKB-80 ,SHARC, 80 MHz, 600 MFLOPS, 3.3v I/O, 2.5v core, floating pointapplications. The ADSP-21160M Single-cycle Execution (with or without SIMD) of: A includes an 80 MH ..
ADSP-21161NCCA100 ,DSP MicrocomputerFEATURES (continued) 32-48, 16-48, 8-48 Execution Packing for Executing 1 M Bit On-Chip Dual-Ported ..
ADSP-21161NCCAZ100 , SHARC Processor
ADSP-21161NKCA100 ,DSP MicrocomputerFEATURESSingle-Instruction-Multiple-Data (SIMD) Computational 100 MHz (10 ns) Core Instruction Rate ..
ADSP-21161NKCA-100 ,DSP MicrocomputerGENERAL DESCRIPTIONDMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 7The ADSP-2 ..
ADSP-21262SKBC-200 ,SHARC ProcessorCharacteristics .....38Phase-Locked Loop ........8136-Ball BGA Pin Configurations .....39Power Sup ..
AD9888KS-100-AD9888KS-140-AD9888KS-170-AD9888KS-205
100/140/170/205 MSPS Analog Flat Panel Interface
REV.A
100/140/170/205 MSPS Analog
Flat Panel Interface
FUNCTIONAL BLOCK DIAGRAM
FEATURES
205 MSPS Maximum Conversion Rate
500 MHz Programmable Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
Less than 450 ps p-p PLL Clock Jitter @ 205 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for “Hot Plugging”
2:1 Analog Input Mux
4:2:2 Output Format Mode
Midscale Clamping
Power-Down Mode
Low Power: <1 W Typical @ 205 MSPS
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TV
GENERAL DESCRIPTIONThe AD9888 is a complete 8-bit, 205 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 205 MSPS encode
rate capability and full-power analog bandwidth of 500 MHz
supports resolutions up to UXGA (1600 × 1200 at 75 Hz).
For ease of design and to minimize cost, the AD9888 is a fully
integrated interface solution for flat panel displays. The AD9888
includes an analog interface with a 205 MHz triple ADC with
internal 1.25 V reference, PLL to generate a pixel clock from
HSYNC and COAST, midscale clamping, and programmable
gain, offset, and clamp control. The user provides only a 3.3 V
power supply, analog input, and HSYNC and COAST signals.
Three-state CMOS outputs may be powered from 2.5 V to 3.3V.
The AD9888’s on-chip PLL generates a pixel clock from HSYNC
and COAST inputs. Pixel clock output frequencies range fromMHz to 205 MHz. PLL clock jitter is less than 450 ps p-p
typical at 205 MSPS. When the COAST signal is presented, the
PLL maintains its output frequency in the absence of HSYNC.
A sampling phase adjustment is provided. Data, HSYNC, and
Clock output phase relationships are maintained. The PLL can
be disabled and an external clock input provided as the pixel
clock. The AD9888 also offers full sync processing for compos-
ite sync and Sync-on-Green applications.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This interface is fully pro-
grammable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9888 is pro-
vided in a space-saving 128-lead MQFP surface mount plastic
package and is specified over the 0°C to 70°C temperature range.
AD9888–SPECIFICATIONS(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate)SWITCHING PERFORMANCE
DIGITAL INPUTS
AD9888NOTESAD9888KS-100 specifications are tested at 100 MHz. AD9888KS-140 specifications are tested at 140 MHz.See Figure 23.VCO Range = 10, Charge Pump Current = 100, PLL Divider = 1693.VCO Range = 11, Charge Pump Current = 100, PLL Divider = 2159.DEMUX = 1, DATACK and DATACK Load = 15 pF, Data Load = 5 pF.Maximum bandwidth setting. Bandwidth can also be programmed to 300 MHz, 150 MHz, and 75 MHz.Using External Pixel Clock.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level100% production tested.
II.100% production tested at 25°C and sample tested at
specified temperatures.
III.Sample tested only.
IV.Parameter is guaranteed by design and characterization
testing.Parameter is a typical value only.
VI.100% production tested at 25°C; guaranteed by design and
characterization testing.
ABSOLUTE MAXIMUM RATINGS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . –25°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9888 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ORDERING GUIDE
AD9888
PIN CONFIGURATION
VSOUTSOGOUTHSOUTD
ATA
ATA
GNDGNDGND
VDD
GND
GND
GND
GND
VDD
GND
DGA0
FIL
DGA1
DGA2
DGA3
AST
DGA4
CKEXT
DGA5
GND
DGA6
DGA7
DGB7
VDD
GND
DBA0
DBA1
DBA2
DBA3
DBA4
REF BYPASS
GND
GND
RAIN0
RAIN1
RMIDSCV
GND
SOGIN0
GAIN0
GND
SOGIN1
GAIN1
GND
BAIN0
GND
BAIN1
BMIDSCV
GND
GND
CKINV
CLAMP
SDA
SCL
DBA5
DBA6
VDD
GND
DGB0
DGB1
DGB2
DGB3
DGB4
DGB5
DGB6
GND
GND
PVD
DBA7
VDD
GND
GND
GND
GND
GND
VSYNC1HSYNC1VSYNC0HSYNC0
GND
GND
Table I.Complete Pinout ListSync Outputs
Clamp Voltages
Serial Port
(2-Wire
Data Clock
AD9888
PIN FUNCTION DESCRIPTIONSBAIN0
RAIN1
BAIN1
HSYNC0
HSYNC1
VSYNC0
VSYNC1
SOGIN0
SOGIN1
CLAMP
COAST
CKEXT
PIN FUNCTION DESCRIPTIONS (continued)
OutputsDRA7-0
DRB7-0
DGA7-0
DGB7-0
DBA7-0
DBB7-0
DATACK
DATACK
HSOUT
SOGOUT
REF BYPASS
AD9888
PIN FUNCTION DESCRIPTIONS (continued)
Power SupplyVDD
Serial Port (2-Wire)For a full description of the 2-wire serial register and how it works, refer to the Control Register section.
DESIGN GUIDE
General DescriptionThe AD9888 is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel monitors
or projectors. The circuit is ideal for providing a computer inter-
face for HDTV monitors or as the front-end to high-performance
video scan converters.
Implemented in a high-performance CMOS process, the inter-
face can capture signals with pixel rates of up to 205 MHz, and
with an Alternate Pixel Sampling mode, up to 340 MHz.
The AD9888 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a
2-wire serial interface. Full integration of these sensitive analog
functions makes system design straightforward and less sensitive
to the physical and electrical environment.
With a typical power dissipation of only 650 mW and an operat-
ing temperature range of 0°C to 70°C, the device requires no
special environmental considerations.
Input Signal HandlingThe AD9888 has six high-impedance analog input pins for the
red, green, and blue channels. They will accommodate signals
ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a DVI-I
connector, a 15-pin D connector, or via BNC connectors. The
At that point, the signal should be resistively terminated (to the
signal ground return) and capacitively coupled to the AD9888
inputs through 47 nF capacitors. These capacitors form part of
the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal
bandwidth. The ultrawide bandwidth inputs of the AD9888
(500 MHz) can track the input signal continuously as it moves
from one pixel level to the next, and digitize the pixel during
a long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. The AD9888 can digitize graphics signals over a
very wide range of frequencies (10 MHz to 205 MHz). Often
characteristics that are beneficial at one frequency can be detri-
mental at another. Analog bandwidth is one such characteristic.
For UXGA resolutions (up to 205 MHz), a very high analog
bandwidth is desirable because of the fast input signal slew
rates. For VGA and lower resolutions (down to 12.5 MHz), a
very high bandwidth is not desirable, because it allows excess
noise to pass through. To accommodate these varying needs,
the AD9888 includes variable analog bandwidth control.
Four settings are available (75 MHz, 150 MHz, 300 MHz,
and 500 MHz), allowing the analog bandwidth to be matched
with the resolution of the incoming graphics signal.
Sync ProcessingThe AD9888 contains circuitry that enables it to accept com-
posite sync inputs, such as Sync-on-Green or the trilevel syncs
found in digital TV signals. A complete description of the sync
processing functionality is found in the Sync Slicer and Sync
Separator sections.
Hsync, Vsync InputsThe interface also takes a horizontal sync signal, which is used
to generate the pixel clock and clamp timing. It is possible to
operate the AD9888 without applying Hsync (using an external
clock, external clamp, and single port output mode) but a number
of features of the chip will be unavailable, so it is recommended
that Hsync be provided. This can be either a sync signal directly
from the graphics source, or a preprocessed TTL or CMOS
level signal.
The Hsync input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no ter-
mination is required or desired.
Serial Control PortThe serial control port is designed for 3.3 V logic. If there areV drivers on the bus, these pins should be protected with
150Ω series resistors placed between the pull-up resistors and
the input pins.
Output Signal HandlingThe digital outputs are designed and specified to operate from a
3.3 V power supply (VDD). They can also work with a VDD as
low as 2.5V for compatibility with other 2.5V logic.
Clamping
RGB ClampingTo digitize the incoming signal properly, the dc offset of the input
must be adjusted to fit the range of the on-board A/Dconverters.
Most graphics systems produce RGB signals with black at ground
and white at approximately 0.75 V. However, if sync signals are
embedded in the graphics, the sync tip is often at ground and
black is at 300 mV. Then white is at approximately 1.0 V. Some
common RGB line amplifier boxes use emitter-follower buffers
to split signals and increase drive capability. This introduces a
700 mV dc offset to the signal, which must be removed for
proper capture by the AD9888.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. An
offset is then introduced which results in the A/D converters
producing a black output (code 00h) when the known black
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to
eliminate offset errors.
In most graphics systems, black is transmitted between active
video lines. Going back to CRT displays, when the electron
beam has completed writing a horizontal line on the screen
(at the right side), the beam is deflected quickly to the left side
of the screen (called horizontal retrace) and a black signal is
provided to prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
a period following Hsync called the back porch where a good
black reference is provided. This is the time when clamping
should be done.
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time (with External Clamp = 1).
The polarity of this signal is set by the Clamp Polarity (Register
0Fh, Bit 6).
A simpler method of clamp timing employs the AD9888 inter-
nal clamp timing generator. The Clamp Placement register is
programmed with the number of pixel times that should pass
after the trailing edge of HSYNC before clamping starts. A
second register (Clamp Duration, Register 06h) sets the duration
of the clamp. These are both 8-bit values, providing considerable
flexibility in clamp generation. The clamp timing is referenced
to the trailing edge of Hsync because, though Hsync duration
can vary widely, the back porch (black reference) always follows
Hsync. A good starting point for establishing clamping is to set
the clamp placement to 08h (providing 8 pixel periods for the
graphics signal to stabilize after sync) and set the clamp dura-
tion to 14h (giving the clamp 20 pixel periods to reestablish the
black reference).
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capacitor
affects the performance of the clamp. If it is too small, there will
be a significant amplitude change during a horizontal line time
(between clamping intervals). If the capacitor is too large, then
it will take excessively long for the clamp to recover from a large
change in incoming signal offset. The recommended value (47nF)
results in recovering from a step error of 100 mV to within
1/2LSB in 10 lines with a clamp duration of 20 pixel periods
on a 60 Hz SXGA signal.
YUV ClampingYUV graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) can be at
the midpoint of the video signal rather than the bottom. For
these signals it can be necessary to clamp to the midscale range
of the A/D converter range (80h) rather than bottom of the
A/Dconverter range (00h).
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the series bus register. The red
and blue channels each have their own selection bit so that they
can be clamped to either midscale or ground independently. The
clamp controls are located in register 10h and are Bits 1 and 2.
The midscale reference voltage that each A/D converter clamps
to is provided independently on the RMIDSCV and BMIDSCV
pins. These two pins should be bypassed to ground with a
0.1µF capacitor (even if midscale clamping is not required).
Gain and Offset ControlThe AD9888 can accommodate input signals with inputs ranging
from 0.5 V to 1.0 V full scale. The full-scale range is set in three
8-bit registers (Red Gain, Green Gain, and Blue Gain; Registers
08h, 09h, and 10h respectively).
Note that increasing the gain setting results in an image with
less contrast.
The offset control shifts the entire input range, resulting in a
AD9888The offset controls provide a ±63 LSB adjustment range. This
range is connected with the full-scale range, so if the input range
is doubled (from 0.5 V to 1.0 V), the offset step size is also
doubled (from 2 mV per step to 4 mV per step).
Figure 2 illustrates the interaction of gain and offset controls.
The magnitude of an LSB in offset adjustment is proportional
to the full-scale range, so changing the full-scale range also
changes the offset. The change is minimal if the offset setting is
near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same amount
as the zero-scale level.
Figure 2.Gain and Offset Control
Sync-on-GreenThe Sync-on-Green input operates in two steps. First, it sets a
baseline clamp level off of the incoming video signal with a
negative peak detector. Second, it sets the sync trigger level
(nominally 150 mV above the negative peak). The exact trigger
level is variable and can be programmed via register 11H. The
Sync-on-Green input must be ac-coupled to the green analog
input through its own capacitor as shown in Figure 3. The value
of the capacitor must be 1 nF ± 20%. If Sync-on-Green is not
used, this connection is not required and the SOGIN pin should be
left unconnected. (Note: the Sync-on-Green signal is always
negative polarity.) For more details, see the Sync Processing section.
Figure 3.Typical Clamp Configuration for RGB/YUV
Applications
Clock GenerationA Phase Locked Loop (PLL) is employed to generate the pixel
clock. The Hsync input provides a reference frequency to the PLL.
A Voltage Controlled Oscillator (VCO) generates a much higher
pixel clock frequency. This pixel clock is divided by the PLL
divide value (registers 01H and 02H) and phase compared with
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,
there is a period during which the signal is slewing from the old
pixel amplitude and settling at its new value. Then there is a time
when the input voltage is stable, before the signal must slew to a
new value (Figure 4). The ratio of the slewing time to the stable
time is a function of the bandwidth of the graphics DAC and the
bandwidth of the transmission system (cable and termination). It
is also a function of the overall pixel rate. Clearly, if the dynamic
characteristics of the system remain fixed, then the slewing and
settling time is likewise fixed. This time must be subtracted from
the total pixel period, leaving the stable period. At higher pixel
frequencies, the total cycle time is shorter, and the stable pixel
time becomes shorter as well.
Figure 4.Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined, and must also be subtracted
from the stable pixel time.
Considerable care has been taken in the design of the AD9888’s
clock generation circuit to minimize jitter. As indicated in Fig-
ure 5, the clock jitter of the AD9888 is less than 9% of the total
pixel time in all operating modes, making the reduction in the valid
sampling time due to jitter negligible.
Figure 5.Pixel Clock Jitter vs. Frequency
The PLL characteristics are determined by the loop filter design,
by the PLL Charge Pump Current and by the VCO range setting.
Figure 6. PLL Loop Filter Detail
Four programmable registers are provided to optimize the per-
formance of the PLL. These registers are:The 12-Bit Divisor Registers. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock fre-
quencies in the range of 10 MHz to 205 MHz. The Divisor
Register controls the exact multiplication factor. This regis-
ter may be set to any value between 221 and 4095. (The
divide ratio that is actually used is the programmed divide
ratio plus one.)The 2-Bit VCO Range Register. To lower the sensitivity of
the output frequency to noise on the control signal, the VCO
operating frequency range is divided into four overlapping
regions. The VCO Range register sets this operating range.
Because there are only four possible regions, only the two
least significant bits of the VCO Range register are used. The
frequency ranges for the lowest and highest regions are shown
in Table II.The 3-Bit Charge Pump Current Register. This register allows
the current that drives the low-pass loop filter to be varied.
The possible current values are listed in Table III.
Table II.VCO Frequency Ranges
Table III.Charge Pump Current/Control Bits
Table IV.Recommended VCO Range and Charge Pump Current Settings for Standard Display FormatsVGA
QXGA
AD9888The 5-Bit Phase Adjust Register. The phase of the generated
sampling clock may be shifted to locate an optimum sampling
point within a clock cycle. The Phase Adjust Register provides
32 phase-shift steps of 11.25° each. The Hsync signal with an
identical phase shift is available through the HSOUT pin.
Phase adjustment is still available if the pixel clock is being
provided externally.
The COAST pin is used to allow the PLL to continue to run
at the same frequency, in the absence of the incoming Hsync
signal. This may be used during the vertical sync period, or
any other time that the Hsync signal is unavailable. The polarity
of the COAST signal may be set through the COAST
Polarity Register. Also, the polarity of the Hsync signal may be
set through the Hsync Polarity Register.
Alternate Pixel Sampling ModeA Logic 1 input on Clock Invert (CKINV, Pin 29) inverts the
nominal ADC clock. CKINV can be switched between frames
to implement the alternate pixel sampling mode. This allows
higher effective image resolution to be achieved at lower pixel
rates but with lower frame rates.
Figure 7.Odd and Even Pixels in a Frame
On one frame, only even pixels are digitized. On the subsequent
frame, odd pixels are sampled. By reconstructing the entire frame
in the graphics controller, a complete image can be reconstructed.
This is similar to the interlacing process that is employed in
broadcast television systems, but the interlacing is vertical
instead of horizontal. The frame data is still presented to the
display at the full desired refresh rate (usually 60 Hz) so there
are no flicker artifacts added.
Figure 9.Even Pixels from Frame 2
Figure 10.Combined Frame Output from Graphics
Controller
Figure 11.Subsequent Frame from Controller
TIMINGThe following timing diagrams show the operation of the AD9888
analog interface in all clock modes. The part establishes timing
by having the sample that corresponds to the pixel digitized
when the leading edge of Hsync occurs sent to the “A” data
port. In dual-channel mode, the next sample is sent to the “B”
port. Future samples are alternated between the “A” and “B”
data ports. In single-channel mode, data is only sent to the “A”
data port, and the “B” port is placed in a high impedance state.
The Output Data Clock signal is created so that its rising edge
always occurs between “A” data transitions, and can be used to
latch the output data externally.
Figure 12.Output Timing
Hsync TimingHorizontal sync is processed in the AD9888 to eliminate
ambiguity in the timing of the leading edge with respect to the
phase-delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360° in 32 steps via the Phase Adjust
register (to optimize the pixel sampling time). Display systems
use Hsync to align memory and display write cycles, so it is
important to have a stable timing relationship between Hsync
output (HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9888. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be pro-
grammed either active high or active low (Register 0EH, Bit 5).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via regis-
ter 07H. HSOUT is the sync signal that should be used to drive
the rest of the display system.
COAST TimingIn most computer systems, the Hsync signal is provided con-
tinuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary, and should not be used.
In some systems, however, Hsync is disturbed during the Verti-
cal Sync period (Vsync). In some cases, Hsync pulses disappear.
In other systems, such as those that employ Composite Sync
(Csync) signals or embedded Sync-On-Green (SOG), Hsync
includes equalization pulses or other distortions during Vsync.
To avoid upsetting the clock generator during Vsync, it is impor-
tant to ignore these distortions. If the pixel clock PLL sees
extraneous pulses, it will attempt to lock to this new frequency,
and will have changed frequency by the end of the Vsync period.
It will then take a few lines of correct Hsync timing to recover at
the beginning of a new frame, resulting in a “tearing” of the
image at the top of the display.
The COAST input is provided to eliminate this problem. It is
an asynchronous input that disables the PLL input and allows
the clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
AD9888Figure 13.Single-Channel Mode
Figure 14.Single-Channel Mode, Two Pixels/Clock (Even Pixels)
Figure 15.Single-Channel Mode, Two Pixels/Clock (Odd Pixels)
Figure 16.Dual-Channel Mode, Interleaved Outputs
Figure 17.Dual-Channel Mode, Parallel Outputs
Figure 18.Dual-Channel Mode, Interleaved Outputs, Two Pixels/Clock (Even Pixels)
AD9888Figure 19.Dual-Channel Mode, Interleaved Outputs, Two Pixels/Clock (Odd Pixels)
Figure 20.Dual-Channel Mode, Parallel Outputs, Two Pixels/Clock (Even Pixels)
Figure 21.Dual-Channel Mode, Parallel Outputs, Two Pixels/Clock (Odd Pixels)
