AD9886KS-140 ,Complete 8-Bit 140 MSPS Analog InterfaceSPECIFICATIONSD DDTest AD9886KS-100 AD9886KS-140Parameter Temp Level Min Typ Max Min ..
AD9887KS-100 ,Dual Interface for Flat Panel DisplaysSPECIFICATIONSANALOG INTERFACE (V = 3.3 V, V = 3.3 V, ADC Clock = Maximum Conversion Rate, unless o ..
AD9887KS-140 ,Dual Interface for Flat Panel DisplaysGENERAL DESCRIPTION2A0DATACKThe AD9887 offers designers the flexibility of a dual analog andHSOUTdi ..
AD9888KS-100 ,100/140/170/205 MSPS Analog Flat Panel InterfaceSPECIFICATIONSD DD1Test AD9888KS-100/-140 AD9888KS-170 AD9888KS-205Parameter Temp Level Min Typ Max ..
AD9888KS-140 ,100/140/170/205 MSPS Analog Flat Panel InterfaceSPECIFICATIONSD DD1Test AD9888KS-100/-140 AD9888KS-170 AD9888KS-205Parameter Temp Level Min Typ Max ..
AD9888KS-170 ,100/140/170/205 MSPS Analog Flat Panel InterfaceSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVEL ..
ADSP-2115KP-66 ,ADSP-2100 Family DSP Microcomputersfeatures plus 80K bytes of on-chip RAMand, on the ADSP-2111, a host interface port.configured as 16 ..
ADSP-2115KP-80 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 1768-Pin PGA (ADSP-2101) . . . ..
ADSP2115KS66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2180-Lead PQFP, 80-Lead TQFP . ..
ADSP-2115KS-66 ,ADSP-2100 Family DSP Microcomputersapplications. TheFamily processor with host interface port,ADSP-21xx processors are all built upon ..
ADSP-2115KS-66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 1768-Pin PGA (ADSP-2101) . . . ..
ADSP-2115KS-80 ,ADSP-2100 Family DSP MicrocomputersSPECIFICATIONSPACKAGE OUTLINE DIMENSIONS(ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . . ..
AD9886KS-100-AD9886KS-140
Complete 8-Bit 140 MSPS Analog Interface
REV.0
Analog Interface for
Flat Panel Displays
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Analog Interface
140 MSPS Maximum Conversion Rate
330 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamp for YUV Applications
GENERAL DESCRIPTIONThe AD9886 is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140MSPS encode
rate capability and full-power analog bandwidth of 330MHz
supports resolutions up to SXGA (1280 × 1024 at 75 Hz).
For ease of design and to minimize cost, the AD9886 is a fully
integrated interface solution for FPDs. The AD9886 includes a
140 MHz triple ADC with internal 1.25 V reference, PLL to
generate a pixel clock from an HSYNC, and programmable
gain, offset, and clamp control. The user provides only a 3.3 V
power supply, analog input, and an HSYNC signal. Three-state
CMOS outputs may be powered from 2.5V to 3.3V.
The AD9886’s on-chip PLL generates a pixel clock from an
HSYNC. Pixel clock output frequencies range from 12 MHz to
140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of HSYNC. A sampling phase
adjustment is provided. Data, HSYNC and Clock output phase
relationships are maintained. The PLL can be disabled and an
external clock input provided as the pixel clock. The AD9886
also offers full sync processing for composite sync and sync-on-
green applications.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This interface is fully pro-
grammable via a 2-wire serial interface.
AD9886–SPECIFICATIONS(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate.)
AD9886NOTESDrive Strength = 11.VCO Range = 01, Charge Pump Current = 001, PLL Divider = 1693.VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1600.DEMUX = 1, DATACK and DATACK Load = 10 pF, Data Load = 5 pF.Using external pixel clock.
Specifications subject to change without notice.
AD9886
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9886 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . –25°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
ORDERING GUIDE
EXPLANATION OF TEST LEVELS
Test Level100% production tested.100% production tested at 25°C and sample tested at
specified temperatures.
IIISample tested only.Parameter is guaranteed by design and characterization testing.Parameter is a typical value only.100% production tested at 25°C; guaranteed by design and
characterization testing.
PIN CONFIGURATION
RED B<0>RED B<1>RED B<2>RED B<3>RED B<4>RED B<5>RED B<6>RED B<7>GNDVDDRED A<0>RED A<1>RED A<2>RED A<3>RED A<4>RED A<5>RED A<6>RED A<7>GNDVDDSOGOUTHSOUTVSOUTNCS
CDT
DATACLKBDATACLKGNDVDDGNDGNDSCAN
GNDVDREF
OUT
REFVDGNDGND
GNDGND
VDD
GND
SCAN
OUTNCNCNC
SCAN
CLK
GNDVDVDNCNC
GNDNC
GNDNC
GNDNCVDVD
GNDNCNCNC
GND
PVD
GND
PVDFILTPVD
GND
VDD
GND
GREEN A<7>
GREEN A<6>
GREEN A<5>
GREEN A<4>
GREEN A<3>
GREEN A<2>
GREEN A<1>
GREEN A<0>
VDD
GND
GREEN B<7>
GREEN B<6>
GREEN B<5>
GREEN B<4>
GREEN B<3>
GREEN B<2>
GREEN B<1>
GREEN B<0>
VDD
GND
BLUE A<7>
BLUE A<6>
BLUE A<5>
BLUE A<4>
BLUE A<3>
BLUE A<2>
BLUE A<1>
BLUE A<0>
VDD
GND
BLUE B<7>
BLUE B<6>
BLUE B<5>
BLUE B<4>
BLUE B<3>
BLUE B<2>
BLUE B<1>
BLUE B<0>
RMIDSCV
RAIN
RCLAMPV
GND
GND
GND
GMIDSCV
GAIN
GCLAMPV
SOGIN
GND
GND
GND
BMIDSCV
BAIN
BCLAMPV
GND
GND
CKINV
CLAMP
SDA
SCL
PVD
PVD
GND
GND
COAST
CKEXT
HSYNC
VSYNC
NC = NO CONNECT
AD9886
Table I.Complete Pinout ListInputs
External
Sync/Clock
Inputs
Sync Outputs
Voltage
Serial Port
(2-Wire
Serial Interface)
Data Outputs
Data Clock
Scan Function
No Connect
PIN FUNCTION DETAIL
InputsRAINAnalog Input for RED Channel
GAINAnalog Input for GREEN Channel
BAINAnalog Input for BLUE Channel
High-impedance inputs that accept the RED,
GREEN, and BLUE channel graphics signals,
respectively. (The three channels are identi-
cal and can be used for any colors, but colors
are assigned for convenient reference.)
They accommodate input signals ranging
from 0.5 V to 1.0 V full scale. Signals should
be ac-coupled to these pins to support clamp
operation.
HSYNCHorizontal Sync Input
This input receives a logic signal that estab-
lishes the horizontal timing reference and
provides the frequency reference for pixel
clock generation.
The logic sense of this pin is controlled by
serial register 0Fh Bit 7 (HSYNC Polarity).
Only the leading edge of HSYNC is active,
the trailing edge is ignored. When HSYNC
Polarity = 0, the falling edge of HSYNC is
used. When HSYNC Polarity = 1, the rising
edge is active.
The input includes a Schmitt trigger for noise
immunity, with a nominal input threshold
of 1.5 V.
Electrostatic Discharge (ESD) protection
diodes will conduct heavily if this pin is driven
more than 0.5 V above the maximum toler-
ance voltage (3.3 V), or more than 0.5 V
below ground.
VSYNCVertical Sync Input
This is the input for vertical sync.
SOGINSync-on-Green Input
This input is provided to assist with processing
signals with embedded sync, typically on the
GREEN channel. The pin is connected to a
high-speed comparator with an internally gen-
erated threshold, which is set to 0.15 V above
the negative peak of the input signal.
When connected to an ac-coupled graphics
signal with embedded sync, it will produce a
noninverting digital output on SOGOUT.
(This is usually a composite sync signal,
containing both vertical and horizontal sync
information that must be separated before
passing the horizontal sync signal to HSYNC).
When not used, this input should be left
unconnected. For more details on this func-
This logic input may be used to define the
time during which the input signal is clamped
to the reference dc level (ground for RGB or
midscale for YUV). It should be exercised
when the reference dc level is known to be
present on the analog input channels, typi-
cally during the back porch of the graphics
signal. The CLAMP pin is enabled by setting
control bit EXTCLMP to 1 (the default
power-up is 0). When disabled, this pin is
ignored and the clamp timing is determined
internally by counting a delay and duration
from the trailing edge of the HSYNC input.
The logic sense of this pin is controlled by
CLAMPOL. When not used, this pin must be
grounded and EXTCLMP programmed to 0.
COASTClock Generator Coast Input (Optional)
This input may be used to cause the pixel
clock generator to stop synchronizing with
HSYNC and continue producing a clock at
its current frequency and phase. This is useful
when processing signals from sources that fail
to produce horizontal sync pulses when in the
vertical interval. The COAST signal is gener-
ally not required for PC-generated signals.
The logic sense of this pin is controlled by
COAST Polarity.
When not used, this pin may be grounded
and COAST Polarity programmed to 1, or tied
HIGH (to VD through a 10 kΩ resistor) and
COAST Polarity programmed to 0. COAST
Polarity defaults to 1 at power-up.
CKEXTExternal Clock Input (Optional)
This pin may be used to provide an external
clock to the AD9886, in place of the clock
internally generated from HSYNC.
It is enabled by programming EXTCLK to 1.
When an external clock is used, all other inter-
nal functions operate normally. When unused,
this pin should be tied through a 10 kΩ resistor
to GROUND, and EXTCLK programmed to
0. The clock phase adjustment still operates
when an external clock source is used.
CKINVSampling Clock Inversion (Optional)
This pin may be used to invert the pixel
sampling clock, which has the effect of
shifting the sampling phase 180°. This is in
support of Alternate Pixel Sampling mode,
wherein higher-frequency input signals (up
to 280 Mpps) may be captured by first sam-
pling the odd pixels, then capturing the even
pixels on the subsequent frame.
This pin should be exercised only during
blanking intervals (typically vertical blanking)
AD9886
OutputsDRA7-0Data Output, Red Channel, Port A
DRB7-0Data Output, Red Channel, Port B
DGA7-0Data Output, Green Channel, Port A
DGB7-0Data Output, Green Channel, Port B
DBA7-0Data Output, Blue Channel, Port A
DBB7-0Data Output, Blue Channel, Port B
These are the main data outputs. Bit 7 is
the MSB.
Each channel has two ports. When the part is
operated in single-channel mode (DEMUX =
0), all data are presented to Port A, and Port B
is placed in a high-impedance state.
Programming DEMUX to 1 established dual-
channel mode, wherein alternate pixels are
presented to Port A and Port B of each chan-
nel. These will appear simultaneously, two
pixels presented at the time of every second
input pixel, when PAR is set to 1 (parallel
mode). When PAR = 0, pixel data appear
alternately on the two ports, one new sample
with each incoming pixel (interleaved mode).
In dual channel mode, the first pixel after
HSYNC is routed to Port A. The second
pixel goes to Port B, the third to A, etc. This
can be reversed by setting OUTPHASE to 1.
The delay from pixel sampling time to output
is fixed. When the sampling time is changed
by adjusting the PHASE register, the output
timing is shifted as well. The DATACK,
DATACK, and HSOUT outputs are also
moved, so the timing relationship among the
signals is maintained.
DATACKData Output Clock
DATACKData Output Clock Complement
Differential data clock output signals to be
used to strobe the output data and HSOUT
into external logic.
They are produced by the internal clock gen-
erator and are synchronous with the internal
pixel sampling clock.
When the AD9886 is operated in single-
channel mode, the output frequency is equal
to the pixel sampling frequency. When operat-
ing in dual channel mode, the clock frequency
is one-half the pixel frequency, as is the output
data frequency.
When the sampling time is changed by adjust-
ing the PHASE register, the output timing
is shifted as well. The Data, DATACK,
DATACK, and HSOUT outputs are all
moved, so the timing relationship among the
HSOUTHorizontal Sync Output
A reconstructed and phase-aligned version of
the Hsync input. Both the polarity and dura-
tion of this output can be programmed via
serial bus registers.
By maintaining alignment with DATACK,
DATACK, and Data, data timing with
respect to horizontal sync can always be
determined.
SOGOUTSync-On-Green Slicer Output
This pin can be programmed to output
either the output from the Sync-On-Green
slicer comparator or an unprocessed but
delayed version of the HSYNC input. See
the Sync Block Diagram to view how this
pin is connected.
(Note: Besides slicing off SOG, the output
from this pin receives no additional process-
ing on the AD9886. VSYNC separation is
performed via the sync separator.)
REFOUTInternal Reference Output
Output from the internal 1.25 V bandgap
reference. This output is intended to drive
relatively light loads. It can drive the AD9886
Reference Input directly, but should be exter-
nally buffered if it is used to drive other loads
as well.
The absolute accuracy of this output is ±4%,
and the temperature coefficient is ±50 ppm,
which is adequate for most AD9886 appli-
cations. If higher accuracy is required, an
external reference may be employed instead.
If an external reference is used, connect this
pin to ground through a 0.1 µF capacitor.
REFINReference Input
The reference input accepts the master refer-
ence voltage for all AD9886 internal circuitry
(1.25 V ±10%). It may be driven directly by
the REFOUT pin. Its high impedance pre-
sents a very light load to the reference source.
This pin should always be bypassed to Ground
with a 0.1 µF capacitor.
FILTExternal Filter Connection
For proper operation, the pixel clock genera-
tor PLL requires an external filter. Connect
the filter shown Figure 7 to this pin. For
optimal performance, minimize noise and
parasitics on this node.
Power SupplyMain Power Supply
These pins supply power to the main ele-
ments of the circuit. It should be as quiet and
filtered as possible.
VDDDigital Output Power Supply
A large number of output pins (up to 52)
switching at high speed (up to 140 MHz)
generates a lot of power supply transients
(noise). These supply pins are identified
separately from the VD pins so special care
can be taken to minimize output noise trans-
ferred into the sensitive analog circuitry.
If the AD9886 is interfacing with lower-
voltage logic, VDD may be connected to a
lower supply voltage (as low as 2.5 V) for
compatibility.
PVDClock Generator Power Supply
The most sensitive portion of the AD9886 is
the clock generation circuitry. These pins
provide power to the clock PLL and help the
user design for optimal performance. The
designer should provide “quiet,” noise-free
power to these pins.
GNDGround
The ground return for all circuitry on chip.
It is recommended that the AD9886 be
assembled on a single solid ground plane,
with careful attention to ground current paths.
Serial Port (Two-Wire)SDASerial Port Data I/O
SCLSerial Port Data ClockSerial Port Address Input 1Serial Port Address Input 2
For a full description of the 2-wire serial regis-
ter and how it works, refer to the Control
Register section.
SCAN FunctionSCANINData Input for SCAN Function
Data can be loaded serially into the 48-bit
SCAN register through this pin, clocking it in
with the SCANCLK pin. It then comes out of
the 48 data outputs in parallel. This function
is useful for loading known data into a graph-
ics controller chip for testing purposes.
SCANOUTData Output for SCAN Function
The data in the 48-bit SCAN register can be
read through this pin. Data is read on a FIFO
basis and is clocked via the SCANCLK pin.
SCANCLKData Clock for SCAN Function
This pin clocks the data through the SCAN
register. It controls both data input and
data output.
AD9886
DESIGN GUIDE
General DescriptionThe AD9886 is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel monitors
or projectors. The circuit is ideal for providing a computer
interface for HDTV monitors or as the front end to high-
performance video scan converters.
Implemented in a high-performance CMOS process, the inter-
face can capture signals with pixel rates of up to 140 MHz and
with an Alternate Pixel Sampling mode, up to 280 MHz.
The AD9886 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control,
and output data formatting. All controls are programmable via
a 2-wire serial interface. Full integration of these sensitive analog
functions makes system design straightforward and less sensi-
tive to the physical and electrical environment.
With a typical power dissipation of less than 750 mW and an
operating temperature range of 0°C to 70°C, the device requires
no special environmental considerations.
Input Signal HandlingThe AD9886 has three high-impedance analog input pins for
the Red, Green, and Blue channels. They will accommodate
signals ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-pin D connector, or via BNC connectors.
The AD9886 should be located as close as practical to the
input connector. Signals should be routed via matched-imped-
ance traces (normally 75 Ω) to the IC input pins.
At that point the signal should be resistively terminated (75 Ω
to the signal ground return) and capacitively coupled to the
AD9886 inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal
bandwidth. The ultrawide bandwidth inputs of the AD9886
(330 MHz) can track the input signal continuously as it moves
from one pixel level to the next, and digitize the pixel during a
long, flat pixel time. In many systems, however, there are mis-
matches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. It has been shown that a small inductor in series
with the input is effective in rolling off the input bandwidth
slightly, and providing a high quality signal over a wider range
of conditions. Using a Fair-Rite #2508051217Z0 High-Speed
Signal Chip Bead inductor in the circuit of Figure 1 gives good
results in most applications.
HSYNC, VSYNC InputsThe AD9886 takes a horizontal sync signal, which is used to
generate the pixel clock and clamp timing. It is possible to oper-
ate the AD9886 without applying HSYNC (using an external
clock, external clamp, and single port output mode) but a number
of features of the chip will be unavailable, so it is recommended
that HSYNC be provided. This can be either a sync signal
directly from the graphics source, or a preprocessed TTL or
CMOS level signal.
The HSYNC input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no ter-
mination is required or desired.
Serial Control PortThe serial control port is designed for 3.3 V logic. If there are
5 V drivers on the bus, these pins should be protected with
150 Ω series resistors placed between the pull-up resistors and
the input pins.
Output Signal HandlingThe digital outputs are designed and specified to operate from a
3.3 V power supply (VDD). They can also work with a VDD as
low as 2.5 V for compatibility with other 2.5 V logic.
Clamping
RGB ClampingTo properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board A/D
converters.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground and black is at 300 mV. Then white is at approximately
1.0 V. Some common RGB line amplifier boxes use emitter-
follower buffers to split signals and increase drive capability.
This introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9886.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. An
offset is then introduced which results in the A/D converters
producing a black output (code 00h) when the known black
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to
eliminate offset errors.
In most graphics systems, black is transmitted between active
video lines. Going back to CRT displays, when the electron
beam has completed writing a horizontal line on the screen (at
the right side), the beam is quickly deflected to the left side of
the screen (called horizontal retrace) and a black signal is pro-
vided to prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(HSYNC) is produced briefly to signal the CRT that it is time
to begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of HSYNC. Fortunately, there is virtually
always a period following HSYNC called the back porch where
a good black reference is provided. This is the time when clamp-
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time (with EXTCLMP = 1).
The polarity of this signal is set by the Clamp Polarity bit.
A simpler method of clamp timing employs the AD9886 inter-
nal clamp timing generator. The Clamp Placement register is
programmed with the number of pixel times that should pass
after the trailing edge of HSYNC before clamping starts. A
second register (Clamp Duration) sets the duration of the
clamp. These are both 8-bit values, providing considerable
flexibility in clamp generation. The clamp timing is referenced
to the trailing edge of HSYNC because, although HSYNC
duration can vary widely, the back porch (black reference)
always follows HSYNC. A good starting point for establishing
clamping is to set the clamp placement to 08h (providing eight
pixel periods for the graphics signal to stabilize after sync) and
set the clamp duration to 14h (giving the clamp 20 pixel periods
to reestablish the black reference).
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capaci-
tor affects the performance of the clamp. If it is too small, there
will be a significant amplitude change during a horizontal line
time (between clamping intervals). If the capacitor is too large,
it will take excessively long for the clamp to recover from a large
change in incoming signal offset. The recommended value
(47 nF) results in recovering from a step error of 100 mV to
within 1/2 LSB in 10 lines with a clamp duration of 20 pixel
periods on a 60 Hz SXGA signal.
YUV ClampingYUV graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) can be at
the midpoint of the video signal rather than the bottom. For
these signals it can be necessary to clamp to the midscale range
of the A/D converter range (10h) rather than bottom of the A/D
converter range (00h).
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the series bus register. Each of
the three converters has its own selection bit so that they can be
clamped to either midscale or ground independently. These bits
are located in Register 0Fh and are Bits 0–2.
The midscale reference voltage that each A/D converter clamps
to is provided independently on the RMIDSCV, GMIDSCV, and
BMIDSCV pins. Each converter must have its own midscale refer-
ence because both offset adjustment and gain adjustment for
each converter will affect the dc level of midscale.
During clamping, each A/D converter is clamped to its respec-
tive midscale reference input. These inputs are pins RCLAMPV,
GCLAMPV, and BCLAMPV for the red, green, and blue converters
respectively. The typical connections for both RGB and YUV
clamping are shown below in Figure 2. Note: if midscale clamp-
ing is not required, all of the midscale voltage outputs should
still be connected to ground through a 0.1 µF capacitor.
Figure 2.Typical Clamp Configuration for RBG/YUV
Applications
Gain and Offset ControlThe AD9886 can accommodate input signals with inputs rang-
ing from 0.5 V to 1.0 V full scale. The full-scale range is set in
three 8-bit registers (Red Gain, Green Gain, and Blue Gain).
Note that increasing the gain setting results in an image with
less contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (Red Offset,
Green Offset, Blue Offset) provide independent settings for
each channel.
The offset controls provide a ±63 LSB adjustment range. This
range is connected with the full-scale range, so if the input range
is doubled (from 0.5 V to 1.0 V) then the offset step size is also
doubled (from 2 mV per step to 4 mV per step).
Figure 3 illustrates the interaction of gain and offset controls.
The magnitude of an LSB in offset adjustment is proportional
to the full-scale range, so changing the full-scale range also
changes the offset. The change is minimal if the offset setting is
near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same amount
as the zero-scale level.
Figure 3.Gain and Offset Control
AD9886
Sync-on-GreenThe Sync-on-Green input operates in two steps. First, it sets a
baseline clamp level from the incoming video signal with a
negative peak detector. Second, it sets the sync trigger level to
~150 mV above the negative peak. The Sync-on-Green input
must be ac-coupled to the green analog input through its own
capacitor as shown in Figure 4. The value of the capacitor must
be 1 nF ±20%. If Sync-on-Green is not used, this connection is
not required. (Note: The Sync-on-Green signal is always nega-
tive polarity.)
Figure 4. Typical Clamp Configuration for RGB/YUV
Applications
Clock GenerationA Phase Locked Loop (PLL) is employed to generate the pixel
clock. In this PLL, the Hsync input provides a reference fre-
quency. A Voltage Controlled Oscillator (VCO) generates a
much higher pixel clock frequency. This pixel clock is divided
by the PLL divide value (Registers 01H and 02H) and phase
compared with the Hsync input. Any error is used to shift the
VCO frequency and maintain lock between the two signals.
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,
there is a period during which the signal is slewing from the old
pixel amplitude and settling at its new value. Then there is a
time when the input voltage is stable, before the signal must
slew to a new value (see Figure 5). The ratio of the slewing time
to the stable time is a function of the bandwidth of the graphics
DAC and the bandwidth of the transmission system (cable and
termination). It is also a function of the overall pixel rate. Clearly,
if the dynamic characteristics of the system remain fixed, the
slewing and settling time is likewise fixed. This time must be
subtracted from the total pixel period, leaving the stable period.
At higher pixel frequencies, the total cycle time is shorter, and
the stable pixel time becomes shorter as well.
Figure 5.Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined, and must also be subtracted
from the stable pixel time.
Considerable care has been taken in the design of the AD9886’s
clock generation circuit to minimize jitter. As indicated in Fig-
ure 6, the clock jitter of the AD9886 is less than 5% of the total
pixel time in all operating modes, making the reduction in the
valid sampling time due to jitter negligible.
Figure 6.Pixel Clock Jitter vs. Frequency
The PLL characteristics are determined by the loop filter
design, by the PLL charge pump current and by the VCO range
setting. The loop filter design is illustrated in Figure 7. Recom-
mended settings of VCO range and charge pump current for
VESA standard display modes are listed in Table IV.
Figure 7.PLL Loop Filter Detail
Four programmable registers are provided to optimize the per-
formance of the PLL. These registers are:The 12-Bit Divisor Register. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock fre-
quencies in the range of 12 MHz to 140 MHz. The Divisor
Register controls the exact multiplication factor. This register
may be set to any value between 221 and 4095. (The divide
ratio that is actually used is the programmed divide ratio
plus one.)The 2-Bit VCO Range Register. To lower the sensitivity of
the output frequency to noise on the control signal, the VCO
operating frequency range is divided into four overlapping
regions. The VCO Range register sets this operating range.
Because there are only four possible regions, only the two
least-significant bits of the VCO Range register are used.
The frequency ranges for the lowest and highest regions
Table IV.Recommended VCO Range and Charge Pump Current Settings for Standard Display FormatsSVGA
XGA
SXGA
*Graphics sampled at one-half the incoming pixel rate using Alternate Pixel Sampling mode.
Table II.VCO Frequency RangesThe 3-Bit Charge Pump Current Register. This register
allows the current that drives the low pass loop filter to be
varied. The possible current values are listed in Table III.
Table III.Charge Pump Current/Control BitsThe 5-Bit Phase Adjust Register. The phase of the generated
sampling clock may be shifted to locate an optimum sam-
pling point within a clock cycle. The Phase Adjust register
provides 32 phase-shift steps of 11.25° each. The Hsync
signal with an identical phase shift is available through the
HSOUT pin. Phase adjustment is still available if the pixel
clock is being provided externally.
The COAST pin is used to allow the PLL to continue to run
at the same frequency, in the absence of the incoming Hsync
signal. This may be used during the vertical sync period, or
any other time that the Hsync signal is unavailable. The
polarity of the COAST signal may be set through the Coast
Polarity Register. Also, the polarity of the Hsync signal may
be set through the HSYNC Polarity Register. For both
HSYNC and COAST, a value of “1” inverts the signal.
AD9886Figure 8.ADC Block Diagram (Single Channel Output)
Figure 9.Relationship of Offset Range to Input Range
SCAN FunctionThe SCAN function is intended as a pseudo JTAG function for
manufacturing test for the board. The ordinary operation of the
AD9886 is disabled during SCAN.
To enable the SCAN function, set register 14h, bit 2 to 1. To
SCAN in data to all 48 digital outputs, apply 48 serial bits of
data and 48 clocks (typically 5MHz, max of 20MHz) to the
SCANIN and SCANCLK pins respectively. The data is shifted
in on the rising edge of SCANCLK. The first serial bit shifted
in will appear at the RED A<7> output after one clock cycle.
After 48 clocks, the first bit is shifted all the way to the BLU
B<0>. The 48th bit will now be at the RED A<7> output. If
SCANCLK continues after 48 cycles, the data will continue to be
shifted from RED A<7> to BLU B<0> and will come out of the
SCANOUT pin as serial data on the falling edge of SCANCLK.
This is illustrated in Figure 10. A setup time (Tsu) of 3ns
should be plenty and no hold time (Thold) is required (≥ 0ns).
This is illustrated in Figure 11.
Figure 11.SCAN Setup and Hold
Alternate Pixel Sampling ModeA Logic 1 input on Clock Invert (CKINV, Pin 94) inverts the
nominal ADC clock. CKINV can be switched between frames
to implement the alternate pixel sampling mode. This allows
higher effective image resolution to be achieved at lower pixel
rates but with lower frame rates.
Figure 12.Odd and Even Pixels in a Frame
On one frame, only even pixels are digitized. On the subsequent
frame, odd pixels are sampled. By reconstructing the entire
frame in the graphics controller, a complete image can be recon-
structed. This is very similar to the interlacing process that is
employed in broadcast television systems, but the interlacing is
vertical instead of horizontal. The frame data is still presented to
the display at the full desired refresh rate (usually 60 Hz) so no
flicker artifacts added.
Figure 13.Odd Pixels from Frame 1
Figure 14.Even Pixels from Frame 2
Figure 15.Combine Frame Output from Graphics Controller
Figure 16.Subsequent Frame from Controller
Timing (Analog Interface)The following timing diagrams show the operation of the
AD9886 analog interface in all clock modes. The part estab-
lishes timing by having the sample that corresponds to the pixel
digitized when the leading edge of HSYNC occurs sent to the
“A” data port. In Dual Channel Mode, the next sample is sent
to the “B” port. Future samples are alternated between the “A”
and “B” data ports. In Single Channel Mode, data is only sent
to the “A” data port, and the “B” port is placed in a high
impedance state.
The Output Data Clock signal is created so that its rising edge
always occurs between “A” data transitions, and can be used to
latch the output data externally.
There is a pipeline in the AD9886, which must be flushed before
valid data becomes available. In all single channel modes, four
data sets are presented before valid data is available. In all dual
channel modes, two data sets are presented before valid “A”
port data is available.
Figure 17.Output Timing
Hsync TimingHorizontal sync is processed in the AD9886 to eliminate
ambiguity in the timing of the leading edge with respect to the
phase-delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360° in 32 steps via the Phase Adjust
register (to optimize the pixel sampling time). Display systems use
Hsync to align memory and display write cycles, so it is important
to have a stable timing relationship between Hsync output
(HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9886. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be pro-
grammed either active high or active low (Register 04H, Bit 4).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via Regis-
ter 07H. HSOUT is the sync signal that should be used to drive
the rest of the display system.
Coast TimingIn most computer systems, the Hsync signal is provided con-
tinuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary, and should not be used.
In some systems, however, Hsync is disturbed during the Verti-
cal Sync period (Vsync). In some cases, Hsync pulses disappear.
In other systems, such as those that employ Composite Sync
(Csync) signals or embed Sync-On-Green (SOG), Hsync includes
equalization pulses or other distortions during Vsync. To avoid
upsetting the clock generator during Vsync, it is important to
ignore these distortions. If the pixel clock PLL sees extraneous
pulses, it will attempt to lock to this new frequency, and will
have changed frequency by the end of the Vsync period. It will
then take a few lines of correct Hsync timing to recover at the
beginning of a new frame, resulting in a “tearing” of the image
at the top of the display.
The COAST input is provided to eliminate this problem. It is
an asynchronous input that disables the PLL input and allows
the clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
AD9886Figure 18.Single-Channel Mode
Figure 19.Single-Channel Mode, 2 Pixels/Clock (Even Pixels)
Figure 20.Single-Channel Mode, 2 Pixels/Clock (Odd Pixels)
