AD9884 ,Triple 8-Bit, 140 MSPS ADC, RGB Graphics Digitizer for SXGA LCD MonitorsSPECIFICATIONSTest AD9884AKS-100 AD9884AKS-140Parameter Temp Level Min Typ Max Min Typ Max UnitRESO ..
AD9884A ,100 MSPS/140 MSPS Analog Flat Panel InterfaceCHARACTERISTICSq –Junction-to-CaseJCThermal Resistance V 8.4 8.4
AD9884
Triple 8-Bit, 140 MSPS ADC, RGB Graphics Digitizer for SXGA LCD Monitors
REV. C
100 MSPS/140 MSPS
Analog Flat Panel Interface
GENERAL DESCRIPTIONThe AD9884A is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full-power analog bandwidth of 500 MHz
supports display resolutions of up to 1280 × 1024 (SXGA) atHz with sufficient input bandwidth to accurately acquire and
digitize each pixel.
To minimize system cost and power dissipation, the AD9884A
includes an internal 1.25 V reference, PLL to generate a pixel
clock from HSYNC, and programmable gain, offset and clamp
circuits. The user provides only a 3.3 V power supply, analog
input, and HSYNC signals. Three-state CMOS outputs may be
powered by a supply between 2.5 V and 3.3 V.
The AD9884A’s on-chip PLL generates a pixel clock from the
HSYNC input. Pixel clock output frequencies range from
FEATURES
140 MSPS Maximum Conversion Rate
500 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
400 ps p-p PLL Clock Jitter
Power-Down Mode
3.3 V Power Supply
2.5 V to 3.3 V Three-State CMOS Outputs
Demultiplexed Output Ports
Data Clock Output Provided
Low Power: 570 mW Typical
Internal PLL Generates CLOCK from HSYNC
Serial Port Interface
Fully Programmable
Supports Alternate Pixel Sampling for Higher-
Resolution Applications
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
FUNCTIONAL BLOCK DIAGRAMMHz to 140 MHz. PLL clock jitter is typically 400ps p-p
relative to the input reference. When the COAST signal is pre-
sented, the PLL maintains its output frequency in the absence
of HSYNC. A 32-step sampling phase adjustment is provided.
Data, HSYNC and Data Clock output phase relationships are
always maintained. The PLL can be disabled and an external
clock input provided as the pixel clock.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This device is fully program-
mable via a two-wire serial port.
Fabricated in an advanced CMOS process, the AD9884A is
provided in a space-saving 128-lead MQFP surface mount plastic
package and is specified over a 0°C to +70°C temperature range.
AD9884A–SPECIFICATIONS
(VD = 3.3 V, VDD = 3.3 V, PVD = 3.3 V, ADC Clock Frequency = Maximum, PLL
Clock Frequency = Maximum, Control Registers Programmed to Default State)SWITCHING PERFORMANCE
AD9884ANOTESVCORNGE = 01, CURRENT = 001, PLLDIV = 169310.VCORNGE = 10, CURRENT = 110, PLLDIV = 160010.DEMUX = 1; DATACK and DATACK load = 15 pF; Data load = 5 pF.Using external pixel clock.
Specifications subject to change without notice.
ORDERING GUIDEAD9884AKS-100
EXPLANATION OF TEST LEVELS
Test Level100% production tested.
II.100% production tested at 25°C and sample tested at specified
temperatures.
III.Sample tested only.
IV.Parameter is guaranteed by design and characterization testing.Parameter is a typical value only.
VI.100% production tested at 25°C; guaranteed by design and
characterization testing.
ABSOLUTE MAXIMUM RATINGS*VD, PVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4 V
PVD to VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to –0.5 V
REFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . –20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9884A features proprietary ESD protection circuitry, permanent damage may
AD9884A
Table I.Package Interconnections
PIN CONFIGURATION
REFINREFOUTPWRDN
GNDGNDGNDV
GNDSOGOUTHSOUTDATACKDATACKV
GNDD
HSYNCCOAST
GND
CKEXT
FILT
GND
GND
GNDGNDGND
DRB0
DRB1
DRB2
DRB3
DRB4
DRB5
DRB6
DRB7
VDD
GND
DGA0
DGA1
DGA2
DGB2
DGB3
DGB4
DGB5
DGB6
DGB7
VDD
GND
GND
GND
RAIN
GND
GND
GND
SOGIN
GAIN
GND
GND
GND
BAIN
GND
GND
CKINV
CLAMP
SDA
SCL
GND
GND
DBA0
DBA1
GND
DGA3
DGA4
DGA5
DGA6
DGA7
VDD
GND
DGB0
DGB1
PVD
PVD
GND
DBA2
DBA3
DBA4
DBA5
DBA6
DBA7
NC = NO CONNECT
AD9884A
PIN FUNCTION DESCRIPTIONSGAIN
BAIN
HSYNC
COAST
CLAMP
SOGIN
CKEXT
CKINV
PIN FUNCTION DESCRIPTIONS (continued)
AD9884A
PIN FUNCTION DESCRIPTIONS (continued)
ANALOG INTERFACEREFOUTInternal Reference Output
Output from the internal 1.25 V bandgap reference. This output is intended to drive relatively light loads. It can
drive the AD9884A Reference input directly, but should be externally buffered if it is used to drive other loads as
well. The absolute accuracy of this output is ±4%, and the temperature coefficient is ±50 ppm, which is adequate
for most AD9884A applications. If higher accuracy is required, an external reference may be employed. If an exter-
nal reference is used, tie this pin to ground through a 0.1µF capacitor.
REFINReference Input
The reference input accepts the master reference voltage for all AD9884A internal circuitry (+1.25 V ± 10%). It
may be driven directly by the REFOUT pin. Its high impedance presents a very light load to the reference source.
This pin should be bypassed to Ground with a 0.1µF capacitor.
FILTExternal Filter Connection
For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure
10 to this pin. For optimal performance, minimize noise and parasitics on this node.
POWER SUPPLY
Table III.Default Register Values
CONTROL REGISTER DETAIL
PLL DIVIDER CONTROLThe eight most significant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
The PLL derives a master clock from an incoming HSYNC signal.
The master clock frequency is then divided by an integer value,
and the divider’s output is phase-locked to HSYNC. This PLLDIV
value determines the number of pixel times (pixels plus horizontal
blanking overhead) per line. This is typically 20% to 30% more
than the number of active pixels in the display.
The 12-bit value of PLLDIV supports divide ratios from 2 to 4095.
The higher the value loaded in this register, the higher the resulting
clock frequency with respect to a fixed HSYNC frequency.
VESA has established some standard timing specifications, which
will assist in determining the value for PLLDIV as a function of
horizontal and vertical display resolution and frame rate (Table
VII). However, many computer systems do not conform precisely
to the recommendations, and these numbers should be used only
as a guide. The display system manufacturer should provide auto-
matic or manual means for optimizing PLLDIV. An incorrectly set
PLLDIV will usually produce one or more vertical noise bars on
the display. The greater the error, the greater the number of bars
produced.
The power-up default value of PLLDIV is 1693 (PLLDIVM =
69h, PLLDIVL = Dxh).
The four least significant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693 (PLLDIVM =
69h, PLLDIVL = Dxh).
CONTROL REGISTER MAPThe AD9884A is initialized and controlled by a set of registers
that determine the operating modes. An external controller is
employed to write and read the control registers through the
2-line serial interface port.
Table II.Control Register Map
Clock Generator ControlAD9884A
INPUT GAINAn 8-bit word that sets the gain of the RED channel. The
AD9884A can accommodate input signals with a full-scale
range of between 0.5 V and 1.0 V p-p. Setting REDGAIN to
255 corresponds to an input range of 1.0 V. A REDGAIN of
0 establishes an input range of 0.5 V. Note that increasing
REDGAIN results in the picture having less contrast (the
input signal uses fewer of the available converter codes). See
Figure 8.
The power-up default value is REDGAIN = 80h.
An 8-bit word that sets the gain of the GREEN channel. See
REDGAIN (02).
The power-up default value is GRNGAIN = 80h.
An 8-bit word that sets the gain of the BLUE channel. See
REDGAIN (02).
The power-up default value is BLUGAIN = 80h.
INPUT OFFSETA six-bit offset binary word that sets the dc offset of the RED
channel.
One LSB of offset adjustment equals approximately one LSB
change in the ADC offset. Therefore, the absolute magnitude of
the offset adjustment scales as the gain of the channel is changed
(Figure 9). A nominal setting of 31 results in the channel nomi-
nally clamping the back porch (during the clamping interval) to
code 00. An offset setting of 63 results in the channel clamping
to code 31 of the ADC. An offset setting of 0 clamps to code
–31 (off the bottom of the range). Increasing the value of
REDOFST decreases the brightness of the channel.
The power-up default value is REDOFST = 80h.
A six-bit offset binary word that sets the dc offset of the GREEN
channel. See REDOFST (05).
The power-up default value is GRNOFST = 80h.
A six-bit offset binary word that sets the DC offset of the GREEN
channel. See REDOFST (05).
The power-up default value is BLUOFST = 80h.
CLAMP TIMINGAn 8-bit register that sets the position of the internally generated clamp.
When EXTCLMP = 0, a clamp signal is generated internally, at
a position established by CLPLACE and for a duration set by
CLDUR. Clamping is started CLPLACE pixel periods after the
trailing edge of HSYNC. CLPLACE may be programmed to
any value between 1 and 255. CLPLACE = 0 is not supported.
The clamp should be placed during a time that the input signal
presents a stable black-level reference, usually the back porch
period between HSYNC and the image. A value of 08h will
usually work.
When EXTCLMP = 1, this register is ignored.
The power-up default value is CLPLACE = 80h.
An 8-bit register that sets the duration of the internally gener-
ated clamp.
When EXTCLMP = 0, a clamp signal is generated internally, at
a position established by CLPLACE and for a duration set by
CLDUR. Clamping is started CLPLACE pixel periods after the
trailing edge of HSYNC, and continues for CLDUR pixel peri-
ods. CLDUR may be programmed to any value between 1 and
255. CLDUR = 0 is not supported.
For the best results, the clamp duration should be set to include
the majority of the black reference signal time found following
the HSYNC signal trailing edge. Insufficient clamping time can
produce brightness changes at the top of the screen, and a slow
recovery from large changes in the Average Picture Level (APL), or
brightness. A value of 10h to 20h works with most standard signals.
When EXTCLMP = 1, this register is ignored.
The power-up default value is CLDUR = 80h.
GENERAL CONTROLA bit that determines whether all pixels are presented to a single
port (A), or alternating pixels are demultiplexed to Ports A and B.
When DEMUX = 0, Port B outputs are in a highimpedance state.
The power-up default value is DEMUX = 1.
Setting this bit to a Logic 1 delays data on Port A and the
DATACK output by one-half DATACK period so that the
rising edge of DATACK may be used to externally latch data
from both Port A and Port B. When this bit is set to a Logic 0,
the rising edge of DATACK may be used to externally latch
data from Port A only, and the DATACK rising edge may be
used to externally latch data from Port B.
When in single port mode (DEMUX = 0), this bit is ignored.
The power-up default value is PARALLEL = 1.
A bit that must be set to indicate the polarity of the HSYNC
signal that is applied to the HSYNC input.
Active LOW is the traditional negative-going HSYNC pulse.
Sampling timing is based on the leading edge of HSYNC, which
is the FALLING edge. The Clamp Position, as determined by
CLPLACE, is measured from the trailing edge.
Active HIGH is inverted from the traditional HSYNC, with a
positive-going pulse. This means that sampling timing will be
based on the leading edge of HSYNC, which is now the RISING
edge, and clamp placement will count from the FALLING edge.
The device will operate more-or-less properly if this bit is set
incorrectly, but the internally generated clamp position, as
established by CLPOS, will not be placed as expected, which
may generate clamping errors.
The power-up default value is HSPOL = 1.
A bit that must be set to indicate the polarity of the COAST
signal that is applied to the COAST input.
Active LOW means that the clock generator will ignore HSYNC
inputs when COAST is LOW, and continue operating at the
same nominal frequency until COAST goes HIGH.
Active HIGH means that the clock generator will ignore HSYNC
inputs when COAST is HIGH, and continue operating at the
same nominal frequency until COAST goes LOW.
The power-up default value is CSTPOL = 1.
A bit that determines the source of clamp timing.
A 0 enables the clamp timing circuitry controlled by CLPLACE
and CLDUR. The clamp position and duration is counted from
the trailing edge of HSYNC.
A 1 enables the external CLAMP input pin. The three channels
are clamped when the CLAMP signal is active. The polarity of
CLAMP is determined by the CLAMPOL bit.
The power-up default value is EXTCLMP = 0.
A bit that determines the polarity of the externally provided
CLAMP signal.
A 0 means that the circuit will clamp when CLAMP is LOW,
and it will pass the signal to the ADC when CLAMP is HIGH.
A 1 means that the circuit will clamp when CLAMP is HIGH,
and it will pass the signal to the ADC when CLAMP is LOW.
The power-up default value is CLAMPOL = 1.
A bit that determines the source of the pixel clock.
A 0 enables the internal PLL that generates the pixel clock from
an externally-provided HSYNC.
A 1 enables the external CKEXT input pin. In this mode, the
PLL Divide Ratio (PLLDIV) is ignored. The clock phase adjust
(PHASE) is still functional.
AD9884A
CLOCK GENERATOR CONTROLA five-bit value that adjusts the sampling phase in 32 steps across
one pixel time. Each step represents an 11.25 degree shift in
sampling phase.
The power-up default value is PHASE = 16.
Two bits that establish the operating range of the clock generator.
VCORNGE must be set to correspond with the desired operat-
ing frequency (incoming pixel rate).
The power-up default value is VCORNGE = 01.
Three bits that establish the current driving the loop filter in the
clock generator.
CURRENT must be set to correspond with the desired operat-
ing frequency (incoming pixel rate).
The power-up default value is CURRENT = 001.
One bit that determines whether even pixels or odd pixels go to
Port A.
In normal operation (OUTPHASE = 0), when operating in
Dual Channel output mode (DEMUX = 1), the first sample
after the HSYNC leading edge is presented at Port A. Every
subsequent ODD sample appears at Port A. All EVEN samples
go to Port B.
When OUTPHASE = 1, these ports are reversed and the first
sample goes to Port B.
The die revision of the AD9884A can be determined by reading
these three bits.
Serial Control PortA 2-wire serial control interface is provided. Up to four AD9884A
devices may be connected to the 2-wire serial interface, with
each device having a unique address.
The 2-wire interface comprises a clock (SCL) and a bidirec-
tional data (SDA) pin. The Analog Flat Panel Interface acts as a
slave for receiving and transmitting data over the serial interface.
When the serial interface is not active, the logic levels on SCL
and SDA are pulled HIGH by external pull-up resistors.
Data received or transmitted on the SDA line must be stable for
the duration of the positive-going SCL pulse. Data on SDA
must change only when SCL is LOW. If SDA changes state
while SCL is HIGH, the serial interface interprets that action as
a start or stop sequence.
There are six components to serial bus operation:Start SignalSlave Address ByteBase Register Address ByteData Byte to Read or WriteStop Signal
When the serial interface is inactive (SCL and SDA are HIGH)
communications are initiated by sending a start signal. The start
signal is a HIGH-to-LOW transition on SDA while SCL is
HIGH. This signal alerts all slaved devices that a data transfer
sequence is coming.
The first eight bits of data transferred after a start signal com-
prising a seven bit slave address (the first seven bits) and a
single R/W bit (the eighth bit). The R/W bit indicates the direc-
tion of data transfer, read from (1) or write to (0) the slave
device. If the transmitted slave address matches the address of
the device (set by the state of the SA1-0 input pins in Table IV),
the AD9884A acknowledges by bringing SDA LOW on the
ninth SCL pulse. If the addresses do not match, the AD9884A
does not acknowledge.
Table IV.Serial Port Addresses
Data Transfer via Serial InterfaceFor each byte of data read or written, the MSB is the first bit of
the sequence.
If the AD9884A does not acknowledge the master device during
a write sequence, the SDA remains HIGH so the master can
generate a stop signal. If the master device does not acknowl-
