AD9883AKSTZ-110 ,Highly Integrated Graphics Interface Chip Includes Three 8-Bit/110 MSPS ADCsGENERAL DESCRIPTION140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.The AD9883A is a com ..
AD9883KST-110 ,110 MSPS Analog Interface for Flat Panel DisplaysSPECIFICATIONSAnalog Interface (V = 3.3 V, V = 3.3 V, ADC Clock = Maximum Conversion Rate)D DDTest ..
AD9884 ,Triple 8-Bit, 140 MSPS ADC, RGB Graphics Digitizer for SXGA LCD MonitorsSPECIFICATIONSTest AD9884AKS-100 AD9884AKS-140Parameter Temp Level Min Typ Max Min Typ Max UnitRESO ..
AD9884A ,100 MSPS/140 MSPS Analog Flat Panel InterfaceCHARACTERISTICSq –Junction-to-CaseJCThermal Resistance V 8.4 8.4
AD9883ABSTZ-110-AD9883AKSTZ-110
Highly Integrated Graphics Interface Chip Includes Three 8-Bit/110 MSPS ADCs
REV. B
110 MSPS/140 MSPS Analog Interface
for Flat Panel Displays
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Industrial Temperature Range Operation
140 MSPS Maximum Conversion Rate
300 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 110 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for Hot Plugging
Midscale Clamping
Power-Down Mode
Low Power:500 mW Typical
4:2:2 Output Format Mode
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TV
GENERAL DESCRIPTIONThe AD9883A is a complete 8-bit, 140 MSPS, monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280 × 1024 at 75 Hz).
The AD9883A includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and Hsync and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883A’s on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz to
140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9883A also offers full sync
processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883A is pro-
vided in a space-saving 80-lead LQFP surface-mount plastic package
and is specified over the –40°C to +85°C temperature range.
AD9883A–SPECIFICATIONSSWITCHING PERFORMANCE
DIGITAL INPUTS
Analog Interface(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate, unless otherwise noted.)
AD9883ANOTESVCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693.DATACK Load = 15 pF, Data Load = 5 pF.
Specifications subject to change without notice.
AD9883ADIGITAL INPUTS
Analog Interface(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate, unless otherwise noted.)
NOTESVCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693.DATACK Load = 15 pF, Data Load = 5 pF.
Specifications subject to change without notice.
AD9883A
ABSOLUTE MAXIMUM RATINGS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
EXPLANATION OF TEST LEVELS
Test Level100% production tested.
II.100% production tested at 25°C and sample tested at
specified temperatures.
III.Sample tested only.
IV.Parameter is guaranteed by design and characterization testing.Parameter is a typical value only.
VI.100% production tested at 25°C; guaranteed by design and
characterization testing.
ORDERING GUIDE*Lead-free product
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9883A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
GND
GREEN <7>
GREEN <6>
GREEN <5>
GREEN <4>
GREEN <3>
GREEN <2>
GREEN <1>
GREEN <0>
GND
VDD
BLUE <7>
BLUE <6>
BLUE <5>
BLUE <4>
BLUE <3>
BLUE <2>
BLUE <1>
BLUE <0>
GND
GND
GND
GND
GND
GND
GND
REF BYPASS
SDA
SCL
RAIN
GAIN
BAIN
SOGIN
GND
RED <0>
RED <1>
RED <2>RED <3>RED <4>
RED <5>
RED <6>RED <7>V
GND
HSOUTSOGOUTGNDV
GNDVSOUT
GND
GNDGND
GND
MIDSCV
CLAMP
GND
AST
HSYNC
VSYNC
GND
FIL
GND
Table I. Complete Pinout List
AD9883A
PIN FUNCTION DESCRIPTIONSSERIAL PORT (2-Wire)
DATA OUTPUTS
DATA CLOCK OUTPUT
INPUTS
DESIGN GUIDE
General DescriptionThe AD9883A is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel monitors
or projectors. The circuit is ideal for providing a computer interface
for HDTV monitors or as the front end to high performance video
scan converters. Implemented in a high performance CMOS
process, the interface can capture signals with pixel rates up
to 110 MHz.
The AD9883A includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
With a typical power dissipation of only 500 mW and an operating
temperature range of 0°C to 70°C, the device requires no special
environmental considerations.
Digital InputsAll digital inputs on the AD9883A operate to 3.3 V CMOS levels.
However, all digital inputs are 5 V tolerant. Applying 5 V to
them will not cause any damage.
Input Signal HandlingThe AD9883A has three high impedance analog input pins
for the Red, Green, and Blue channels. They will accommodate
signals ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a
PIN FUNCTION DESCRIPTIONS (continued)POWER SUPPLYMain Power Supply
These pins supply power to the main elements of the circuit. They should be filtered and as quiet as possible.
VDDDigital Output Power Supply
A large number of output pins (up to 25) switching at high speed (up to 110 MHz) generates a lot of power supply transients
(noise). These supply pins are identified separately from the VD pins so special care can be taken to minimize output
noise transferred into the sensitive analog circuitry. If the AD9883A is interfacing with lower voltage logic, VDD may be
connected to a lower supply voltage (as low as 2.5 V) for compatibility.
PVDClock Generator Power Supply
The most sensitive portion of the AD9883A is the clock generation circuitry. These pins provide power to the clock PLL and
help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.
GNDGround
The ground return for all circuitry on-chip. It is recommended that the AD9883A be assembled on a single solid ground
plane, with careful attention given to ground current paths.
AD9883AAt that point the signal should be resistively terminated (75 Ω
to the signal ground return) and capacitively coupled to the
AD9883A inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best perfor-
mance can be obtained with the widest possible signal bandwidth.
The ultrawide bandwidth inputs of the AD9883A (300 MHz)
can track the input signal continuously as it moves from one pixel
level to the next, and digitize the pixel during a long, flat pixel
time. In many systems, however, there are mismatches, reflections,
and noise, which can result in excessive ringing and distortion of
the input waveform. This makes it more difficult to establish a
sampling phase that provides good image quality. It has been
shown that a small inductor in series with the input is effective in
rolling off the input bandwidth slightly and providing a high
quality signal over a wider range of conditions. Using a Fair-
Rite #2508051217Z0 High Speed Signal Chip Bead inductor
in the circuit of Figure 1 gives good results in most applications.
Figure 1. Analog Input Interface Circuit
Hsync, Vsync InputsThe interface also takes a horizontal sync signal, which is used
to generate the pixel clock and clamp timing. This can be either
a sync signal directly from the graphics source, or a preprocessed
TTL or CMOS level signal.
The Hsync input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no ter-
mination is required.
Serial Control PortThe serial control port is designed for 3.3 V logic. If there are 5 V
drivers on the bus, these pins should be protected with 150 Ω series
resistors placed between the pull-up resistors and the input pins.
Output Signal HandlingThe digital outputs are designed and specified to operate from a
3.3 V power supply (VDD). They can also work with a VDD as
low as 2.5 V for compatibility with other 2.5 V logic.
Clamping
RGB ClampingTo properly digitize the incoming signal, the dc offset of the input
must be adjusted to fit the range of the on-board A/D converters.
Most graphics systems produce RGB signals with black at ground
and white at approximately 0.75 V. However, if sync signals
are embedded in the graphics, the sync tip is often at ground
and black is at 300 mV. Then white is at approximately 1.0 V.
Some common RGB line amplifier boxes use emitter-follower
buffers to split signals and increase drive capability. This intro-
duces a 700 mV dc offset to the signal, which must be removed
for proper capture by the AD9883A.
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to elimi-
nate offset errors.
In most PC graphics systems, black is transmitted between
active video lines. With CRT displays, when the electron beam
has completed writing a horizontal line on the screen (at the
right side), the beam is deflected quickly to the left side of the
screen (called horizontal retrace) and a black signal is provided
to prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of Hsync. Fortunately, there is virtually
always a period following Hsync, called the back porch, where a
good black reference is provided. This is the time when clamp-
ing should be done.
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time (with External Clamp = 1).
The polarity of this signal is set by the Clamp Polarity bit.
A simpler method of clamp timing employs the AD9883A internal
clamp timing generator. The Clamp Placement register is pro-
grammed with the number of pixel times that should pass after
the trailing edge of HSYNC before clamping starts. A second
register (Clamp Duration) sets the duration of the clamp. These
are both 8-bit values, providing considerable flexibility in clamp
generation. The clamp timing is referenced to the trailing edge
of Hsync because, though Hsync duration can vary widely, the
back porch (black reference) always follows Hsync. A good
starting point for establishing clamping is to set the clamp place-
ment to 09H (providing 9 pixel periods for the graphics signal to
stabilize after sync) and set the clamp duration to 14H (giving
the clamp 20 pixel periods to reestablish the black reference).
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capaci-
tor affects the performance of the clamp. If it is too small, there
will be a significant amplitude change during a horizontal line
time (between clamping intervals). If the capacitor is too large,
then it will take excessively long for the clamp to recover from a
large change in incoming signal offset. The recommended value
(47 nF) results in recovering from a step error of 100 mV to
within 1/2 LSB in 10 lines with a clamp duration of 20 pixel
periods on a 60 Hz SXGA signal.
YUV ClampingYUV graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) can be at
the midpoint of the graphics signal rather than at the bottom.
For these signals, it can be necessary to clamp to the midscale
range of the A/D converter range (80H) rather than at the bottom
of the A/D converter range (00H).
Clamping to midscale rather than to ground can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
clamped to either midscale or ground independently. These
bits are located in register 10H and are Bits 0–2. The midscale
reference voltage that each A/D converter clamps to is provided
Figure 2. Gain and Offset Control
Gain and Offset ControlThe AD9883A can accommodate input signals with inputs
ranging from 0.5 V to 1.0 V full scale. The full-scale range is set
in three 8-bit registers (Red Gain, Green Gain, and Blue Gain).
Note that increasing the gain setting results in an image with
less contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (Red Offset,
Green Offset, Blue Offset) provide independent settings for
each channel. The offset controls provide a ±63 LSB adjust-
ment range. This range is connected with the full-scale range, so
if the input range is doubled (from 0.5 V to 1.0 V) then the offset
step size is also doubled (from 2 mV per step to 4 mV per step).
Figure 2 illustrates the interaction of gain and offset controls.
The magnitude of an LSB in offset adjustment is proportional
to the full-scale range, so changing the full-scale range also
changes the offset. The change is minimal if the offset setting is
near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same amount
as the zero scale level.
Sync-on-GreenThe Sync-on-Green input operates in two steps. First, it sets a
baseline clamp level off of the incoming video signal with a
negative peak detector. Second, it sets the sync trigger level to a
programmable level (typically 150 mV) above the negative peak.
The Sync-on-Green input must be ac-coupled to the Green
analog input through its own capacitor, as shown in Figure 3.
The value of the capacitor must be 1 nF ± 20%. If Sync-on-Green
is not used, this connection is not required. Note that the Sync-
on-Green signal is always negative polarity.
Figure 3. Typical Clamp Configuration
Clock GenerationA phase locked loop (PLL) is employed to generate the pixel
clock. In this PLL, the Hsync input provides a reference fre-
quency. A voltage controlled oscillator (VCO) generates a much
higher pixel clock frequency. This pixel clock is divided by the
PLL divide value (registers 01H and 02H) and phase compared
with the Hsync input. Any error is used to shift the VCO fre-
quency and maintain lock between the two signals.
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,
there is a period during which the signal is slewing from the old
pixel amplitude and settling at its new value. Then there is a
time when the input voltage is stable, before the signal must
slew to a new value (Figure 4). The ratio of the slewing time to
the stable time is a function of the bandwidth of the graphics
DAC and the bandwidth of the transmission system (cable and
termination). It is also a function of the overall pixel rate. Clearly,
if the dynamic characteristics of the system remain fixed, the
slewing and settling time is likewise fixed. This time must be
subtracted from the total pixel period, leaving the stable period.
At higher pixel frequencies, the total cycle time is shorter, and the
stable pixel time becomes shorter as well.
Figure 4. Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined, and must also be subtracted
from the stable pixel time.
Considerable care has been taken in the design of the AD9883A’s
clock generation circuit to minimize jitter. As indicated in
Figure 5, the clock jitter of the AD9883A is less than 5% of the
total pixel time in all operating modes, making the reduction in
the valid sampling time due to jitter negligible.
AD9883AThe PLL characteristics are determined by the loop filter design, by
the PLL Charge Pump Current, and by the VCO range setting.
The loop filter design is illustrated in Figure 6. Recommended
settings of VCO range and charge pump current for VESA
standard display modes are listed in Table V.
Figure 6. PLL Loop Filter Detail
Four programmable registers are provided to optimize the per-
formance of the PLL. These registers are:The 12-Bit Divisor Register. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock
frequencies in the range of 12 MHz to 110 MHz. The
Divisor Register controls the exact multiplication factor.
This register may be set to any value between 221 and 4095.
(The divide ratio that is actually used is the programmed
divide ratio plus one.)The 2-Bit VCO Range Register. To improve the noise
performance of the AD9883A, the VCO operating frequency
range is divided into three overlapping regions. The VCO
Range Register sets this operating range. The frequency
ranges for the lowest and highest regions are shown in Table II.
Table II. VCO Frequency RangesThe 3-Bit Charge Pump Current Register. This register
allows the current that drives the low-pass loop filter to be
varied. The possible current values are listed in Table III.
Table III. Charge Pump Current/Control BitsThe 5-Bit Phase Adjust Register. The phase of the generated
sampling clock may be shifted to locate an optimum sampling
point within a clock cycle. The Phase Adjust Register provides
32 phase-shift steps of 11.25° each. The Hsync signal with
an identical phase shift is available through the HSOUT pin.
The COAST pin is used to allow the PLL to continue to run
at the same frequency, in the absence of the incoming Hsync
signal or during disturbances in Hsync (such as equalization
pulses). This may be used during the vertical sync period, or
any other time that the Hsync signal is unavailable. The
polarity of the COAST signal may be set through the Coast
Polarity Register. Also, the polarity of the Hsync signal
may be set through the Hsync Polarity Register. If not
using automatic polarity detection, the Hsync and COAST
Polarity bits should be set to match the respective polarities
of the input signals.
Power ManagementThe AD9883A uses the activity detect circuits, the active inter-
face bits in the serial bus, the active interface override bits, and
the power-down bit to determine the correct power state. There
are three power states, full-power, seek mode, and power-down.
Table IV summarizes how the AD9883A determines what power
mode to be in and which circuitry is powered on/off in each of
these modes. The power-down command has priority over the
automatic circuitry.
Table IV. Power-Down Mode DescriptionsNOTESPower-down is controlled via Bit 1 in serial bus register 0FH.Sync detect is determined by OR-ing Bits 7, 4, and 1 in serial bus register 14H.
Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display FormatsSVGA
XGA
SXGA
TimingThe following timing diagrams show the operation of the
AD9883A.
The output data clock signal is created so that its rising edge
always occurs between data transitions, and can be used to latch
the output data externally.
There is a pipeline in the AD9883A, which must be flushed
before valid data becomes available. This means four data sets
are presented before valid data is available.
Figure 7. Output Timing
Hsync TimingHorizontal Sync (Hsync) is processed in the AD9883A to elimi-
nate ambiguity in the timing of the leading edge with respect to
the phase-delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360° in 32 steps via the Phase Adjust
Register (to optimize the pixel sampling time). Display systems
use Hsync to align memory and display write cycles, so it is
important to have a stable timing relationship between Hsync
output (HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9883A. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be pro-
grammed either active high or active low (register 0EH, Bit 5).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via regis-
ter 07H. HSOUT is the sync signal that should be used to drive
the rest of the display system.
Coast TimingIn most computer systems, the Hsync signal is provided con-
tinuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary, and should not be used and
the pin should be permanently connected to the inactive state.
In some systems, however, Hsync is disturbed during the Vertical
Sync period (Vsync). In some cases, Hsync pulses disappear.
In other systems, such as those that employ Composite Sync
(Csync) signals or embedded Sync-on-Green (SOG), Hsync
includes equalization pulses or other distortions during Vsync. To
avoid upsetting the clock generator during Vsync, it is impor-
tant to ignore these distortions. If the pixel clock PLL sees
extraneous pulses, it will attempt to lock to this new frequency,
and will have changed frequency by the end of the Vsync period.
It will then take a few lines of correct Hsync timing to recover
at the beginning of a new frame, resulting in a “tearing” of the
image at the top of the display.
The COAST input is provided to eliminate this problem. It is
an asynchronous input that disables the PLL input and allows
the clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
AD9883AFigure 8. 4:4:4 Mode (For RGB and YUV)
Figure 9. 4:2:2 Mode (For YUV Only)
