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ADSP-21061LKSZ-160 , Commercial Grade SHARC DSP Microcomputer
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ADSP-21062CS-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyFEATURES Butterfly Computation40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction2 Mbit On-Ch ..
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ADSP-21062CSZ-160 , SHARC Processor
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AD9882KST-100-AD9882KST-140
Dual Interface for Flat Panel Displays
REV.A
Dual Interface for
Flat Panel Displays
FEATURES
Analog Interface
140 MSPS Maximum Conversion Rate
Programmable Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamping
4:2:2 Output Format Mode
Digital Interface
DVI 1.0 Compatible Interface
112 MHz Operation
High Skew Tolerance of 1 Full Input Clock
Sync Detect for “Hot Plugging”
Supports High Bandwidth Digital Content Protection
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converter
Microdisplays
Digital TV
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD9882 offers designers the flexibility of an analog interface
and Digital Visual Interface (DVI) receiver integrated on a single
chip. Also included is support for High bandwidth Digital
Content Protection (HDCP).
Analog InterfaceThe AD9882 is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280 ¥ 1024 at 75 Hz).
The analog interface includes a 140 MHz triple ADC with
internal 1.25 V reference, a Phase Locked Loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only a 3.3 V power supply, analog input, and Hsync. Three-
state CMOS outputs may be powered from 2.2 V to 3.3V.
The AD9882’s on-chip PLL generates a pixel clock from Hsync.
Pixel clock output frequencies range from 12 MHz to 140 MHz.
PLL clock jitter is typically 500 ps p-p at 140 MSPS. The AD9882
also offers full sync processing for composite sync and Sync-on-
Green (SOG) applications.
Digital InterfaceThe AD9882 contains a DVI 1.0 compatible receiver and supports
display resolutions up to SXGA (1280 ¥ 1024 at 60 Hz). The
receiver features an intra-pair skew tolerance of up to one full
clock cycle.
With the inclusion of HDCP, displays may now receive encrypted
video content. The AD9882 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and renew-
ability of that authentication during transmission as specified by
the HDCP v1.0 protocol.
Fabricated in an advanced CMOS process, the AD9882 is
provided in a space-saving 100-lead LQFP surface-mount plastic
package and is specified over the 0∞C to 70∞C temperature range.
AD9882–SPECIFICATIONS
ANALOG INTERFACE
ELECTRICAL CHARACTERISTICSDIGITAL INPUTS
DIGITAL OUTPUTS
(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate, unless
otherwise noted.)
AD9882NOTESDrive Strength = 11.VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693.DATACK Load = 15 pF, Data Load = 5 pF.Simulated typical performance with package mounted to a four-layer board.
Specifications subject to change without notice.
AD9882
DIGITAL INTERFACE
ELECTRICAL CHARACTERISTICS
(VD = 3.3 V, VDD = 3.3 V, Clock = Maximum, unless otherwise noted.)
AD9882NOTESThe typical pattern contains a grayscale area, Output Drive = High.DATACK Load = 10 pF, Data Load = 10 pF.The worst-case pattern contains a black and white checkerboard pattern, Output Drive = High.DRIVE STRENGTH = 11
Specifications subject to change without notice.
AD9882
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9882 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –25∞C to +85∞C
Storage Temperature . . . . . . . . . . . . . . . . . –65∞C to +150∞C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 175∞C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions outside of those indicated in the operation sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
EXPLANATION OF TEST LEVELS
Test Level100% production tested.
II.100% production tested at 25∞C and sample tested at
specified temperatures.
III.Sample tested only.
IV.Parameter is guaranteed by design and characterization
testing.Parameter is a typical value only.
VI.100% production tested at 25∞C; guaranteed by design
and characterization testing.
PIN CONFIGURATIONGND
GREEN<7>
GREEN<6>
GREEN<5>
GREEN<4>
GREEN<3>
GREEN<2>
GREEN<1>
GREEN<0>
VDD
GND
BLUE<7>
BLUE<6>
BLUE<5>
BLUE<4>
BLUE<3>
BLUE<2>
BLUE<1>
BLUE<0>
VDD
GND
CTL 0
CTL 1
CTL 2
CTL 3
GND
TERM
GND
X0–
X0+
GND
X1–
X1+
GND
X2–
X2+
GND
XC+
XC–
GND
GND
FIL
GND
GND
MIDBYPASS
REFBYPASS
GND
RAIN
GND
GND
GAIN
SOGIN
GND
GND
BAIN
GND
GND
DDCSDA
DDCSCL
PVD
GND
RED<0>RED<1>RED<2>RED<3>RED<4>RED<5>RED<6>RED<7>GNDSOGOUTHSOUTVSOUTDEDA
GNDMD
MCLVSYNCHSYNCSD
SCLA0
AD9882
Table I.Complete Pinout ListSync
Outputs
References
PLL Filter
Serial Port
Control
Data
PIN DESCRIPTIONS OF SHARED PINS BETWEEN
ANALOG AND DIGITAL INTERFACES
HSOUTHorizontal Sync OutputA reconstructed and phase-aligned version of the
video Hsync. The polarity of this output can be
controlled via a serial bus bit. In analog interface
mode, the placement and duration are variable.
In digital interface mode, the placement and
duration are set by the graphics transmitter.
VSOUTVertical Sync OutputThe separated Vsync from a composite signal or
a direct pass-through of the Vsync input. The
polarity of this output can be controlled via a
serial bus bit. The placement and duration in all
modes is set by the graphics transmitter.
SERIAL PORT (2-WIRE)
SDASerial Port Data I/O
SCLSerial Port Data ClockSerial Port Address InputFor a full description of the 2-wire serial register,
refer to the Control Port section on 2-Wire
Serial Control.
DATA OUTPUTS
REDData Output, RED Channel
GREENData Output, GREEN Channel
BLUEData Output, BLUE ChannelThe main data outputs. Bit 7 is the MSB. These
outputs are shared between the two interfaces
and behave according to which interface is active.
Refer to the sections on the two interfaces for
more information on how these outputs behave.
DATACKData Output ClockJust like the data outputs, the data clock output
is shared between the two interfaces. It behaves
differently depending on which interface is active.
Refer to the sections on the two interfaces to
determine how this pin behaves.
Table II.Analog Interface Pin ListInputs
External
Sync/Clock
Sync Outputs
Voltage
Reference
AD9882
PIN FUNCTION DETAIL (ANALOG INTERFACE)
INPUTS
RAINAnalog Input for RED Channel
GAINAnalog Input for GREEN Channel
BAINAnalog Input for BLUE ChannelHigh impedance inputs that accept the RED,
GREEN, and BLUE channel graphics signals,
respectively. For RGB, the three channels are
identical and can be used for any colors, but
colors are assigned for convenient reference.
For proper 4:2:2 formatting in a YPbPr application,
the Y must be connected to the GAIN input, the
Pb must be connected to the BAIN input, and the
Pr must be connected to the RAIN input.
They accommodate input signals ranging from
0.5 V to 1.0 V full scale. Signals should be
ac-coupled to these pins to support clamp
operation.
HSYNCHorizontal Sync InputThis input receives a logic signal that establishes
the horizontal timing reference and provides the
frequency reference for pixel clock generation.
The logic sense of this pin is controlled by Serial
Register Bit 10H, Bit 6 (Hsync Polarity). Only
the leading edge of Hsync is active; the trailing
edge is ignored. When Hsync Polarity = 0, the
falling edge of Hsync is used. When Hsync
Polarity = 1, the rising edge is active.
The input includes a Schmitt trigger for noise
immunity, with a nominal input threshold of
1.5 V.
Electrostatic Discharge (ESD) protection diodes
will conduct heavily if this pin is driven more
than 0.5 V above the maximum tolerance voltage
(3.3 V), or more than 0.5 V below ground.
VSYNCVertical Sync InputThis is the input for vertical sync.
SOGINSync-on-Green InputThis input is provided to assist with processing
signals with embedded sync, typically on the
GREEN channel. The pin is connected to a
high speed comparator with an internally gener-
ated threshold, which is set by the value of
register 0FH, Bits 7–3.
When connected to an ac-coupled graphics
signal with embedded sync, it will produce a
noninverting digital output on SOGOUT.
When not used, this input should be left uncon-
nected. For more details on this function and
how it should be configured, refer to the Sync-
on-Green section.
SOGOUTSync-on-Green Slicer OutputThis pin can be programmed to produce either
the output from the Sync-on-Green slicer com-
parator or an unprocessed but delayed version of
the Hsync input. See the Sync Processing Block
Diagram, Figure 18, to view how this pin is
connected.
Note: The output from this pin is the composite
SYNC without additional processing from the
AD9882.
FILTExternal Filter ConnectionFor proper operation, the pixel clock generator
PLL requires an external filter. Connect the
filter shown in Figure 6 to this pin. For optimal
performance, minimize noise and parasitics on
this node.
REFBYPASSInternal Reference BYPASSBypass for the internal 1.25 V band gap refer-
ence. It should be connected to ground through
a 0.1 mF capacitor.
The absolute accuracy of this reference is ±4%,
and the temperature coefficient is ±50 ppm,
which is adequate for most AD9882 applica-
tions. If higher accuracy is required, an external
reference may be employed instead.
MIDBYPASSMidscale Voltage Reference BYPASSBypass for the internal midscale voltage refer-
ence. It should be connected to ground through
a 0.1 mF capacitor. The exact voltage varies with
the gain setting of the RED channel.
HSOUTHorizontal Sync OutputA reconstructed and phase-aligned version of
the Hsync input. The duration of Hsync can
only be programmed on the analog interface,
not the digital.
DATACKData Output ClockThe data clock output signal is used to clock the
output data and HSOUT into external logic.
It is produced by the internal clock generator
and is synchronous with the internal pixel
sampling clock.
When the sampling time is changed by adjusting
the PHASE register, the output timing is shifted
as well. The Data, DATACK, and HSOUT
outputs are all moved so the timing relationship
among the signals is maintained.
VSOUTVertical Sync OutputThe separated Vsync from a composite signal or
a direct pass-through of the Vsync input. The
polarity of this output can be controlled via
Register 10H, Bit 2. The placement and duration
in all modes is set by the graphics transmitter.
REDData Output, RED Channel
GREENData Output, GREEN Channel
BLUEData Output, BLUE ChannelThese are the main data outputs. Bit 7 is the MSB.
The delay from pixel sampling time to output is
fixed. When the sampling time is changed by
adjusting the PHASE register, the output timing
is shifted as well. The DATACK and HSOUT
outputs are also moved, so the timing relation-
ship among the signals is maintained.
Please refer to the timing diagrams for more
information.
POWER SUPPLYMain Power SupplyThese pins supply power to the main elements of
the circuit. They should be as quiet as possible.
VDDDigital Output Power SupplyA large number of output pins (up to 25) switch-
ing at high speed (up to 140 MHz) generates a
lot of power supply transients. These supply
pins are identified separately from the VD pins
so special care can be taken to minimize out-
put noise transferred into the sensitive analog
circuitry.
If the AD9882 is interfacing with lower voltage
logic, VDD may be connected to a lower supply
voltage (as low as 2.2 V) for compatibility.
PVDClock Generator Power SupplyThe most sensitive portion of the AD9882 is the
clock generation circuitry. These pins provide
power to the clock PLL and help the user design
for optimal performance. The designer should
provide noise-free power to these pins.
GNDGroundThe ground return for all circuitry on chip. It is
recommended that the AD9882 be assembled on
a single solid ground plane, with careful attention
to ground current paths.
Table III.Interface Selection Controls
AIO
AD9882
Table IV.Power-Down Modes, 4:2:2 and 4:4:4 Format DescriptionsSoft Power-
Down (Seek
Analog
Interface On
NOTESPower-down is controlled via Bit 1 in Serial Bus Register 14H.Analog Interface Detect is determined by OR-ing Bits 7, 6, and 5 in Serial Bus Register 15H.Digital Interface Detect is determined by Bit 4 in Serial Bus Register 15H.
THEORY OF OPERATION (INTERFACE DETECTION)
Active Interface Detection and SelectionThe AD9882 includes circuitry to detect whether an interface is
active or not. See Table III.
For detecting the analog interface, the circuitry monitors the
presence of Hsync, Vsync, and Sync-on-Green. The result of
the detection circuitry can be read from the 2-wire serial inter-
face bus at Address 15H, Bits 7, 5, and 6, respectively. If one of
these sync signals disappears, the maximum time it takes for the
circuitry to detect it is 100 ms.
For detecting the digital interface, there are two stages of detection.
The first stage searches for the presence of the digital interface
clock. The circuitry for detecting the digital interface clock is
active even when the digital interface is powered down. The
result of this detection stage can be read from the 2-wire serial
interface bus at Address 15H, Bit 4. If the clock disappears, the
maximum time it takes for the circuitry to detect it is 100 ms.
Once a digital interface clock is detected, the digital interface is
powered up and the second stage of detection begins. During
the second stage, the circuitry searches for 32 consecutive DEs.
Once 32 DEs are found, the detection process is complete.
There is an override for the automatic interface selection. It is
the AIO (Active Interface Override) bit, Register 0FH, Bit 2.
When the AIO bit is set to logic “0,” the automatic circuitry will
be used. When the AIO bit is set to logic “1,” the AIS (Active
Interface Select) bit (Register 0FH, Bit 1) will be used to
determine the active interface rather than the automatic circuitry.
Power ManagementThe AD9882 is a dual interface device with shared outputs. Only
one interface can be used at a time. For this reason, the chip auto-
matically powers down the unused interface. When the analog
interface is being used, most of the digital interface circuitry is
powered down, and vice versa. This helps to minimize the AD9882
total power dissipation. In addition, if neither interface has activity
on it, then the chip powers down both interfaces. The AD9882
uses the activity detect circuits, the active interface bits in Serial
Register 15H, the active interface override bits in Register 0FH,
Bits 2 and 1, and the power-down bit in Register 14H, Bit 1, to
determine the correct power state. In a given power mode, not all
circuitry in the inactive interface is powered down completely.
When the digital interface is active, the band gap reference
Hsync, Vsync, and SOG detect circuitry remain powered up.
When the analog interface is active, the digital interface clock
detect circuit is not powered down. Table IV summarizes how
the AD9882 determines what power mode to be in and what
circuitry is powered on/off in each of these modes. The power-
down command has priority, then the active interface override,
and then the automatic circuitry.
THEORY OF OPERATION AND DESIGN GUIDE
(ANALOG INTERFACE)
General DescriptionThe AD9882 is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel
monitors or projectors. The device is ideal for implementing a
computer interface for HDTV monitors or as the front end to
high performance video scan converters.
Implemented in a high performance CMOS process, the inter-
face can capture signals with pixel rates of up to 140 MHz.
The AD9882 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a
2-wire serial interface. Full integration of these sensitive analog
functions makes the system design straightforward and less
sensitive to the physical and electrical environment.
With a typical power dissipation of only 875 mW and an operat-
ing temperature range of 0∞C to 70∞C, the device requires no
special environmental considerations.
Input Signal HandlingThe AD9882 has three high impedance analog input pins for
the RED, GREEN, and BLUE channels. They will accommodate
signals ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-pin D connector, or BNC connectors.
The AD9882 should be located as close as practical to the input
connector. Signals should be routed via matched-impedance
traces (normally 75 W) to the IC input pins.
At that point, the signal should be resistively terminated (75W
to the signal ground return) and capacitively coupled to the
AD9882 inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit. See Figure 1.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal band-
width. The wide bandwidth inputs of the AD9882 (300MHz) can
track the input signal continuously as it moves from one pixel
level to the next and digitize the pixel during a long, flat pixel
time. In many systems, however, there are mismatches, reflections,
and noise, which can result in excessive ringing and distortion of
the input waveform. This makes it more difficult to establish a
sampling phase that provides good image quality. It has been
shown that a small inductor in series with the input is effective
in rolling off the input bandwidth slightly and providing a high
quality signal over a wider range of conditions. Using a Fair-Rite
#2508051217Z0 High Speed Signal Chip Bead inductor in the
circuit of Figure 1 gives good results in most applications.
Figure 1.Analog Input Interface Circuit
AD9882
Hsync, Vsync InputsThe AD9882 receives a horizontal sync signal and uses it to
generate the pixel clock and clamp timing. This can be either a
sync signal directly from the graphics source or a preprocessed
TTL or CMOS level signal.
The Hsync input includes a Schmitt trigger buffer and is capable
of handling signals with long rise times, with superior noise
immunity. In typical PC based graphic systems, the sync signals
are simply TTLlevel drivers feeding unshielded wires in the
monitor cable. As such, no termination is required.
Serial Control PortThe serial control port is designed for 3.3 V logic. If there are
5 V drivers on the bus, these pins should be protected with
150W series resistors placed between the pull-up resistors and
the input pins.
Output Signal HandlingThe digital outputs are designed and specified to operate from3.3 V power supply (VDD). They can also work with a VDD as
low as 2.5 V for compatibility with other 2.5 V logic.
Clamping
RGB ClampingTo properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board A/D
converters.
Most graphics systems produce RGB signals with black at ground
and white at approximately 0.75V. However, if sync signals are
embedded in the graphics, the sync tip is often at ground and
black is at 300 mV; white will be approximately 1.0V. Some
common RGB line amplifier boxes use emitter-follower buffers
to split signals and increase drive capability. This introduces a
700mV dc offset to the signal, which is removed by clamping
for proper capture by the AD9882.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. Origi-
nating from CRT displays, the electron beam is “blanked” by
sending a black level during horizontal retrace to prevent
disturbing the image. Most graphics systems maintain this
format of sending a black level between active video lines.
An offset is then introduced, which results in the A/D converters
producing a black output (code 00H) when the known black
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to
eliminate offset errors.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of Hsync. Fortunately, there is virtually always
a period following Hsync called the back porch, in which a good
black reference is provided. This is the time when clamping should
be done.
The clamp timing is established by the AD9882 internal clamp
timing generator. The Clamp Placement Register (05H) is
programmed with the number of pixel times that should pass
after the trailing edge of Hsync before clamping starts. A second
register (Clamp Duration, 06H) sets the duration of the clamp.
These are both 8-bit values, providing considerable flexibility in
clamp generation. The clamp timing is referenced to the trailing
edge of Hsync since the back porch (black reference) always
follows Hsync. A good starting point for establishing clamping is
to set the clamp placement to 08H (providing eight pixel periods
for the graphics signal to stabilize after sync) and set the clamp
duration to 14H (giving the clamp 20 pixel periods to re-establish
the black reference).
The value of the external input coupling capacitor affects the
performance of the clamp. If the value is too small, there can be
an amplitude change during a horizontal line time (between
clamping intervals). If the capacitor is too large, then it will take
excessively long for the clamp to recover from a large change in
incoming signal offset. The recommended value (47 nF) results
in recovery from a step error of 100 mV to within one-half LSB
in 10 lines using a clamp duration of 20 pixel periods on a 75 Hz
SXGA signal.
YUV ClampingYUV signals are slightly different from RGB signals in that the
dc reference level (black level in RGB signals) will be at the
midpoint of the U and V video. For these signals, it can be
necessary to clamp to the midscale range of the A/D converter
range (80H) rather than the bottom of the A/D converter range (00H).
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
clamped to either midscale or ground independently. These bits
are located in Register 11H and are Bits 4–6. The midscale
reference voltage that each A/D converter clamps to is provided
on the MIDBYPASS pin (Pin 74). This pin should be bypassed
to ground with a 0.1 mF capacitor (even if midscale clamping is
not required).
Gain and Offset ControlThe AD9882 can accommodate input signals with inputs ranging
from 0.5 V to 1.0 V full scale. The full-scale range is set in three
8-bit registers (RED Gain, GREEN Gain, and BLUE Gain).
A code of 0 establishes a minimum input range of 0.5 V;
255corresponds with the maximum range of 1.0 V. Note
that INCREASING the gain setting results in an image with
LESS contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (RED Offset,
GREEN Offset, BLUE Offset) provide independent settings
for each channel.
The offset controls provide a ±63 LSB adjustment range. This
range is connected with the full-scale range, so if the input range
is doubled (from 0.5 V to 1.0 V), the offset step size is also
doubled (from 2 mV per step to 4 mV per step).
Figure 2 illustrates the interaction of gain and offset controls.
The magnitude of an LSB in offset adjustment is proportional to
the full-scale range, so changing the full-scale range also changes
the offset. The change is minimal if the offset setting is near
midscale. When changing the offset, the full-scale range is not
affected, but the full-scale level is shifted by the same amount as
the zero-scale level.
Figure 2.Gain and Offset Control
Sync-on-Green (SOG)The Sync-on-Green input operates in two steps. First, it sets
abaseline clamp level off of the incoming video signal with a
negative peak detector. Second, it sets the Sync trigger level
(nominally 150 mV above the negative peak). The exact trigger
level is variable and can be programmed via Register 0FH,
Bits 7–3. The Sync-on-Green input must be ac-coupled to the
green analog input through its own capacitor as shown in Figure3.
The value of the capacitor must be 1 nF ±20%. If Sync-on-Green
is not used, this connection is not required and SOGIN should
be left unconnected. (Note: The Sync-on-Green signal is always
negative polarity.) Please refer to the Sync Processing section
for further information.
Figure 3.Typical Clamp Configuration
Clock GenerationA Phase Locked Loop (PLL) is employed to generate the pixel
clock. The Hsync input provides a reference frequency for the
PLL. A Voltage Controlled Oscillator (VCO) generates a much
higher pixel clock frequency. This pixel clock is divided by the
PLL divide value (Registers 01H and 02H) and phase compared
with the Hsync input. Any error is used to shift the VCO frequency
and maintain lock between the two signals.
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,
there is a period during which the signal is slewing from the old
pixel amplitude and settling at its new value. Then there is a
time when the input voltage is stable, before the signal must
slew to a new value (Figure 4). The ratio of the slewing time to
the stable time is a function of the bandwidth of the graphics
DAC and the bandwidth of the transmission system (cable and
termination). It is also a function of the overall pixel rate. Clearly,
if the dynamic characteristics of the system remain fixed, then
the slewing and settling time is likewise fixed. This time must be
subtracted from the total pixel period, leaving the stable period.
At higher pixel frequencies, the total cycle time is shorter, and
the stable pixel time becomes shorter as well.
Figure 4.Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined and must also be subtracted
from the stable pixel time.
Considerable care has been taken in the design of the AD9882’s
clock generation circuit to minimize jitter. As indicated in Fig-
ure 5, the clock jitter of the AD9882 is less than 6% of the total
pixel time in all operating modes, making the reduction in the
valid sampling time due to jitter negligible.
Figure 5.Pixel Clock Jitter vs. Frequency
AD9882
Table V.VCO Frequency RangesThe 3-bit Charge Pump Current Register (Register 03H,
Bits 3–5). This register allows the current that drives the
low-pass loop filter to be varied. The possible current values
are listed in Table VI.
Table VI.Charge Pump Current/Control BitsThe 5-bit Phase Adjust Register (Register 04H, Bits 3–7).
The phase of the generated sampling clock may be shifted to
locate an optimum sampling point within a clock cycle. The
Phase Adjust Register provides 32 phase-shift steps of 11.25∞
each. The Hsync signal with an identical phase shift is available
through the HSOUT pin.
The PLL characteristics are determined by the loop filter design,
the PLL charge pump current, and the VCO range setting.
The loop filter design is illustrated in Figure 6. Recommended
settings of VCO range and charge pump current for VESA
standard display modes are listed in Table VII.
Figure 6.PLL Loop Filter Detail
Four programmable registers are provided to optimize the
performance of the PLL. These registers are:The 12-bit Divisor Register (Registers 01H and 02H). The
input Hsync frequencies range from 15 kHz to 110 kHz. The
PLL multiplies the frequency of the Hsync signal, producing
pixel clock frequencies in the range of 12 MHz to 140 MHz.
The Divisor Register controls the exact multiplication factor.
This register may be set to any value between 221 and 4095.
(The divide ratio that is actually used is the programmed
divide ratio plus one.)The 2-bit VCO Range Register (Register 03H, Bits 6 and 7).
To improve the noise performance of the AD9882, the VCO
operating frequency range is divided into three overlapping
regions. The VCO Range register sets this operating range.
The frequency ranges for the lowest and highest regions are
shown in Table V.
Table VII.Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
The COAST function allows the PLL to continue to run at the
same frequency, in the absence of the incoming Hsync signal or
during disturbances in Hsync (such as equalization pulses). This
may be used during the vertical sync period, or any other time
that the Hsync signal is unavailable. Also, the polarity of the
Hsync signal may be set through the Hsync Polarity Bit (Register
10H, Bit 6). If not using automatic polarity detection, the Hsync
polarity bit should be set to match the polarity of the Hsync
input signal.
TIMING (ANALOG INTERFACE)The following timing diagrams show the operation of the AD9882.
The Output Data Clock signal is created so that its rising edge
always occurs between data transitions and can be used to latch
the output data externally.
Figure 7.Output Timing
Hsync TimingHorizontal Sync (Hsync) is processed in the AD9882 to elimi-
nate ambiguity in the timing of the leading edge with respect to
the phase-delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360∞ in 32 steps via the Phase Adjust
Register (Register 04H) to optimize the pixel sampling time.
Display systems use Hsync to align memory and display write
cycles, so it is important to have a stable timing relationship
between Hsync output (HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9882. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be pro-
grammed either active high or active low (Register 10H, Bit 5).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via
Register 07H. HSOUT is the sync signal that should be used to
drive the rest of the display system.
Coast TimingIn most computer systems, the Hsync signal is provided continu-
ously on a dedicated wire. In these systems, the COAST function
is unnecessary and should be disabled using Register 11H, Bits 1–3.
In some systems, however, Hsync is disturbed during the Vertical
Sync period (Vsync). In other cases, Hsync pulses disappear.other systems, such as those that employ Composite Sync
(Csync) signals or embedded Sync-on-Green (SOG), Hsync
includes equalization pulses or other distortions during Vsync. To
avoid upsetting the clock generator during Vsync, it is important
to ignore these distortions. If the pixel clock PLL sees extraneous
pulses, it will attempt to lock to this new frequency and will
have changed frequency by the end of the Vsync period. It will
then take a few lines of correct Hsync timing to recover at the
beginning of a new frame, resulting in a “tearing” of the image
at the top of the display.
The COAST function is provided to eliminate this problem. It
is an internally generated signal, created by the sync processing
engine that disables the PLL input and allows the clock to free-run
at its then-current frequency. The PLL can free-run for several
lines without significant frequency drift.
AD9882
TIMING DIAGRAMSFigure 8.4:4:4 Mode (for RGB and YPbPr)
Figure 9.4:2:2 Mode (for YPbPr Only)
