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AD9878BSTZ
Mixed-Signal Front End for Broadband Applications
Mixed-Signal Front End
for Broadband Applications
Rev. A
FEATURES
Low cost 3.3 V CMOS MxFE™ for broadband applications
DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant
232 MHz quadrature digital upconverter
12-bit direct IF DAC (TxDAC+®)
Up to 65 MHz carrier frequency DDS
Programmable sampling clock rates
Analog Tx output level adjust
Dual 12-bit, 29 MSPS direct IF ADCs with video clamp input
10-bit, 29 MSPS sampling ADC
8-bit ∑-∆ auxiliary DAC
Direct interface to AD832x family of PGA cable drivers
APPLICATIONS
Cable set-top boxes
Cable and wireless modems
FUNCTIONAL BLOCK DIAGRAM TxID[5:0]
SDIO
IF10[4:0]
IF12[11:0]
FLAG[2:1]
Figure 1.
GENERAL DESCRIPTION The AD9878 is a single-supply, cable modem/set-top box,
mixed-signal front end. The device contains a transmit path
interpolation filter, a complete quadrature digital upconverter,
and a transmit DAC. The receive path contains dual 12-bit
ADCs and a 10-bit ADC. All internally required clocks and an
output system clock are generated by the phase-locked loop
(PLL) from a single crystal oscillator or clock input.
The transmit path interpolation filter provides an upsampling
factor of 16× with an output signal bandwidth up to 4.35 MHz.
Carrier frequencies up to 65 MHz with 26 bits of frequency tuning
resolution can be generated by the direct digital synthesizer
(DDS). The transmit DAC resolution is 12 bits and can run at
sampling rates as high as 232 MSPS. Analog output scaling from
0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when
reduced output levels are required.
The 12-bit ADCs provide excellent undersampling performance,
allowing this device to typically deliver better than 10 ENOBs
with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at
rates up to 29 MHz, allowing them to process wideband signals.
The AD9878 includes a programmable ∑-∆ DAC, which can be
used to control an external component such as a variable gain
amplifier (VGA) or a voltage controlled tuner.
The AD9878 also integrates a CA port that enables a host
processor to interface with the AD832x family of programmable
gain amplifier (PGA) cable drivers or industry equivalent via
the MxFE serial port (SPORT).
The AD9878 is available in a 100-lead, LQFP package. The
AD9878 is specified over the extended industrial (−40°C to
+85°C) temperature range.
TABLE OF CONTENTS Electrical Characteristics.................................................................4
Absolute Maximum Ratings............................................................7
Explanation of Test Levels...........................................................7
Thermal Characteristics..............................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Typical Performance Characteristics...........................................10
Terminology....................................................................................13
Register Bit Definitions..................................................................14
Register 0x00—Initialization....................................................15
Register 0x01—Clock Configuration.......................................15
Register 0x02—Power-Down....................................................15
Register 0x03—Flag Control.....................................................15
Register 0x04—∑-∆ Control Word...........................................15
Register 0x07—Video Input Configuration............................16
Register 0x08—ADC Clock Configuration............................16
Register 0x0C—Die Revision....................................................16
Register 0x0D—Tx Frequency Tuning Words LSBs..............16
Register 0x0E—DAC Gain Control.........................................16
Register 0x0F—Tx Path Configuration...................................16
Registers 0x10 Through 0x17—Burst Parameter...................17
Serial Interface for Register Control............................................18
General Operation of the Serial Interface...............................18
Instruction Byte..........................................................................18
Serial Interface Port Pin Descriptions.....................................18
MSB/LSB Transfers.....................................................................19
Notes on Serial Port Operation................................................19
Theory of Operation......................................................................20
Transmit Path..............................................................................21
Data Assembler...........................................................................21
Transmit Timing.........................................................................21
Interpolation Filter.....................................................................21
Half-Band Filters (HBFs)..........................................................21
Cascade Integrator Comb (CIC) Filter....................................21
Combined Filter Response........................................................21
Digital Upconverter...................................................................22
Tx Signal Level Considerations................................................22
Tx Throughput and Latency.....................................................23
DAC..............................................................................................23
Programming the AD8321/AD8323 or
AD8322/AD8327/AD8238 Cable-Driver Amplifiers............23
OSCIN Clock Multiplier...........................................................24
Clock and Oscillator Circuitry.................................................24
Programmable Clock Output REFCLK..................................24
Power-Up Sequence...................................................................26
Reset.............................................................................................26
Transmit Power-Down..............................................................26
∑-∆ Outputs................................................................................27
Receive Path (Rx).......................................................................27
IF10 and IF12 ADC Operation................................................27
ADC Voltage References...........................................................29
Video Input.................................................................................29
PCB Design Considerations..........................................................30
Component Placement..............................................................30
Power Planes and Decoupling..................................................30
Ground Planes............................................................................30
Signal Routing.............................................................................30
Outline Dimensions.......................................................................36
Ordering Guide..........................................................................36
REVISION HISTORY
3/05—Rev. 0 to Rev. A Changed OSCOUT to REFCLK..................................................Universal
Changes to Electrical Characteristics........................................................4
Changes to Pin Configuration and Function Descriptions....................8
Changes to ∑-∆ Output Signals (Figure 32)............................................27
Change to ∑-∆ RC Filter (Figure 33).......................................................27
Changes to Evaluation PCB Schematic (Figure 38 and Figure 39)......31
Updated Outline Dimensions...................................................................36
Changes to Ordering Guide......................................................................36
5/03—Revision 0: Initial Version
ELECTRICAL CHARACTERISTICS VAS = 3.3 V ± 5%, VDS = 3.3 V ± 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8), ADC clock derived from OSCIN,
RSET = 4.02 kΩ, maximum. Fine gain, 75 Ω DAC load.
Table 1.
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS I. Devices are 100% production tested at 25°C and guaranteed
by design and characterization testing for extended industrial
operating temperature range (−40°C to +85°C).
II. Parameter is guaranteed by design and/or characterization
testing.
III. Parameter is a typical value only.
N/A. Test level definition is not applicable.
THERMAL CHARACTERISTICS Thermal resistance of 100-lead LQFP: θJA = 40.5°C/W
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGNDVIDEO INAGNDIF12A
IF12A
AGNDAV
FT12A
AGNDIF12B
IF12B
AGNDAV
FT12B
AGNDAV
DD1
AGND1
IF10+IF10
AGND
REFT10
REFB10
AGND10
AVDD10
DRVDD
DRGND
REFCLK
SIGDELT
FLAG1
FLAG2
CA_EN
CA_DATA
CA_CLK
DVDDOSC
OSCIN
XTAL
DGNDOSC
AGNDPLL
PLLFILT
AVDDPLL
DVDDPLL
DGNDPLL
AVDDTx
Tx+
Tx–
TxSYN
TxIQ(
TxIQ(
TxIQ(
TxIQ(
TxIQ(
TxIQ(
DGND
DGND
PROFILE
ESET
DGND
DGNDTx
DDTx
RDN
FIO
ADJ
AGNDTx
DRGND
DRVDD
(MSB) IF12(11)
IF12(10)
IF12(9)
IF12(8)
IF12(7)
IF12(6)
IF12(5)
IF12(4)
IF12(3)
IF12(2)
IF12(1)
IF12(0)
(MSB) IF10(4)
IF10(3)
IF10(2)
IF10(1)
IF10(0)
RxSYNC
DRGND
DRVDD
MCLK
DVDD
DGND
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
MAGNITUDE
(dB)4681012141618–100
–10Figure 3. Dual-Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz,
RSET = 10 kΩ (IOUT = 4 mA), RBW = 1 kHz
FREQUENCY (MHz)
MAGNITUDE
(dB)4681012141618–100
–10Figure 4. Dual-Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz,
RSET = 4 kΩ (IOUT = 10 mA), RBW = 1 kHz
FREQUENCY (MHz)
MAGNITUDE
(dB)575961636567697073–100
–10FREQUENCY (MHz)
MAGNITUDE
(dB)575961636567697173–100
–10
Figure 6. Dual-Sideband Spectral Plot, fC = 65 MHz, f = 1 MHz,
RSET = 4 kΩ (IOUT = 10 mA), RBW = 1 kHz
FREQUENCY (MHz)
MAGNITUDE
(dB)20406080100–100
120Figure 7. Single Sideband @ 65 MHz, fC = 66 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz
FREQUENCY (MHz)
MAGNITUDE
(dB)20406080100–100
12003277-027
FREQUENCY (MHz)
MAGNITUDE
(dB)20406080100–100
120Figure 9. Single Sideband @ 42 MHz, fC = 43 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz
FREQUENCY (MHz)
MAGNITUDE
(dB)20406080100–90
120Figure 10. Single Sideband @ 42 MHz, fC = 43 MHz,
f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz
FREQUENCY (MHz)
MAGNITUDE
(dB)20406080100–100
120Figure 11. Single Sideband @ 5 MHz, fC = 6 MHz,
FREQUENCY (MHz)
MAGNITUDE
(dB)20406080100–90
120Figure 12. Single Sideband @ 5 MHz, fC = 6 MHz,
f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz
FREQUENCY (MHz)
MAGNITUDE
(dB)
2.5Figure 13. Single Sideband @ 65 MHz, fC = 66 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 500 Hz
FREQUENCY (MHz)
MAGNITUDE
(dB)
2.5Figure 14. Single Sideband @ 65 MHz, fC = 66 MHz,
FREQUENCY (MHz)
MAGNITUDE
(dB)
–10Figure 15. Single Sideband @ 65 MHz, fC = 66 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 50 Hz
MAGNITUDE
(dB)
FREQUENCY (MHz)
–2.5Figure 16. Single Sideband @ 65 MHz, fC = 66 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 10 Hz
MAGNITUDE
(dB)
FREQUENCY (MHz)5101520253035404550Figure 17. 16-QAM @ 42 MHz Spectral Plot, RBW = 1 kHz
MAGNITUDE
(dB)
FREQUENCY (MHz)5101520253035404550Figure 18. 16-QAM @ 5 MHz Spectral Plot, RBW = 1 kHz
TERMINOLOGY
Differential Nonlinearity Error (DNL, No Missing Codes) An ideal converter exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. No missing
codes indicates that all of the ADC codes must be present over
all operating ranges.
Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from
a line drawn from negative full scale through positive full scale.
The point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line.
Phase Noise Single-sideband, phase-noise power is specified relative to the
carrier (dBc/Hz) at a given frequency offset (1 kHz) from the
carrier. Phase noise can be measured directly in single-tone
transmit mode with a spectrum analyzer that supports noise
marker measurements. It detects the relative power between
the carrier and the offset (1 kHz) sideband noise and takes
the resolution bandwidth (RBW) into account by subtracting
10 × log(RBW). It also adds a correction factor that compensates
for the implementation of the resolution bandwidth, log display,
and detector characteristic.
Output Compliance Range The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Spurious-Free Dynamic Range (SFDR) The difference, in dB, between the rms amplitude of the DAC
output signal (or ADC input signal) and the peak spurious signal
over the specified bandwidth (Nyquist bandwidth, unless
otherwise noted).
Pipeline Delay (Latency) The number of clock cycles between conversion initiation and
the associated output data being made available.
Offset Error The first code transition should occur at an analog value ½ LSB
above negative full scale. Offset error is defined as the deviation
of the actual transition from that point.
Gain Error The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur for an
analog value 1½ LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last
Aperture Delay The aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance that specifies the time delay between the
rising edge of the sampling clock input and when the input
signal is held for conversion.
Aperture Jitter Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the ADC.
Input Referred Noise The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and converted to an equivalent voltage. This results in a
noise figure that can be directly referred to the input of the MxFE.
Signal-to-Noise and Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the measured input signal
to the rms sum of other spectral components below the Nyquist
frequency, including harmonics, but excluding dc. The value for
SINAD is expressed in decibels.
Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number
of bits. Using the following formula, it is possible to get a measure
of performance expressed as N, the effective number of bits: 02.6dB76.1N
Thus, the effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.
Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured input signal
to the rms sum of other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal.
It is expressed as a percentage, or in decibels.
Power Supply Rejection Power supply rejection specifies the converter’s maximum full-
scale change when the supplies are varied from nominal to
minimum or maximum specified voltages.
Channel-to-Channel Isolation (Crosstalk) In an ideal multichannel system, the signal in one channel does
not influence the signal level of another channel. The channel-
to-channel isolation specification is a measure of the change
REGISTER BIT DEFINITIONS
Table 4. Register Map REGISTER 0x00—INITIALIZATION
Bits 0 to 4: OSCIN Multiplier This register field is used to program the on-chip clock
multiplier that generates the chip’s high frequency system clock,
fSYSCLK. For example, to multiply the external crystal clock fOSCIN
by 16, program Register 0x00, Bits 4:0, to 0x10. The default
clock multiplier value, M, is 0x08. Valid entries range from 1 to
31. When M is set to 1, the PLL is disabled and internal clocks
are derived directly from OSCIN. The PLL requires 200 MCLK
cycles to regain frequency lock after a change in M. After the
recapture time of the PLL, the frequency of fSYSCLK is stable.
Bit 5: Reset Writing 1 to this bit resets the registers to their default values
and restarts the chip. The reset bit always reads back 0. The bits
in Register 0x00 are not affected by this software reset. However,
a low level at the RESET pin forces all registers, including all
bits in Register 0x00, to their default states.
Bit 6: LSB First Active high indicates SPI serial port access of instruction byte and
data registers is LSB first. Default low indicates MSB-first format.
Bit 7: SDIO Bidirectional Active high configures the serial port as a 3-signal port with
the SDIO pin used as a bidirectional input/output pin. Default
low indicates that the serial port uses four signals with SDIO
configured as an input and SDO configured as an output.
REGISTER 0x01—CLOCK CONFIGURATION
Bits [5:0]: MCLK Divider This register determines the output clock on the REFCLK pin.
At default 0 (R = 0), REFCLK provides a buffered version of the
OSCIN clock signal for other chips. The register can also be used
to divide the chip’s master clock fMCLK by R, where R is an integer
between 2 and 63. The generated reference clock on REFCLK pin
can be used for external frequency controlled devices.
Bit 7: PLL Lock Detect When this bit is set low, the REFCLK pin functions in its
default mode and provides an output clock with frequency
fMCKL/R, as described above. If this bit is set to 1, the REFCLK pin
is configured to indicate whether the PLL is locked to fOSCIN. In
this mode, the REFCLK pin should be low-pass filtered with an
RC filter of 1.0 kΩ and 0.1 µF. A low output on REFCLK indicates
that the PLL has achieved lock with fOSCIN.
REGISTER 0x02—POWER-DOWN Unused sections of the chip can be powered down when the
corresponding bits are set high. This register has a default value
of 0x00, all sections active.
Bit 0: Power Down ADC12B Voltage Reference
Bit 1: Power Down ADC12A Voltage Reference Active high powers down the voltage reference circuit for
the ADC12A.
Bit 2: Power Down ADC10 Active high powers down the 10-bit ADC.
Bit 3: Power Down ADC12B Active high powers down the ADC12B.
Bit 4: Power Down ADC12A Active high powers down the ADC12A.
Bit 5: Power Down Tx Active high powers down the digital transmit section of the
chip, similar to the function of the PWRDN pin.
Bit 6: Power Down DAC Tx Active high powers down the DAC.
Bit 7: Power Down PLL Active high powers down the OSCIN multiplier.
REGISTER 0x03—FLAG CONTROL
Bit 0: Flag 0 Enable When this bit is active high, the SIGDELT pin maintains a fixed
logic level determined directly by the MSB of the ∑-∆ control
word of Register 0x04.
Bit 1: Flag 1 The logic level of this bit is applied at the FLAG1 pin.
Bit 4: Flag 2 The logic level of this bit is applied at the FLAG2 pin.
Bit 5: Video Input into ADC12B If the video input is enabled, setting this bit high sends the
signal applied to the VIDEO IN pin to the ADC12B. Otherwise,
the signal applied to the VIDEO IN pin is sent to the ADC12A.
REGISTER 0x04—∑-∆ CONTROL WORD
Bits [7:0]: ∑-∆ Control Word The ∑-∆ control word is 8 bits wide and controls the duty cycle
of the digital output on the SIGDELT pin. Changes to the ∑-∆
control word take effect immediately for every register write.
∑-∆ output control words have a default value of 0. The control
words are in straight binary format, with 0x00 corresponding to
the bottom of scale or 0% duty cycle, and 0xFF corresponding
to the top of scale or near 100% duty cycle.
Bit 7: Flag 0 (∑-∆ Control Word MSB) When the Flag 0 enable bit (Register 0x03, Bit 0) is set, the logic
level of this bit appears on the output of the SIGDELT pin.
REGISTER 0x07—VIDEO INPUT CONFIGURATION
Bits [6:0]: Clamp Level Control Value The 7-bit clamp-level control value is used to set an offset to the
automatic clamp-level control loop. The actual ADC output has a
clamp-level offset equal to 16 times the clamp level control value. --ValueControlLevelClampOffsetLevelClamp=
The default value for the clamp-level control value is 0x20. This
results in an ADC output clamp-level offset of 512 LSBs. The
valid programming range for the clamp-level control value is
0x16 to 0x127.
Bit 7: Video Input Enable This bit enables the video input. In default with Bit 7 = 0, both
IF12 ADCs are connected to IF inputs. If the video input is
enabled by setting bit 7 = 1, the video input will be connected to
the IF12 ADC selected by REG 0x03, Bit 6.
REGISTER 0x08—ADC CLOCK CONFIGURATION
Bit 0: Send ADC12B Data Only When this bit is set high, the device enters a nonmultiplexed
mode, and only the data from the ADC12B is sent to the
IF[11:0] digital output port.
Bit 1: Send ADC12A Data Only When this bit is set high, the device enters a nonmultiplexed
mode, and only the data from the ADC12A is sent to the
IF[11:0] digital output port.
If both the send ADC12B data only and send ADC12A data
only register bits are set high, the device sends both ADC12A
and ADC12B data in the default multiplexed mode.
Bit 3: Power Down ADC10 Voltage Reference Active high powers down the voltage reference circuit for
the ADC10.
Bit 4: Power Down RxSYNC Generator Setting this bit to 1 powers down the 10-bit ADC’s sampling
clock and makes the RxSYNC output pin stay low. It can be
used for additional power saving on top of the power-down
selections in Register 0x02.
Bit 5: Rx PORT Fast Edge Rate Setting this bit to 1 increases the output drive strength of all digital
output pins, except MCLK, REFCLK, SIGDELT, and
FLAG[2:1]. These pins always have high output drive capability.
Bit 7: ADC Clocked Directly from OSCIN When set high, the ADC sampling clock is derived directly from
the input clock at OSCIN. In this mode, the clock supplied to the
OSCIN pin should originate from an external crystal or low jitter
crystal oscillator. When this bit is low, the ADC sampling clock
is derived from the internal PLL and the frequency of the clock
REGISTER 0x0C—DIE REVISION
Bits [3:0]: Version The die version of the chip can be read from this register.
REGISTER 0x0D—Tx FREQUENCY TUNING WORDS
LSBs This register accommodates the 2 LSBs for each frequency tuning
word (FTW). See the Registers 0x10 Through 0x17—
Burst Parameter section.
REGISTER 0x0E—DAC GAIN CONTROL This register allows the user to program the DAC gain if the
Tx Gain Control Select Bit 3 in Register 0x0F is set to 0.
Table 5. DAC Gain Control
Bits [3:0] DAC Gain (dB)
REGISTER 0x0F—Tx PATH CONFIGURATION
Bit 0: Single Tone Tx Mode Active high configures the AD9878 for single-tone applications
(e.g., FSK). The AD9878 supplies a single frequency output, as
determined by the FTW selected by the active profile. In this
mode, the TxIQ input data pins are ignored, but should be tied
to a valid logic voltage level. Default value is 0x00 (inactive).
Bit 1: Spectral Inversion Tx When set to 1, inverted modulation is performed: sincos_tQtOUTMODULATOR+
Default is Logic 0, noninverted modulation: )sincos_tQtOUTMODULATOR−ω
Bit 2: Bypass Inv Sinc Tx Filter Active high configures the AD9878 to bypass the sin(x)/x com-
pensation filter. Default value is 0x00 (inverse sinc filter enabled).
Bit 3: CA Interface Mode Select This bit changes the format of the AD9878 3-wire CA interface to
a format in which the AD9878 digitally interfaces to external
variable gain amplifiers. This is accomplished by changing
the interpretation of the bits in Register 0x13, Register 0x17,
Register 0x1B, and Register 0x1F. See the Cable-Driver Gain
Setting this bit to 0 (default) configures the serial interface to be
compatible with AD8321/AD8323/AD8328 variable cable gain
amplifiers. Setting this bit to 1 configures the serial interface to be
compatible with AD8322/AD8327 variable cable gain amplifiers.
Bit 5: Profile Select The AD9878 quadrature digital upconverter can store two
preconfigured modulation modes, called profiles. Each profile
defines a transmit FTW, cable-driver amplifier gain setting, and
DAC gain setting. The profile select bit or PROFILE pin programs
the current register profile to be used. If the PROFILE pin is used
to switch between profiles, the profile select bit should be set to 0
and tied low.
REGISTERS 0x10 THROUGH 0x17—
BURST PARAMETER
Tx Frequency Tuning Words The FTW determines the DDS-generated carrier frequency (fC)
and is formed via a concatenation of register addresses.
The 26-bit FTW is spread over four register addresses. Bit 25 is
the MSB, and Bit 0 is the LSB. The carrier frequency equation is
as follows: 262SYSCLKCfFTWf×=
Where 2000x0and,<×=FTWfMfOSCINSYSCLK.
Changes to FTW bytes take effect immediately.
Cable-Driver Gain Control The AD9878 has a 3-pin interface to the AD832x family of
programmable gain cable-driver amplifiers. This allows direct
control of the cable driver’s gain through the AD9878. In its
default mode, the complete 8-bit register value is transmitted
over the 3-wire cable amplifier (CA) interface.
If Bit 3 of Register 0x0F is set high, Bits [7:4] of Register 0x13
and Register 0x17 determine the 8-bit word sent over the CA
interface, according to the specifications in Table 6. Bits [3:0] of
Register 0x13 and Register 0x17 determine the fine gain setting
of the DAC output, according to specifications in Table 7.
Table 6. Cable-Driver Gain Control
Table 7. DAC Output Fine Gain Setting New data is automatically sent over the 3-wire CA interface
(and DAC gain adjust) whenever the value of the active gain
control register changes or a new profile is selected. The default
value is 0x00 (lowest gain).
The formula for the combined output-level calculation of
AD9878 fine gain and AD8327 or AD8322 coarse gain is: )()19098788327−+coarsefineVV )14098788322−+fineVV
where:
fine is the decimal value of Bits [3:0].
coarse is the decimal value of Bits [7:4].
V9878(0) is the level at AD9878 output in dBmV for fine = 0.
V8327 is the level at output of AD8327 in dBmV.
V8322 is the level at output of AD8322 in dBmV.
SERIAL INTERFACE FOR REGISTER CONTROL The AD9878 serial port is a flexible, synchronous, serial
communications port that allows easy interface to many
industry-standard microcontrollers and microprocessors.
The interface allows read/write access to all registers that
configure the AD9878. Single or multiple byte transfers are
supported. Also, the interface can be programmed to read words
either MSB first or LSB first. The AD9878 serial interface port
I/O can be configured to have one bidirectional I/O (SDIO)
pin, or two unidirectional I/O (SDIO/SDO) pins.
GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases of a communication cycle with the AD9878.
Phase 1 is the instruction cycle, which is the writing of an in-
struction byte into the AD9878, coincident with the first eight
SCLK rising edges. The instruction byte provides the AD9878
serial port controller with information regarding the data transfer
cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is a read or write, the number of bytes in the data transfer,
and the starting register address for the first byte of the data
transfer. The first eight SCLK rising edges of each communication
cycle are used to write the instruction byte into the AD9878.
The eight remaining SCLK edges are for Phase 2 of the commu-
nication cycle. Phase 2 is the actual data transfer between the
AD9878 and the system controller. Phase 2 of the communication
cycle is a transfer of one to four data bytes, as determined by the
instruction byte. Normally, using one multibyte transfer is the
preferred method. However, single-byte data transfers are useful
to reduce CPU overhead when register access requires only one
byte. Registers change immediately upon writing to the last bit
of each transfer byte.
INSTRUCTION BYTE The R/W bit of the instruction byte determines whether a read
or a write data transfer occurs after the instruction byte write.
Logic high indicates a read operation; logic low indicates a write
operation. The [N1:N0] bits determine the number of bytes to
be transferred during the data transfer cycle. The bit decodes
are shown in Table 9. The timing diagrams are shown in Figure 19
and Figure 20.
Table 8. Instruction Byte Information
Table 9. Bit Decodes Bits [A4:A0] determine which register is accessed during the
data transfer portion of the communication cycle. For multi-
byte transfers, this address is the starting byte address. The
remaining register addresses are generated by the AD9878.
SCLK
SDIO
Figure 19. Timing Diagram for Register Write
SCLK
SDIO
SDO
Figure 20. Timing Diagram for Register Read
SERIAL INTERFACE PORT PIN DESCRIPTIONS SCLK—Serial Clock. The serial clock pin is used to synchronize
data transfers from the AD9878 and to run the serial port state
machine. The maximum SCLK frequency is 15 MHz. Input data
to the AD9878 is sampled up on the rising edge of SCLK. Output
data changes upon the falling edge of SCLK.
CS—Chip Select. Active low input starts and gates a commu-
nication cycle. It allows multiple devices to share a common
serial port bus. The SDO and SDIO pins go into a high impedance
state when CS is high. Chip select should stay low during the
entire communication cycle.
SDIO—Serial Data I/O. Data is always written into the AD9878
on this pin. However, this pin can be used as a bidirectional
data line. The configuration of this pin is controlled by Bit 7 of
Register 0x00. The default is Logic 0, which configures the SDIO
pin as unidirectional.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In
the case where the AD9878 operates in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
