AD9876BST Fast Delivery |IC PHOENIX CO.,LIMITED

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AD9876BST
Broadband Modem Mixed-Signal Front End
REV. A
Broadband Modem
Mixed-Signal Front End
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD9876 is a single-supply broadband modem mixed-signal
front end (MxFE) IC. The device contains a transmit path
interpolation filter and DAC and a receive path PGA, LPF, and
ADC supporting a variety of broadband modem applications.
Also on-chip is a PLL clock multiplier that provides all required
clocks from a single crystal or clock input. The AD9876 provides
12-bit converter performance on both the Tx and Rx path.
The TxDAC+ uses a selectable digital 2× or 4× interpolation
low-pass or band-pass filter to further oversample transmit data
and reduce the complexity of analog reconstruction filtering.
The transmit path signal bandwidth can be as high as 26 MHz
at an input data rate of 64MSPS. The 12-bit DAC provides
differential current outputs for optimum noise and distortion
performance. The DAC full-scale current can be adjusted from
2 to 20mA by a single resistor, providing 20dB of additional
gain range.
The receive path consists of a PGA, LPF, and ADC. The PGA has
a gain range of –6 dB to +36 dB, programmable in 2 dB steps,
adding 42 dB of dynamic range to the receive path. The receive
MxFE is a trademark of Analog Devices, Inc.
TxDAC+ is a registered trademark of Analog Devices, Inc.
path LPF cutoff frequency can be programmed to either 12 MHz
or 26 MHz. The filter cutoff frequency can also be tuned or
bypassed where filter requirements differ. The 12-bit ADC uses
a multistage differential pipeline architecture to achieve excellent
dynamic performance with low power consumption.
The AD9876 provides a voltage regulator controller (VRC) that
can be used with an external power MOSFET transistor to form
a cost-effective 1.3 V linear regulator.
The digital transmit and receive ports are each multiplexed to a
bus width of six bits and are clocked at a frequency of twice the
12-bit word rate.
The AD9876 ADC and/or DAC can also be used at sampling
rates as high as 64 MSPS in a 6-bit resolution nonmulti-
plexed mode.
The AD9876 is pin compatible with the 10-bit AD9875. Both are
available in a space-saving 48-lead LQFP package. They are speci-
fied over the industrial (–40°C to +85°C) temperature range.
FEATURES
Low Cost 3.3 V CMOS Mixed-Signal Front End (MxFE™)
Converter for Broadband Modems
10-/12-Bit D/A Converter (TxDAC+®)
64/32 MSPS Input Word Rate
2�/4� Interpolating LPF or BPF Transmit Filter
128 MSPS DAC Output Update Rate
Wide (26 MHz) Transmit Bandwidth
Power-Down Mode
10-/12-Bit 50 MSPS A/D Converter
Fourth Order Low-Pass Filter 12 MHz or 26 MHz
with Bypass
–6 dB to +36 dB Programmable Gain Amplifier
Internal Clock Multiplier (PLL)
Clock Outputs
Voltage Regulator Controller
48-Lead LQFP Package
APPLICATIONS
Powerline Networking
Home Phone Networking
xDSL
Broadband Wireless
Home RF
AD9876–SPECIFICATIONS
(VS = 3.3 V �10%, fOSCIN = 32 MHz, fDAC = 128 MHz, Gain = –6 dB, RSET = 4.02 k�,
100 � DAC single-ended load, unless otherwise noted. )
AD9876
AD9876
SERIAL CONTROL BUS
CMOS LOGIC INPUTS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9876 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
Power Supply (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Digital Inputs . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V
Analog Inputs . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this speciﬁcation is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
EXPLANATION OF TEST LEVELSDevices are 100% production tested at 25°C and guaran-
teed by design and characterization testing for industrial
operating temperature range (–40°C to +85°C).–Parameter is guaranteed by design and/or characteriza-
tion testing.
III –Parameter is a typical value only.
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP
�JA = 57°C/W
�JC = 28°C/W
ORDERING GUIDE
AD9876
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
DEFINITIONS OF SPECIFICATIONS
CLOCK JITTER
The clock jitter is a measure of the intrinsic jitter of the PLL
generated clocks. It is a measure of the jitter from one rising
and of the clock with respect to another edge of the clock nine
cycles later.
DIFFERENTIAL NONLINEARITY ERROR
(DNL, NO MISSING CODES)
An ideal converter exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicates that all 1024
codes, respectively, must be present over all operating ranges.
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
PHASE NOISE
Single-sideband phase noise power density is specified relative to
the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the
carrier. Phase noise can be measured directly on a generated
single tone with a spectrum analyzer that supports noise marker
measurements. It detects the relative power between the carrier
and the offset (1 kHz) sideband noise and takes the resolution
bandwidth (rbw) into account by subtracting 10 log(rbw). It also
adds a correction factor that compensates for the implementation
of the resolution bandwidth, log display, and detector characteristic.
OUTPUT COMPLIANCE RANGE
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation, resulting in nonlinear per-
formance or breakdown.
SPURIOUS–FREE DYNAMIC RANGE (SFDR)
The difference, in dB, between the rms amplitude of the DACs
output signal (or ADCs input signal) and the peak spurious
signal over the specified bandwidth (Nyquist bandwidth, unless
otherwise noted).
PIPELINE DELAY (LATENCY)
The number of clock cycles between conversion initiation and
the associated output data being made available.
OFFSET ERROR
First transition should occur for an analog value 1/2 LSB above
negative full scale. Offset error is defined as the deviation of the
actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last transition should occur for an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between the first and
last code transitions and the ideal difference between the first
and last code transitions.
INPUT REFERRED NOISE
The rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in LSB
and converted to an equivalent voltage. This results in a noise
figure that can be directly referred to the Rx input of the AD9876.
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
SINAD is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula:
it is possible to get a measure of performance expressed as N,
the effective number of bits.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
POWER SUPPLY REJECTION
Power supply rejection specifies the converters maximum
full-scale change when the supplies are varied from nominal to
minimum and maximum specified voltages.
AD9876
–Typical Tx Digital Filter Performance Characteristics
TPC 1.4� Low-Pass Interpolation Filter
TPC 2.2� Low-Pass Interpolation Filter
TPC 3.4� Band-Pass Interpolation Filter, fS /2 Modula-
tion, Adjacent Image Preserved
TPC 4.2� Band-Pass Interpolation Filter, fS /2 Modula-
tion, Adjacent Image Preserved
TPC 5.4� Band-Pass Interpolation Filter, fS /4 Modulation,
Lower Image Preserved
TPC 6.4� Band-Pass Interpolation Filter, fS /4 Modulation,
Upper Image Preserved
TPC 7.Single-Tone Spectral Plot @ fDATA = 32 MSPS,
fOUT = 5 MHz, 4� LPF
TPC 8.Single-Tone Spectral Plot @ fDATA = 50 MSPS,
fOUT = 11 MHz, 2� LPF
TPC 10.Out-of-Band SFDR vs. fOUT @ fDATA = 32 MSPS
and 50 MSPS
TPC 11.In-Band SFDR vs. fOUT @ fDATA = 32 MSPS
and 50 MSPS
Typical AC Characteristics Curves for TxDAC+( (RSET = 4.02 k�, RDAC = 100 �)
AD9876
Typical AC Characteristics Curves for TxDAC(RSET = 4.02 k�, RDAC = 100 �)
TPC 13.Phase Noise Plot @ fDATA = 32 MSPS,
fOUT = 10 MHz, 4� LPF
TPC 14.Phase Noise Plot @ fDATA = 50 MSPS,
fOUT = 10 MHz, 2� LPF
TPC 15.In-Band Multitone Spectral Plot
@ fDATA = 50 MSPS, fOUT = k � 195 kHz, 2� LPF
TPC 16.Wideband Multitone Spectral Plot
@ fDATA = 50MSPS, fOUT = k �195 kHz, 2� LPF
TPC 17.Rx vs. Tuning Target, fADC = 32 MHz,
LPF with Wideband Rx LPF = 1
TPC 18.PGA Gain Error vs. Gain
Typical Tx Digital Filter Performance Characteristics
TPC 19.fC vs. Tuning Target, fADC = 32 MHz,
LPF with Wideband Rx LPF = 0
TPC 20.PGA Gain Step Size vs. Gain
AD9876
TPC 21.Rx LPF Frequency Response, Low fC
Nominal Tuning Targets
TPC 22.Rx LPF Frequency Response, High fC
Nominal Tuning Targets
TPC 23.Rx LPF Frequency Response, Low fC
Typical AC Characterization Curves for Rx Path
TPC 24.Rx LPF Group Delay, Low fC Nominal
Tuning Targets
TPC 25.Rx LPF Group Delay, High fC, Nominal
Tuning Targets
TPC 26.Rx LPF Group Delay, Low fC, 0 � 60 and

Partno	Mfg	Dc	Qty	Available	Descript
AD9876BST	AD	N/a	834	avai	Broadband Modem Mixed-Signal Front End