AD9874ABST ,Low Power IF Digitizing SubsystemSPECIFICATIONS (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 V to 3.6 V,1VDDQ = VDDP = 2.7 ..
AD9874BST ,IF Digitizing SubsystemSPECIFICATIONS (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 to 3.6 V,1VDDQ = VDDP = 2.7 V ..
AD9876BST ,Broadband Modem Mixed-Signal Front Endapplications. dynamic performance with low power consumption.Also on-chip is a PLL clock multiplier ..
AD9877ABS ,Single Supply Cable Modem/Set Top Box Mixed Signal Front EndGENERAL DESCRIPTION The 12-bit ADC has excellent undersampling performance,The AD9877 is a single-s ..
AD9878BSTZ ,Mixed-Signal Front End for Broadband ApplicationsGENERAL DESCRIPTION The AD9878 is a single-supply, cable modem/set-top box, The 12-bit ADCs provide ..
AD9879BS ,Mixed Signal Front End Set Top Box, Cable ModemGENERAL DESCRIPTION The 12-bit and 10-bit IF ADCs can convert direct IF inputs upThe AD9879 is a si ..
ADSP-21060LAB-160 ,ADSP-2106x SHARC DSP Microcomputer Familyfeatures:DR1BR1-6ADDRRPBAComputation Units (ALU, Multiplier and Shifter) with a CPAID2-0 DATAShared ..
ADSP-21060LAB-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyCHARACTERISTICS (3.3 V) . . . . . . . . . . 15Figure 16. Synchronous Read/Write—Bus Slave . . . . . ..
ADSP-21060L-KB-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyFEATURES40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction4 Mbit On-Chip SRAMExecutionDual-P ..
ADSP-21060LKB-160 ,ADSP-2106x SHARC DSP Microcomputer Familyfeatures:DR1BR1-6ADDRRPBAComputation Units (ALU, Multiplier and Shifter) with a CPAID2-0 DATAShared ..
ADSP-21060LKS-133 ,ADSP-2106x SHARC DSP Microcomputer FamilyApplications225 PBGA PackageSuper Harvard Architecture32-Bit Single-Precision and 40-Bit Extended-P ..
ADSP-21060LKS-160 ,ADSP-2106x SHARC DSP Microcomputer Familyfeaturesof the ADSP-21000 family core. The ADSP-21060 is code- andfunction-compatible with the ADSP ..
AD9874ABST
Low Power IF Digitizing Subsystem
REV.A
IF Digitizing Subsystem*. Patent No. 5,969,657; other patents pending.
FEATURES
10 MHz to 300 MHz Input Frequency
7.2 kHz to 270 kHz Output Signal Bandwidth
8.1 dB SSB NF
0 dBm IIP3
AGC Free Range up to –34 dBm
12 dB Continuous AGC Range
16 dB Front End Attenuator
Baseband I/Q 16-Bit (or 24-Bit) Serial Digital Output
LO and Sampling Clock Synthesizers
Programmable Decimation Factor, Output Format,
AGC, and Synthesizer Settings
370 � Input Impedance
2.7 V to 3.6 V Supply Voltage
Low Current Consumption: 20 mA
48-Lead LQFP Package (1.4 mm Thick)
APPLICATIONS
Multimode Narrow-Band Radio Products
Analog/Digital UHF/VHF FDMA Receivers
TETRA, APCO25, GSM/EDGE
Portable and Mobile Radio Products
Base Station Applications
SATCOM Terminals
GENERAL DESCRIPTIONThe AD9874 is a general-purpose IF subsystem that digitizes a
low level 10 MHz to 300 MHz IF input with a signal bandwidth
ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9874
consists of a low noise amplifier, a mixer, a band-pass sigma-delta
analog-to-digital converter, and a decimation filter with program-
mable decimation factor. An automatic gain control (AGC) circuit
gives the AD9874 12 dB of continuous gain adjustment. Auxil-
iary blocks include both clock and LO synthesizers.
The AD9874’s high dynamic range and inherent antialiasing
provided by the band-pass sigma-delta converter allow the
AD9874 to cope with blocking signals up to 95 dB stronger
than the desired signal. This attribute can often reduce the cost of
a radio by reducing its IF filtering requirements. Also, it enables
multimode radios of varying channel bandwidths, allowing the
IF filter to be specified for the largest channel bandwidth.
The SPI port programs numerous parameters of the AD9874,
thus allowing the device to be optimized for any given application.
Programmable parameters include synthesizer divide ratios, AGC
attenuation and attack/decay time, received signal strength level,
decimation factor, output data format, 16dB attenuator, and the
selected bias currents. The bias currents of the LNA and mixer
can be further reduced at the expense of degraded performance
for battery-powered applications.
FUNCTIONAL BLOCK DIAGRAM
AD9874
TABLE OF CONTENTSAD9874—SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . .3
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . .5
PIN CONFIGURATION/DESCRIPTION . . . . . . . . . . . . .6
DEFINITION OF SPECIFICATIONS/
TEST METHODS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
TYPICAL PERFORMANCE CHARACTERISTICS . . . . .8
SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . .13
SYNCHRONOUS SERIAL INTERFACE (SSI) . . . . . . . .16
Synchronization Using SYNCB . . . . . . . . . . . . . . . . . . . .18
Interfacing to DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
POWER CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
LO SYNTHESIZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Fast Acquire Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
CLOCK SYNTHESIZER . . . . . . . . . . . . . . . . . . . . . . . . . .21
IF LNA/MIXER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
BAND-PASS SIGMA DELTA (�-�) ADC . . . . . . . . . . . .24
DECIMATION FILTER . . . . . . . . . . . . . . . . . . . . . . . . . .26
VARIABLE GAIN AMPLIFIER WITH AGC . . . . . . . . . .28
Variable Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . .29
System NF vs. VGA Control . . . . . . . . . . . . . . . . . . . . . .31
APPLICATION CONSIDERATIONS . . . . . . . . . . . . . . .32
Frequency Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Spurious Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
EXTERNAL PASSIVE COMPONENT
REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Superheterodyne Receiver . . . . . . . . . . . . . . . . . . . . . . . .34
Synchronization of Multiple AD9874s . . . . . . . . . . . . . . .36
Split Path Rx Architecture . . . . . . . . . . . . . . . . . . . . . . . .37
Hung Mixer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
LAYOUT EXAMPLE
EVALUATION BOARD AND SOFTWARE . . . . . . . . .38
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .39
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
AD9874–SPECIFICATIONSLO SYNTHESIZER
NOTESStandard operating mode: LNA/Mixer @ high bias setting, VGA @ Min ATTEN setting, synthesizers in normal (not fast acquire) mode, fCLK = 18 MHz, decimation
factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.This includes 0.9 dB loss of matching network.AGC with DVGA enabled.Measured in 10 kHz bandwidth.
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 V to 3.6 V,
VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS, fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted.)1
AD9874
DIGITAL SPECIFICATIONS(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V,
fCLK = 18 MSPS, fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted.)1SPI-WRITE OPERATION
CMOS LOGIC INPUTS
NOTESStandard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, fCLK = 18 MHz, decimation factor = 300, 10 pF load on SSI output pins:
VDDx = 3.0 V.Programmable in steps of 48 or 60.CMOS output mode with CLOAD = 10 pF and Drive Strength = 7.Absolute Max and Min input/output levels are VDDH +0.3 V and –0.3 V.IOL = 1 mA; specification is also dependent on Drive Strength setting.
Specifications subject to change without notice.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS**Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
ORDERING GUIDE
EXPLANATION OF TEST LEVELS
TEST LEVEL100% production tested.
II.100% production tested at 25°C and sample tested at
specified temperatures. AC testing done on sample basis.
III.Sample tested only.
IV.Parameter is guaranteed by design and/or
characterization testing.Parameter is a typical value only.
VI.All devices are 100% production tested at 25°C; min and
max guaranteed by design and characterization for industrial
temperature range.
THERMAL CHARACTERISTICS
Thermal Resistance48-Lead LQFP
�JA = 76.2°C/W
�JC = 17°C/W
