AD9873JS ,Analog Front End Converter for Set-Top Box, Cable ModemCharacteristics . . . . . . . . . . . 18 Op Amp Selection Guide . . . . . . . . . . . . . . . . . . ..
AD9874ABST ,Low Power IF Digitizing SubsystemSPECIFICATIONS (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 V to 3.6 V,1VDDQ = VDDP = 2.7 ..
AD9874BST ,IF Digitizing SubsystemSPECIFICATIONS (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 to 3.6 V,1VDDQ = VDDP = 2.7 V ..
AD9876BST ,Broadband Modem Mixed-Signal Front Endapplications. dynamic performance with low power consumption.Also on-chip is a PLL clock multiplier ..
AD9877ABS ,Single Supply Cable Modem/Set Top Box Mixed Signal Front EndGENERAL DESCRIPTION The 12-bit ADC has excellent undersampling performance,The AD9877 is a single-s ..
AD9878BSTZ ,Mixed-Signal Front End for Broadband ApplicationsGENERAL DESCRIPTION The AD9878 is a single-supply, cable modem/set-top box, The 12-bit ADCs provide ..
ADSP-21060LAB-160 ,ADSP-2106x SHARC DSP Microcomputer Familyfeatures:DR1BR1-6ADDRRPBAComputation Units (ALU, Multiplier and Shifter) with a CPAID2-0 DATAShared ..
ADSP-21060LAB-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyCHARACTERISTICS (3.3 V) . . . . . . . . . . 15Figure 16. Synchronous Read/Write—Bus Slave . . . . . ..
ADSP-21060L-KB-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyFEATURES40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction4 Mbit On-Chip SRAMExecutionDual-P ..
ADSP-21060LKB-160 ,ADSP-2106x SHARC DSP Microcomputer Familyfeatures:DR1BR1-6ADDRRPBAComputation Units (ALU, Multiplier and Shifter) with a CPAID2-0 DATAShared ..
ADSP-21060LKS-133 ,ADSP-2106x SHARC DSP Microcomputer FamilyApplications225 PBGA PackageSuper Harvard Architecture32-Bit Single-Precision and 40-Bit Extended-P ..
ADSP-21060LKS-160 ,ADSP-2106x SHARC DSP Microcomputer Familyfeaturesof the ADSP-21000 family core. The ADSP-21060 is code- andfunction-compatible with the ADSP ..
AD9873JS
Analog Front End Converter for Set-Top Box, Cable Modem
REV.0
Analog Front End Converter for
Set-Top Box, Cable Modem
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low-Cost 3.3 V CMOS Analog Front End Converter for
MCNS-DOCSIS, DVB, DAVIC-Compliant
Set-Top Box, Cable Modem Applications
232 MHz Quadrature Digital Upconverter
DC to 65 MHz Output Bandwidth
12-Bit Direct IF D/A Converter (TxDAC+®)
Programmable Reference Clock Multiplier (PLL)
Direct Digital Synthesis
Interpolator
SIN(x)/x Compensation Filter
Four Programmable, Pin-Selectable Modulator Profiles
Single-Tone Mode for Frequency Synthesis Applications
12-Bit, 33 MSPS Sampling Direct IF A/D Converter with
Auxiliary Automatic Clamp Video Input Multiplexer
10-Bit, 33 MSPS Sampling Direct IF A/D Converter
Dual 8-Bit, 16.5 MSPS Sampling IQ A/D Converter
Two Independently Programmable Sigma-Delta
Converters
Direct Interface to AD8321/AD8323 PGA Cable Driver
Programmable Frequency Output
Power-Down Modes
APPLICATIONS
Cable and Satellite Systems
PC Multimedia
Digital Communications
Data and Video Modems
Cable Modem
Set-Top Boxes
Powerline Modem
Broadband Wireless Communication
GENERAL DESCRIPTIONThe AD9873 integrates a complete 232 MHz quadrature
digital transmitter and a multichannel receiver with four high-
performance analog-to-digital converters (ADC) for various
video and digital data signals. The AD9873 is designed for cable
modem set-top box applications, where cost, size, power dissi-
pation, and dynamic performance are critical attributes. A single
external crystal is used to control all internal conversion and
data processing cycles.
The transmit section of the AD9873 includes a high-speed
direct digital synthesizer (DDS), a high-performance, high-speed
12-bit digital-to-analog converter (DAC), programmable clock
multiplier circuitry, digital filters, and other digital signal
processing functions, to form a complete quadrature digital
up-converter device.
On the receiver side, two 8-bit ADCs are optimized for IQ
demodulated “out-of band” signals. An on-chip 10-bit ADC
is typically used as a direct IF input of 256 QAM modulated
signals in cable modem applications. A second direct IF input
and an auxiliary video input with automatic programmable clamp
function are multiplexed to a high-performance 12-bit video ADC.
The chip’s programmable sigma-delta modulated outputs and
an output clock may be used to control external components
such as programmable gain amplifiers (PGA) and mixer stages.
Three pins provide a direct interface to the AD8321/AD8323
programmable gain amplifier (PGA) cable driver.
The AD9873 is available in a space-saving 100-lead MQFP package.
TxDAC+ is a registered trademark of Analog Devices, Inc.
AD9873
PageFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 7
THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . 7
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . 7
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DEFINITIONS OF TERMS . . . . . . . . . . . . . . . . . . . . . . . 8
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 9
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . 10
REGISTER BIT DEFINITIONS . . . . . . . . . . . . . . . . . . . 12
TYPICAL PERFORMANCE CHARACTERISTICS . . . 14
Typical Power Consumption Characteristics . . . . . . . . . 14
Dual Sideband Transmit Spectrum . . . . . . . . . . . . . . . . 14
Single Sideband Transmit Spectrum . . . . . . . . . . . . . . . 15
Typical QAM Transmit Performance Characteristics . . 16
Typical ADC Performance Characteristics . . . . . . . . . . . 18
THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . 20
Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
OSC IN Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . 21
Receive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CLOCK AND OSCILLATOR CIRCUITRY . . . . . . . . . . 22
PROGRAMMABLE CLOCK OUTPUT REF CLK . . . . 23
SIGMA-DELTA OUTPUTS . . . . . . . . . . . . . . . . . . . . . . 23
SERIAL INTERFACE FOR REGISTER CONTROL . . . 23
General Operation of the Serial Interface . . . . . . . . . . . . 23
Instruction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial Interface Port Pin Description . . . . . . . . . . . . . . . 24
MSB/LSB Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Notes on Serial Port Operation . . . . . . . . . . . . . . . . . . . 24
PageTRANSMIT PATH (Tx) . . . . . . . . . . . . . . . . . . . . . . . . . 24
Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Half-Band Filters (HBFs) . . . . . . . . . . . . . . . . . . . . . . . 25
Cascaded Integrator—COMB (CIC) Filter . . . . . . . . . . 25
Combined Filter Response . . . . . . . . . . . . . . . . . . . . . . . 25
Inverse SINC Filter (ISF) . . . . . . . . . . . . . . . . . . . . . . . 27
Tx Signal Level Considerations . . . . . . . . . . . . . . . . . . . 28
Tx Throughput and Latency . . . . . . . . . . . . . . . . . . . . . 28
D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PROGRAMMING/WRITING THE AD8321/AD8323
CABLE DRIVER AMPLIFIER GAIN CONTROL . . . 29
RECEIVE PATH (Rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ADC Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . 30
Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Driving the Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . 30
Op Amp Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . 31
ADC Differential Inputs . . . . . . . . . . . . . . . . . . . . . . . . 31
ADC Voltage References . . . . . . . . . . . . . . . . . . . . . . . . 31
Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
POWER AND GROUNDING CONSIDERATIONS . . . 32
EVALUATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . 33
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 39
TABLE OF CONTENTS
AD9873(VAS = 3.3V � 5%, VDS = 3.3V � 10%, fOSCIN = 27MHz, fSYSCLK = 216MHz, fMCLK = 54MHz
(M = 8, N = 4), ADC Sample Rate derived from PLL fMCLK , RSET = 10k�, 75� DAC Load)
SPECIFICATIONS
AD9873–SPECIFICATIONS10-BIT ADC CHARACTERISTICS
12-BIT ADC CHARACTERISTICS
AD9873
