AD9870AST ,IF Digitizing SubsystemSPECIFICATIONS VDDP = 5.0 V, CLK = 18 MSPS, F = 73.35 MHz, F = 71.1 MHz, unless otherwise noted.)IF ..
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AD9874BST ,IF Digitizing SubsystemSPECIFICATIONS (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 to 3.6 V,1VDDQ = VDDP = 2.7 V ..
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ADSP21060KS-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyFEATURES40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction4 Mbit On-Chip SRAMExecutionDual-P ..
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AD9870AST
IF Digitizing Subsystem
REV.0
IF Digitizing Subsystem
FUNCTIONAL BLOCK DIAGRAM
FEATURES
10 MHz–300MHz Input Frequency
Baseband (I/Q) Digital Output
10 kHz–150 kHz Output Signal Bandwidth
12 dB SSB NF
> –1 dBm IIP3 (High IIP3 Mode)
25 dB Continuous AGC Range + 16 dB Gain Step
Support for LO and Sampling Clock Synthesis
Programmable Decimation Rate, Output Format, AAF
Cutoff, AGC and Synthesizer Settings
360 � Input Impedance
2.7 V–3.6 V Supply Voltage
Low Current: 42mA Typ (High IIP3 Mode),mA Typ (Low IIP3, Fixed Gain Mode)
48-Lead LQFP Package (1.4 mm Thick)
APPLICATIONS
Portable and Mobile Radio Products
Digital UHF/VHF FDMA Products
TETRA
PRODUCT DESCRIPTIONThe AD9870 is a general-purpose IF subsystem that digitizes a
low-level 10 MHz–300MHz IF input with a bandwidth of up to
150kHz. The signal chain of the AD9870 consists of a low-noise
amplifier, a mixer, a variable gain amplifier with integral antialias
filter, a bandpass sigma-delta analog-to-digital converter, and a
decimation filter with programmable decimation factor. An auto-
matic gain control (AGC) circuit provides the AD9870 withdB of continuous gain adjustment. The high dynamic range
of the bandpass sigma-delta converter allows the AD9870 to
cope with blocking signals that are as much as 70dB stronger
than the desired signal. Auxiliary blocks include clock and LO
synthesizers as well as a serial peripheral interface (SPI) port.
The SPI port programs numerous parameters of the AD9870,
including the synthesizer divide ratios, the AGC attack and decay
times, the AGC target signal level, the decimation factor, the
output data format, the 16dB attenuator, and the bias currents of
several blocks. Reducing bias currents allows the user to reduce
power consumption at the expense of reduced performance.
AD9870–SPECIFICATIONS
(VDDI = VDDF = VDDA = 3.3 V, VDDC = VDDL = 3.3 V, VDDD = VDDH = 3.3 V, VDDQ =
VDDP = 5.0 V, CLK = 18 MSPS, FIF = 73.35 MHz, FLO = 71.1 MHz, unless otherwise noted.)
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9870 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*Storage Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance48-Lead LQFP
θJA = 91°C/W
θJC = 28°C/W
ORDERING GUIDE
AD9870
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
GNDL
FREF
GNDS
SYNCB
GNDH
DOUTB
MXOP
MXON
GNDF
IF2N
IF2P
VDDF
GCP
GCN
VDDA
GNDA
VREFP
DOUTA
CLKOUT
VDDH
VDDD
VREFNPE
VDDIIFINCXIFGNDICXVLLOPLONCXVMVDDLVDDPIOUTLGNDP
VCM
VDDQ
IOUTC
GNDQ
VDDC
GNDC
CLKP
CLKNGNDS
GNDDPD
SERIAL PERIPHERAL INTERFACE (SPI)The Serial Peripheral Interface (SPI) is a bidirectional serial port. It is used to load configuration information into the registers listed
below as well as to read back their contents. TableI provides a list of the registers that may be programmed through the SPI port.
Addresses and default values are given in hexadecimal form.
Table I.SPI Address MapPOWER CONTROL REGISTERS
AGC
DECIMATION FACTOR
LO SYNTHESIZER
CLOCK SYNTHESIZER
AD9870CLOCK SYNTHESIZER (Continued)
SSI CONTROL
AAF CAPACITOR SETTING/CALIBRATION
TEST REGISTERS AND SPI PORT READ ENABLE
Figure 1.SPI Timing
Figure 1 illustrates the timing for the SPI port. After the periph-
eral enable (PE) signal goes low, data (PD) is read on the rising
edges of the clock (PC). The first bit is a read/not-write indica-
tor; the next six bits are address bits; the eighth bit is ignored;
the last eight bits are data. Address and data are given MSB first.
If the read/not-write indicator is a zero, a write operation occurs
and the data bits are shifted in. If the read/not-write indicator is
a one and if the read-back enable bit (Reg. 3A, Bit 3) has been
set, a read operation occurs and data is shifted out the data pin on
the falling edges of the clock. PE stays low during the operation
and goes high at the end of the transfer. If PE rises before an addi-
tional eightclock cycles have passed, the operation is aborted.
If PE stays low for an additional eight clock cycles, the destina-
tion address is incremented and another eight bits of data are
shifted in. Again, should PE rise early, the current byte is ignored.
By using this implicit addressing mode, the entire chip can be
configured with a single write operation. Registers identified as
being subject to frequent updates, namely those associated with
power control and AGC operation, have been assigned adjacent
addresses to minimize the time required to update them. The auto-
increment mode is not supported for read operations.
Multibyte registers are “big-endian” (the most significant byte
has the lower address) and are updated when a write to the least
significant byte occurs.
SYNCHRONOUS SERIAL INTERFACE (SSI)The primary output of the AD9870 is the converted signal, which
is available from the SSI port as a serial bit stream. The bit stream
consists of a 16-bit I word followed by a 16-bit Q word, where
each word is given MSB first and is in two’s-complement form.
AGC, signal strength, and synchronization information may also
be embedded in the data stream. The output bit rate (fCLKOUT)
is equal to the modulator clock frequency (fCLK) divided by
the contents of the SSIORD register. Users must verify that the
output bit rate is sufficient to accommodate the required num-
ber of bits per frame (see TableII) and that the chosen output
rate does not introduce harmful spurs. Idle (high) bits are used
to fill out each frame; the frame lengths listed in Table II
assume that with embedded frame sync (EFS = 1), at least 10
idle bits are desired.
Table II.Max Legal SSIORD Values for 16-Bit I/O Data and
Decimation by 60 n
Bits per Sample
(Min No. of Bits per Frame)*If the AAGC Bit of SSICRA is set.
Figure 2 illustrates the output timing of the SSI port for several
SSI control register settings. In the default mode of operation,
data is shifted out on rising edges of CLKOUT after a pulse is
output from the frame sync (FS) pin. As described above, the
output data consists of a 16-bit I sample followed by a 16-bit
Q sample plus two optional bytes containing AGC and status
information.
AD9870The two optional bytes are output if the EAGC bit of SSICRA
is set. The first byte contains the eight most significant bits of
the AGC DAC setting while the second byte contains a 2-bit
overload field, a 2-bit reset field, a 2-bit large-signal field, a zero
bit, and a trailing high bit. The overload, reset, and large-signal
fields contain the number of overload, reset, and large-signal
events since the last report, respectively, saturating at three
should the number of events equal or exceed this amount. The
two optional bytes follow the I and Q data as a 16-bit word
provided the AAGC bit of SSICRA is not set. If the AAGC bit
is set, the two bytes follow the I and Q data in an alternating
fashion. In this “alternate AGC data” mode, the LSB of the
byte containing the AGC DAC setting is zero; the LSB of the
byte containing reset/overload information is always a one.
Figure 3 illustrates the fields of the SSI data frames.
Figure 3.SSI Frame Structure
Figure 2.SSI Timing for Several SSICR Settings
When the embedded frame sync bit (EFS) is set, FS is either
low or in a high Z state (as determined by the SFST bit), and
framing information is embedded in the data stream. In this
mode, each eight bits of data are surrounded by a start bit (low)
and a stop bit (high), and each frame ends with at least 10 high
bits. Other control bits can be used to invert the frame sync (SFSI),
to delay the frame sync pulse by one clock period (SLFS), to invert
the clock (SCKI), or to set the clock (SCKT) to a high Z state.
Note that if EFS is set, SLFS is a don’t care.
The AD9870 also provides the means for controlling the switch-
ing characteristics of the digital output signals. With a 25pF
load, the rise and fall times of these signals are no more than
120ns, 45ns, 16ns, or 10ns if the DS (drive strength) setting
is 0, 1, 2, or 3, respectively.
Table III.SSI Control Registers
SSICRA (ADDR = 0x18)
SSICRB (ADDR = 0x19)
POWER CONTROLTo allow power consumption to be minimized, the AD9870
possesses numerous SPI-programmable power-down and bias
control bits.
Each major block may be powered down through the appropri-
ate bit of the STBY register. This scheme provides the greatest
flexibility for configuring the IC to a specific application as well
as for tailoring the IC’s power-down and wake-up characteristics.
Table IV summarizes the function of each of the STBY bits.
Note, when all the blocks are in standby, the master reference
circuit is also put into standby and thus the current is reduced
by a further 0.4 mA.
The AD9870 also allows control over the bias current in several
key blocks. The effects on current consumption and system
performance are described in the section dealing with the
affected block.
Table IV.Standby Control BitsNOTESWhen all blocks are in standby, the master reference circuit is also put into
standby and thus the current is reduced by a further 0.4 mA.Wake-up time is application-dependent.
LO SYNTHESIZERThe LO synthesizer shown in Figure 4 is a fully programmable
PLL capable of 6.25kHz resolution at input frequencies up to
300MHz and reference clocks of up to 25MHz. It consists of a
low-noise digital Phase-Frequency Detector (PFD), a variable
output current charge pump (CP), a 14-bit reference divider,
programmable A and B counters and a dual-modulus 8/9 pres-
caler. The A (3-bit) and B (13-bit) counters, in conjunction
with the dual 8/9 modulus prescaler, implement an N divider
with N = 8 × B + A. In addition, the 14-bit reference counter
(R Counter) allows selectable input reference frequencies, fREF,
at the PFD input. A complete PLL (Phase-Locked Loop) can
be implemented if the synthesizer is used with an external loop
filter and VCO (Voltage Controlled Oscillator).
AD9870The A, B, and R counters can be programmed via the following
registers: LOA, LOB, and LOR. The charge pump output current
is programmable via the LOI register from 0.625mA to 5.0mA
using the following equation: IPUMP = (LOI + 1) × 0.625 mA.
An on-chip lock detect function (enabled by the LOF bit) auto-
matically increases the output current for faster settling during
channel changes. The synthesizer may also be disabled using the
LO standby bit located in the STBY register.
Figure 4. LO Synthesizer
The LO (and CLK) Synthesizer works in the following manner.
The reference frequency, fREF, is buffered and divided by the
value held in the R counter. The internal FREF is then compared
to a divided version of the VCO frequency, fLO. The phase/
frequency detector provides UP and DOWN pulses whose width
vary depending upon the difference in phase and frequency of
its two input signals. The UP/DOWN pulses control the charge
pump, making current available to charge the external low-pass
loop filter when there is a discrepancy between the inputs of the
PFD. The output of the low-pass filter feeds an external VCO
whose output frequency, FLO, is driven such that its divided
down version, FLO, matches that of FREF thus closing the feed-
back loop.
The synthesized frequency is related to the reference frequency
and the LO register contents as follows:
fLO = (8 × LOB + LOA)/LOR × fREF
Note, the minimum allowable value in the LOB register is 3 and
its value must always be greater than that loaded into LOA. The
stability, phase noise, spur performance, and transient response
of the AD9870’s LO (and CLK) synthesizers are determined by
the external loop filter, the VCO, the N-divide factor, and the
reference frequency, fREF. An excellent reference book on PLL
synthesizers titled PLL Performance, Simulation and Design by Deen
Banerjee is available for free at www.national.com.
An example may help illustrate how the values of LOA, LOB,
and LOR can be selected. Consider an application employing a
13 MHz crystal oscillator (i.e., fREF = 13 MHz) with the re-
quirement that FREF = 100 kHz and fLO = 143 MHz (i.e.,
high-side injection with IF = 140.75 MHz and fSAMPLE = 18
MSPS). LOR is selected to be 130 such that fREF = 100 kHz.
The N-divider factor is 1430, which can be realized by select-
ing LOB = 178 and LOA = 6.
Figure 5 shows the equivalent input structures of the synthesiz-
ers’ LO and REF buffers (excluding the ESD structures). The
LO input is fed to the LO synthesizers buffer as well as the
AD9870’s mixer’s LO port. Both inputs are self-biasing and
thus tolerate ac-coupled inputs. The LO input can be driven
with a single-ended or differential signal. Single-ended dc-
coupled inputs should ensure sufficient signal swing above and
below the common-mode bias of the LO and REF buffers (i.e.,
1.38 V and VDDL/2).
Figure 5.Equivalent Input of LO and REF Buffers
Fast Acquire ModeThe fast acquire circuit attempts to boost the output current
when the phase difference between the divided-down LO (i.e., fLO)
and the divided-down reference frequency (i.e., fREF) exceeds
the threshold determined by the LOFA register. The LOFA
register specifies a divisor for the fREF signal, and it is the period
(T) of this divided-down clock that specifies the time interval
which controls the fast acquire algorithm.
Assume for the moment that the nominal charge pump current
is at its lowest setting (i.e., LOI = 0) and denote this minimum
current by I0. When the output pulse from the phase compara-
tor exceeds T, the output current for the next pulse is 2I0; when
the pulse is wider than 2T, the output current for the next pulse
is 3I0, and so forth, up to eight times the minimum output current.
If the nominal charge pump current is more than the minimum
value (i.e., LOI > 0), the preceding rule is only applied if it results
in an increase in the instantaneous charge pump current. If the
charge pump current is set to its lowest value (LOI = 0) and the
fast acquire circuit is enabled, the instantaneous charge pump
current will never fall below 2I0, even when the pulsewidth is
less than T. Thus the charge pump current when fast acquire is
enabled is given by
IPUMP-FA = IO × (1 + max (1, LOI, Pulsewidth/T)).
