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AD9865BCP-AD9865BCPZ-AD9865BCPZRL
10-Bit Broadband Modem Mixed Signal Front End
Broadband Modem Mixed-Signal Front EndRev. A
FEATURES
Low cost 3.3 V CMOS MxFETM for broadband modems
10-bit D/A converter
2×/4× interpolation filter
200 MSPS DAC update rate
Integrated 23 dBm line driver with 19.5 dB gain control
10-bit, 80 MSPS A/D converter
−12 dB to +48 dB low noise RxPGA (< 3.0 nV/rtHz)
Third order, programmable low-pass filter
Flexible digital data path interface
Half- and full-duplex operation
Backward-compatible with AD9975 and AD9875
Various power-down/reduction modes
Internal clock multiplier (PLL)
2 auxiliary programmable clock outputs
Available in 64-lead chip scale package or bare die
APPLICATIONS
Powerline networking
VDSL and HPNA
FUNCTIONAL BLOCK DIAGRAM _P+SPI
AGC[5:0]
RXCLK
RXE/SYNC
ADIO[9:4]/Tx[5:0]
ADIO[3:0]/Rx[5:0]
TXCLK
TXEN/SYNC
MODE
PWRDWN
Figure 1.
GENERAL DESCRIPTION The AD9865 is a mixed-signal front end (MxFE) IC for
transceiver applications requiring Tx and Rx path functionality
with data rates up to 80 MSPS. Its flexible digital interface,
power saving modes, and high Tx-to-Rx isolation make it well
suited for half- and full-duplex applications. The digital inter-
face is extremely flexible allowing simple interfaces to digital
back ends that support half- or full-duplex data transfers, thus
often allowing the AD9865 to replace discrete ADC and DAC
solutions. Power saving modes include the ability to reduce
power consumption of individual functional blocks, or to power
down unused blocks in half-duplex applications. A serial port
interface (SPI®) allows software programming of the various
functional blocks. An on-chip PLL clock multiplier and
synthesizer provide all the required internal clocks, as well as
two external clocks from a single crystal or clock source.
The Tx signal path consists of a bypassable 2×/4× low-pass
interpolation filter, a 10-bit TxDAC, and a line driver. The
transmit path signal bandwidth can be as high as 34 MHz at an
input data rate of 80 MSPS. The TxDAC provides differential
current outputs that can be steered directly to an external load
or to an internal low distortion current amplifier. The current
amplifier (IAMP) can be configured as a current- or voltage-
mode line driver (with two external npn transistors) capable of
delivering in excess of 23 dBm peak signal power. Tx power can
be digitally controlled over a 19.5 dB range in 0.5 dB steps.
The receive path consists of a programmable amplifier
(RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC.
The low noise RxPGA has a programmable gain range of
−12 dB to +48 dB in 1 dB steps. Its input referred noise is less
than 3 nV/rtHz for gain settings beyond 36 dB. The receive path
LPF cutoff frequency can be set over a 15 MHz to 35 MHz
range or simply bypassed. The 10-bit ADC achieves excellent
dynamic performance over a 5 MSPS to 80 MSPS span. Both
the RxPGA and the ADC offer scalable power consumption
allowing power/performance optimization.
The AD9865 provides a highly integrated solution for many
broadband modems. It is available in a space saving 64-pin chip
scale package and is specified over the commercial (−40°C to
+85°C) temperature range.
TABLE OF CONTENTS Specifications.....................................................................................3
Tx Path Specifications..................................................................3
Rx Path Specifications..................................................................4
Power Supply Specifications.......................................................5
Digital Specifications...................................................................6
Serial Port Timing Specifications...............................................7
Half-Duplex Data Interface (ADIO Port) Timing
Specifications................................................................................7
Full-Duplex Data Interface (Tx and Rx Port) Timing
Specifications................................................................................8
Explanation of Test Levels...........................................................8
Absolute Maximum Ratings............................................................9
Thermal Characteristics..............................................................9
ESD Caution..................................................................................9
Pin Configuration and Function Descriptions...........................10
Typical Performance Characteristics...........................................12
Rx Path Typical Performance Characteristics........................12
TxDAC Path Typical Performance Characteristics...............16
IAMP Path Typical Performance Characteristics..................18
Serial Port........................................................................................19
Register Map Description.........................................................21
Serial Port Interface (SPI).........................................................21
Digital Interface..............................................................................23
Half-Duplex Mode.....................................................................23
Full-Duplex Mode......................................................................24
RxPGA Control..........................................................................25
TxPGA Control..........................................................................27
Transmit Path..................................................................................28
Digital Interpolation Filters......................................................28
TxDAC and IAMP Architecture..............................................28
Tx Programmable Gain Control..............................................30
TxDAC Output Operation........................................................30
IAMP Current-Mode Operation..............................................30
IAMP Voltage-Mode Operation..............................................31
IAMP Current Consumption Considerations........................32
Receive Path....................................................................................33
Rx Programmable Gain Amplifier...........................................33
Low-Pass Filter...........................................................................34
Analog-to-Digital Converter (ADC).......................................35
AGC Timing Considerations....................................................36
Clock Synthesizer...........................................................................37
Power Control and Dissipation....................................................39
Power-Down...............................................................................39
Half-Duplex Power Savings......................................................39
Power Reduction Options.........................................................40
Power Dissipation......................................................................42
Mode Select upon Power-Up and Reset..................................42
Analog and Digital Loop-Back Test Modes............................43
PCB Design Considerations..........................................................44
Component Placement..............................................................44
Power Planes and Decoupling..................................................44
Ground Planes............................................................................44
Signal Routing............................................................................44
Evaluation Board............................................................................46
Outline Dimensions.......................................................................47
Ordering Guide..........................................................................47
REVISION HISTORY
11/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Specifications Tables....................................................3
Changes to Serial Table..................................................................19
Changes to Full Duplex Mode section.........................................24
Change to TxDAC and IAMP Architecture section..................29
Change to TxDAC Output Operation section............................30
Insert equation................................................................................37
Change to Figure 84 caption.........................................................42
11/03—Revision 0: Initial Version
SPECIFICATIONS
Tx PATH SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; fOSCIN = 50 MHz, fDAC = 200 MHz, RSET = 2.0 kΩ, unless otherwise
noted.
Table 1. Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input).
2 TxDAC IOUTFS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 Ω, FOUT = 5 MHz, 4x interpolation. IOUN full-scale current = 80 mA, fOSCIN = 80 MHz, fDAC =160 MHz, 2x interpolation.
4 Use external amplifier to drive additional load.
5 Internal VCO operates at 200 MHz , set to divide-by-1. Because CLKOUT2 is a divided down version of OSCIN, its jitter is typically equal to OSCIN.
7 CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1.
Rx PATH SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; half- or full-duplex operation with CONFIG = 0 default power bias
settings, unless otherwise noted.
Table 2. Min Typ Max
1 Includes RxPGA, ADC pipeline, and ADIO bus delay relative to fADC. fIN = 5 MHz, AIN = −1.0 dBFS , LPF cutoff frequency set to 15.5 MHz with Reg. 0x08 = 0x80.
3 fIN = 5 MHz, AIN = −1.0 dBFS , LPF cutoff frequency set to 26 MHz with Reg. 0x08 = 0x80.
POWER SUPPLY SPECIFICATIONS AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3.3 V; RSET = 2 kΩ, full-duplex operation with fDATA = 80 MSPS,1 unless otherwise noted.
Table 3.
