AD9864BCPZ ,IF Digitizing SubsystemGENERAL DESCRIPTION cascaded decimation factor is programmable from 48 to 960. The AD9864 is a gen ..
AD9864BCPZ# ,IF Digitizing SubsystemFEATURES The AD9864 is a general-purpose IF subsystem that digitizes a 10 MHz to 300 MHz input freq ..
AD9865BCP ,10-Bit Broadband Modem Mixed Signal Front EndFEATURES FUNCTIONAL BLOCK DIAGRAM TMLow cost 3.3 V CMOS MxFE for broadband modems 10-bit D/A conver ..
AD9865BCPZ ,10-Bit Broadband Modem Mixed Signal Front Endapplications. The digital inter-face is extremely flexible allowing simple interfaces to digital Th ..
AD9865BCPZRL ,10-Bit Broadband Modem Mixed Signal Front Endapplications requiring Tx and Rx path functionality mode line driver (with two external npn transis ..
AD9866BCP ,12-Bit Broadband Modem Mixed Signal Front EndFEATURES FUNCTIONAL BLOCK DIAGRAM TMLow cost 3.3 V CMOS MxFE for broadband modems 12-bit D/A conver ..
ADSP2105KP80 ,ADSP-2100 Family DSP MicrocomputersFEATURES(ADSP-2111)25 MIPS, 40 ns Maximum Instruction Rate ADSP-2100 CORE Separate On-Chip Buses fo ..
ADSP-2105KP-80 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 1768-Pin PGA (ADSP-2101) . . . ..
ADSP-21060 ,SHARC, 40 MHz, 120 MFLOPS, 5v, floating pointSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17Figure 18a. Synchronous REDY Timing ..
ADSP-21060KS-133 ,ADSP-2106x SHARC DSP Microcomputer FamilyFEATURES . . . . . . . . . . . . . . 4Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ADSP21060KS160 ,ADSP-2106x SHARC DSP Microcomputer Familyfeatures DT0ADRCLKDR0DMAR1-2including a 4 Mbit SRAM memory host processor interface,DMAG1-2TCLK1DMA ..
ADSP-21060KS-160 ,ADSP-2106x SHARC DSP Microcomputer FamilySPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17Figure 18a. Synchronous REDY Timing ..
AD9864BCPZ-AD9864BCPZ#
IF Digitizing Subsystem
IF Digitizing SubsystemRev. 0
FEATURES
10 MHz to 300 MHz input frequency
6.8 kHz to 270 kHz output signal bandwidth
7.5 dB SSB NF
–7.0 dBm IIP3
AGC free range up to –34 dBm
12 dB continuous AGC range
16 dB front end attenuator
Baseband I/Q 16-bit (or 24-bit) serial digital output
LO and sampling clock synthesizers
Programmable decimation factor, output format,
AGC, and sythesizer settings
370 Ω input impedance
2.7 V to 3.6 V supply voltage
Low current consumption: 17 mA
48-lead LFCSP package
APPLICATIONS
Multimode narrow-band radio products
Analog/digital UHF/VHF FDMA receivers
TETRA, APCO25, GSM/EDGE
Portable and mobile radio products
SATCOM terminals *. Patent No. 5,969,657; other patents pending.
PRODUCT OVERVIEW The AD9864 is a general-purpose IF subsystem that digitizes a
low level 10 MHz to 300 MHz IF input with a signal bandwidth
ranging from 6.8 kHz to 270 kHz. The signal chain of the
AD9864 consists of a low noise amplifier (LNA), a mixer, a
band-pass Σ-∆ analog-to-digital converter (ADC), and a deci-
mation filter with programmable decimation factor. An auto-
matic gain control (AGC) circuit gives the AD9864 12 dB of
continuous gain adjustment. Auxiliary blocks include both
clock and LO synthesizers.
The high dynamic range of the AD9864 and inherent antialias-
ing provided by the band-pass Σ-∆ converter allow the device to
cope with blocking signals up to 95 dB stronger than the desired
signal. This attribute often reduces the cost of a radio by reduc-
ing IF filtering requirements. Also, it enables multimode radios
of varying channel bandwidths, allowing the IF filter to be
specified for the largest channel bandwidth.
The SPI® port programs numerous parameters of the AD9864,
allowing the device to be optimized for any given application.
Programmable parameters include synthesizer divide ratios,
AGC attenuation and attack/decay time, received signal
strength level, decimation factor, output data format, 16 dB
attenuator, and the selected bias currents.
The AD9864 is available in a 48-lead LFCSP package and
operates from a single 2.7 V to 3.6 V supply. The total power
consumption is typically 56 mW and a power-down mode is
provided via serial interfacing.
FUNCTIONAL BLOCK DIAGRAM
IFIN
FREF
DOUTA
DOUTB
CLKOUT
MXOPMXONIF2PIF2NGCPGCN
04319-0-001 Figure 1. AD9864 Block Diagram
TABLE OF CONTENTS General Description.........................................................................3
AD9864 Specifications.....................................................................4
Digital Specifications........................................................................6
Absolute Maximum Ratings............................................................7
Thermal Resistance......................................................................7
Pin Configuration and Functional Descriptions..........................8
Definition of Specifications/Test Methods...............................9
Typical Performance Characteristics...........................................10
Serial Peripheral Interface (SPI)...............................................15
Theory of Operation......................................................................17
Serial Port Interface (SPI)..........................................................17
Synchronous Serial Interface (SSI)...........................................18
Syncronization Using SYNCB..................................................22
Interfacing to DSPs.....................................................................22
Power Control.............................................................................23
LO Synthesizer............................................................................23
Fast Acquire Mode......................................................................24
Clock Synthesizer.......................................................................24
IF LNA/Mixer.............................................................................26
Band-Pass ∑-∆ ADC..................................................................27
Decimation Filter.......................................................................29
Variable Gain Amplifier Operation With Automatic Gain
Control.........................................................................................30
Variable Gain Control................................................................31
Automatic Gain Control (AGC)...............................................32
System Noise Figure (NF) Versus VGA (or AGC) Control..34
Applications Considerations.....................................................35
Spurious Responses....................................................................37
External Passive Component Requirements..........................37
Applications................................................................................38
Layout Example, Evaluation Board, and Software.................42
Outline Dimensions.......................................................................43
ESD Caution................................................................................43
Ordering Guide..........................................................................43
REVISION HISTORY Revision 0: Initial Version
GENERAL DESCRIPTION The AD9864 is a general-purpose narrow-band IF subsystem that
digitizes a low level 10 MHz to 300 MHz IF input with a signal
bandwidth ranging from 6.8 kHz to 270 kHz. The signal chain of
the AD9864 consists of an LNA, a mixer, a band-pass Σ-∆ ADC,
and a decimation filter with programmable decimation factor.
The input LNA is a fixed gain block with an input impedance of
approximately 370 Ω||1.4 pF. The LNA input is single-ended
and self-biasing, allowing the input IF to be ac-coupled. The
LNA can be disabled through the serial interface, providing a
fixed 16 dB attenuation to the input signal.
The LNA drives the input port of a Gilbert-type active mixer.
The mixer LO port is driven by the on-chip LO buffer, which
can be driven externally, single-ended or differential. The LO
buffer inputs are self-biasing and allow the LO input to be
ac-coupled. The open-collector outputs of the mixer drive an
external resonant tank consisting of a differential LC network
tuned to the IF of the band-pass Σ-∆ ADC.
The external differential LC tank forms the resonator for the
first stage of the band-pass Σ-∆ ADC. The tank LC values must
be selected for a center frequency of fCLK/8, where fCLK is the
sample rate of the ADC. The fCLK/8 frequency is the IF digitized
by the band-pass Σ-∆ ADC. On-chip calibration allows stan-
dard tolerance inductor and capacitor values. The calibration is
typically performed once at power-up.
The ADC contains a sixth order multibit band-pass Σ-∆ modu-
lator that achieves very high instantaneous dynamic range over
a narrow frequency band centered at fCLK/8. The modulator
output is quadrature mixed to baseband and filtered by three
cascaded linear phase FIR filters to remove out-of-band noise.
The first FIR filter is a fixed decimate by 12 using a fourth order
comb filter. The second FIR filter also uses a fourth order comb
filter with programmable decimation from 1 to 16. The third
FIR stage is programmable for decimation of either 4 or 5. The
cascaded decimation factor is programmable from 48 to 960.
The decimation filter data is output via the synchronous serial
interface (SSI) of the chip.
Additional functionality built into the AD9864 includes LO and
clock synthesizers, programmable AGC, and a flexible synchro-
nous serial interface for output data.
The LO synthesizer is a programmable PLL consisting of a low
noise phase frequency detector (PFD), a variable output current
charge pump (CP), a 14-bit reference divider, A and B counters,
and a dual modulus prescaler. The user only needs to add an
appropriate loop filter and VCO for complete operation.
The clock synthesizer is equivalent to the LO synthesizer with
the following differences: It does not include the prescaler or A counter. It includes a negative resistance core used for VCO
generation.
The AD9864 contains both a variable gain amplifier (VGA) and a
digital VGA (DVGA). Both of these can operate manually or
automatically. In manual mode, the gain for each is programmed
through the SPI. In automatic gain control mode, the gains are
adjusted automatically to ensure the ADC does not clip and that
the rms output level of the ADC is equal to a programmable ref-
erence level.
The VGA has 12 dB of attenuation range and is implemented by
adjusting the ADC full-scale reference level. The DVGA gain is
implemented by scaling the output of the decimation filter. The
DVGA is most useful in extending the dynamic range in nar-
row-band applications requiring 16-bit I and Q data format.
The SSI provides a programmable frame structure, allowing
24-bit or 16-bit I and Q data and flexibility by including
attenuation and RSSI data if required.
AD9864 SPECIFICATIONS
Table 1. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS,
fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation
setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins. This includes 0.9 dB loss of matching network.
2 AGC with DVGA enabled.
