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AD9863BCP-50
12-Bit Mixed-Signal Front-End (MxFE™ )Processor For Broadband Applications
Mixed-Signal Front-End (MxFE™) Baseband
Transceiver for Broadband Applications
Rev. 0
FEATURES
Receive path includes dual 12-bit, 50 MSPS analog-to-digital
converters with internal or external reference
Transmit path includes dual 12-bit, 200 MSPS digital-to-
analog converters with 1×, 2×, or 4× interpolation and
programmable gain control
Internal clock distribution block includes a programmable
phase-locked loop and timing generation circuitry,
allowing single-reference clock operation
24-pin flexible I/O data interface allows various interleaved
or noninterleaved data transfers in half-duplex mode and
interleaved data transfers in full-duplex mode
Configurable through register programmability or
optionally limited programmability through mode pins
Independent Rx and Tx power-down control pins
64-lead LFCSP package (9 mm × 9 mm footprint)
APPLICATIONS
Broadband access
Broadband LAN
Communications (modems)
FUNCTIONAL BLOCK DIAGRAM I/O
INTERFACECONTROL
FLEXIBLEI/O BUS[0:23]
VIN+A
VIN–A
VIN+B
VIN–B
IOUT+A
IOUT–A
IOUT+B
IOUT–B
CLKIN1CLKIN2
Figure 1.
GENERAL DESCRIPTION The AD9863 is a member of the MxFE family—a group of
integrated converters for the communications market. The
AD9863 integrates dual 12-bit analog-to-digital converters
(ADC) and dual 12-bit digital-to-analog converters (TxDAC®).
The AD9863 ADCs are optimized for ADC sampling of 50 MSPS
and less. The dual TxDACs operate at speeds up to 200 MHz
and include a bypassable 2× or 4× interpolation filter. The
AD9863 is optimized for high performance, low power, small
form factor, and to provide a cost-effective solution for the
broadband communication market.
The AD9863 uses a single input clock pin (CLKIN) or two
independent clocks for the Tx path and the Rx path. The ADC
and TxDAC clocks are generated within a timing generation
block that provides user programmable options such as divide
circuits, PLL multipliers, and switches.
A flexible, bidirectional 24-bit I/O bus accommodates a variety
of custom digital back ends or open market DSPs.
In half-duplex systems, the interface supports 24-bit parallel
transfers or 12-bit interleaved transfers. In full-duplex systems,
the interface supports an 12-bit interleaved ADC bus and an
12-bit interleaved TxDAC bus. The flexible I/O bus reduces pin
count and, therefore, reduces the required package size on the
AD9863 and the device to which it connects.
The AD9863 can use either mode pins or a serial programma-
ble interface (SPI) to configure the interface bus, operate the
ADC in a low power mode, configure the TxDAC interpolation
rate, and control ADC and TxDAC power-down. The SPI
provides more programmable options for both the TxDAC path
(for example, coarse and fine gain control and offset control for
channel matching) and the ADC path (for example, the internal
duty cycle stabilizer, and twos complement data format).
The AD9863 is packaged in a 64-lead LFCSP (low profile, fine
pitched, chip scale package). The 64-lead LFCSP footprint is
only 9 mm × 9 mm, and is less than 0.9 mm high, fitting into
tightly spaced applications such as PCMCIA cards.
TABLE OF CONTENTS Tx Path Specifications......................................................................3
Rx Path Specifications......................................................................4
Power Specifications.........................................................................5
Digital Specifications........................................................................5
Timing Specifications.......................................................................6
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configuration and Pin Function Descriptions......................8
Typical Performance Characteristics...........................................10
Terminology....................................................................................17
Theory of Operation......................................................................18
System Block...............................................................................18
Rx Path Block..............................................................................18
Tx Path Block..............................................................................20
Digital Block................................................................................23
Programmable Registers............................................................33
Clock Distribution Block..........................................................36
Outline Dimensions.......................................................................40
Ordering Guide..........................................................................40
REVISION HISTORY Revision 0: Initial Version
Tx PATH SPECIFICATIONS
Table 1. FDAC = 200 MSPS; 4× interpolation; RSET = 4.02 kΩ; differential load resistance of 100 Ω1; TxPGA = 20 dB,
AVDD = DVDD = 3.3 V, unless otherwise noted See Figure 2 for description of the TxDAC termination scheme.
Figure 2. Diagram showing Termination of100 Ω Differential
Load for Some TxDAC Measurements
Rx PATH SPECIFICATIONS
Table 2. FADC = 50 MSPS; internal reference; differential analog inputs, ADC_AVDD = DVDD = 3.3 V, unless otherwise noted
POWER SPECIFICATIONS
Table 3. Analog and digital supplies = 3.3 V; FCLKIN1 = FCLKIN2 = 50 MHz; PLL 4× setting; normal timing mode
DIGITAL SPECIFICATIONS
Table 4.
TIMING SPECIFICATIONS
Table 5.
Table 6. Explanation of Test Levels ABSOLUTE MAXIMUM RATINGS
Table 7.
Thermal Resistance 64-lead LFCSP (4-layer board):
θJA = 24.2 (paddle soldered to ground plan, 0 LPM air)
θJA = 30.8 (paddle not soldered to ground plan, 0 LPM air)
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS 03604-0-072
IFACE
IFACE
DRV
VSS
SPI_C
RDWN
RDWN
ADC_
ADC_
VIN
VIN
VIN
VIN
ADC_
ADC_
LL_
PLL_A
VSS
SPI_DIO
SPI_CLK
SPI_SDO
ADC_LO_PWR
DVDD
DVSS
AVDD
IOUT–A
IOUT+A
AGND
REFIO
FSADJ
AGND
IOUT+B
IOUT–B
AVDD
CLKIN1
CLKIN2
RESET
L10
L11
IFACE1Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Underlined pin names and descriptions apply when the device is configured without a serial port interface, referred to as No SPI mode. 2 Some pin descriptions depend if a serial port is used (SPI mode) or not (No SPI mode), indicated by the labels SPI and No SPI. Some pin descriptions depend on the interface configuration: full-duplex (FD), half-duplex interleaved data (HD12), half-duplex parallel data (HD24), and a half-duplex
interface similar to the AD9860 and AD9862 data interface called clone mode (Clone). Clone mode requires a serial port interface.
TYPICAL PERFORMANCE CHARACTERISTICS
–1100510152025FREQUENCY (MHz)
AMP
UDE
(dBFS
Figure 4. AD9863 Rx Path Single-Tone FFT of Rx Channel B Path
Digitizing 2 MHz Tone
–1100510152025FREQUENCY (MHz)
AMP
UDE
(dBFS
Figure 5. AD9863 Rx Path Single-Tone FFT of Rx Channel B Path
Digitizing 5 MHz Tone
–1100510152025FREQUENCY (MHz)
UDE
(dBFS
Figure 6. AD9863 Rx Path Single-Tone FFT of Rx Channel B Path
Digitizing 24 MHz Tone
–1100510152025FREQUENCY (MHz)
AMP
UDE
(dBFS
Figure 7. AD9863 Rx Path Dual-Tone FFT of Rx Channel A Path
Digitizing 1 MHz and 2 MHz Tones
–1100510152025FREQUENCY (MHz)
AMP
UDE
(dBFS
Figure 8. AD9863 Rx Path Dual-Tone FFT of Rx Channel A Path
Digitizing 5 MHz and 8 MHz Tones
–1100510152025FREQUENCY (MHz)
UDE
(dBFS
Figure 9. AD9863 Rx Path Dual-Tone FFT of Rx Channel A Path
Digitizing 20 MHz and 25 MHz Tones
–1100510152025FREQUENCY (MHz)
AMP
UDE
(dBFS
Figure 10. AD9863 Rx Path Single-Tone FFT of Rx Channel B Path
Digitizing 76 MHz Tone
0510152025INPUT FREQUENCY (MHz)
NR (dBc
Figure 11. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone
SNR Performance vs. Input Frequency
0510152025INPUT FREQUENCY (MHz)
DR (dBc
Figure 12. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone
SFDR Performance vs. Input Frequency
–1100510152025FREQUENCY (MHz)
AMP
UDE
(dBFS
Figure 13. AD9863 Rx Path Dual-Tone FFT of Rx Channel A Path
Digitizing 70 MHz and 72 MHz Tones
10.00510152025INPUT FREQUENCY (MHz)
INAD (dBc
Figure 14. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone
SINAD Performance vs. Input Frequency
–800510152025INPUT FREQUENCY (MHz)
THD (dBc
Figure 15. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone
THD Performance vs. Input Frequency
–5–10–15–20–25–30–35–40–45–50INPUT AMPLITUDE (dBFS)
NR (dBc
Figure 16. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone
SNR Performance vs. Input Amplitude
3.63.33.02.7INPUT AMPLITUDE (dBFS)
NR (dBc
Figure 17. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone
SNR Performance vs. ADC_AVDD and Temperature
2.73.03.33.6INPUT AMPLITUDE (dBFS)
THD (dBc
Figure 18. AD9863 Rx Path Single-Tone THD Performance vs.
ADC_AVDD and Temperature
–20–5–10–15–20–25–30–35–40INPUT AMPLITUDE (dBFS)
DR (dBFS
THD (dBFS
Figure 19. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone
THD and SFDR Performance vs. Input Amplitude
2.73.03.33.6INPUT FREQUENCY (MHz)
INAD (dBc
Figure 20. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone
SINAD Performance vs. ADC_AVDD and Temperature
2.73.03.33.6INPUT AMPLITUDE (dBFS)
DR (dBc
Figure 21. AD9863 Rx Path Single-Tone SFDR Performance vs.
ADC_AVDD and Temperature
–1100510152025FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 22. AD9863 Tx Path 1 MHz Single-Tone Output FFT of Tx Path
with 20 mA Full-Scale Output into 33 Ω Differential Load
DR (dBc
–60510152025OUTPUT FREQUENCY (MHz)
THD (dBc
Figure 23. AD9863 Tx Path THD/SFDR vs. Output Frequency of Tx Channel A,
with 20 mA Full-Scale Output into 60 Ω Differential Load
–60510152025OUTPUT FREQUENCY (MHz)
THD (dBc
Figure 24. AD9863 Tx Path THD vs. Output Frequency of Tx Channel A
–1100510152025FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 25. AD9863 Tx Path 5 MHz Single-Tone Output FFT of Tx Channel A
with 20 mA Full-Scale Output into 33 Ω Differential Load
05101520OUTPUT FREQUENCY (MHz)
NR/
INAD (dBc
Figure 26. AD9863 Tx Path SINAD/SNR vs. Output Frequency of Tx Path
with 20 mA Full-Scale Output into 60 Ω Differential Load
–55510152025OUTPUT FREQUENCY (MHz)
D (dBc
Figure 27. AD9863 Tx Path Dual-Tone (0.5 MHz Spacing) IMD vs.
Output Frequency
Figure 28 to Figure 33 use the same input data to the Tx path, a 64-carrier OFDM signal over a 20 MHz bandwidth, centered at 20 MHz.
The center two carriers are removed from the signal to observe the in-band intermodulation distortion (IMD) from the DAC output.
–1207.512.517.522.527.532.5FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 28. AD9863 Tx Path FFT, 64-Carrier (Center Two Carriers Removed)
OFDM Signal over 20 MHz Bandwidth, Centered at 20 MHz, with
20 mA Full-Scale Output into 60 Ω Differential Load
–1207.58.08.59.09.510.010.511.011.512.012.5FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 29. AD9863 Tx Path FFT, Lower Band IMD Products of
OFDM Signal in Figure 28
–12001020304050607080FREQUENCY (MHz)
AMP
UDE
(dBc
–12018.7519.2519.7520.2520.7521.25FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 31. AD9863 Tx Path FFT, In-Band IMD Products of
OFDM Signal in Figure 28
27.528.028.529.029.530.030.531.031.532.032.5FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 32. AD9863 Tx Path FFT, Lower Band IMD Products of
OFDM Signal in Figure 28
–12001020304050607080FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 33. AD9863 Tx Path FFT of OFDM Signal in
Figure 34 to Figure 39 use the same input data to the Tx path, a 256-carrier OFDM signal over a 1.75 MHz bandwidth, centered at 7 MHz.
The center four carriers are removed from the signal to observe the in-band intermodulation distortion (IMD) from the DAC output.
–1306.06.26.46.66.87.07.27.47.67.88.0FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 34. AD9863 Tx Path FFT, 256-Carrier (Center Four Carriers Removed)
OFDM Signal over 1.75 MHz Bandwidth, Centered at 7 MHz, with
20 mA Full-Scale Output into 60 Ω Differential Load
6.066.086.106.126.146.166.18FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 35. AD9863 Tx Path FFT, Lower-Band IMD Products of
OFDM Signal in Figure 34
–130510152025FREQUENCY (MHz)
AMP
UDE
(dBc
–1306.976.986.997.007.017.027.03FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 37. AD9863 Tx Path FFT, In-Band IMD Products of
OFDM Signal in Figure 34
7.817.837.857.877.897.917.93FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 38. AD9863 Tx Path FFT, Upper-Band IMD Products of
OFDM Signal in Figure 34
–1300510152025FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 40 to Figure 45 use the same input data to the Tx path, a 256-carrier OFDM signal over a 23 MHz bandwidth, centered at 23 MHz.
The center four carriers are removed from the signal to observe the in-band intermodulation distortion (IMD) from the DAC output.
–1201419243429FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 40. AD9863 Tx Path FFT, 256-Carrier (Center Four Carriers Removed)
OFDM Signal over 23 MHz Bandwidth, Centered at 7 MHz, with
20 mA Full-Scale Output into 60 Ω Differential Load
10.510.710.911.111.311.511.711.912.112.312.5FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 41. AD9863 Tx Path FFT, Lower-Band IMD Products of
OFDM Signal in Figure 40
–1200102030405060708090FREQUENCY (MHz)
AMP
UDE
(dBc
6.976.986.997.007.017.027.03FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 43. AD9863 Tx Path FFT, In-Band IMD Products of
OFDM Signal in Figure 40
33.533.733.934.134.334.534.734.935.135.335.5FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 44. AD9863 Tx Path FFT, Upper-Band IMD Products of
OFDM Signal in Figure 40
–1200102030405060708090FREQUENCY (MHz)
AMP
UDE
(dBc
Figure 45. AD9863 Tx Path FFT of OFDM Signal in Figure 40,
TERMINOLOGY
Input Bandwidth The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay The delay between the 50% point of the rising edge of the
CLKIN1 signal and the instant at which the analog input is
actually sampled.
Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.
Crosstalk Coupling onto one channel being driven by a –0.5 dBFS signal
when the adjacent interfering channel is driven by a full-scale
signal.
Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the input phase 180° and taking the peak measurement again.
Then the difference is computed between both peak
measurements.
Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) The effective number of bits is calculated from the measured
SNR based on the following equation: .6.1dBSNRENOBMEASURED−=
Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that a signal
should be left in the logic high state to achieve rated perform-
ance; pulse width low is the minimum time a signal should be
left in the low state, logic low.
Full-Scale Input Power Expressed in dBm, full-scale input power is computed using the
following equation: ⎟⎜=−
001.0log10
INPUTRMSFULLSCALE
FULLSCALEVPower
Gain Error Gain error is the difference between the measured and ideal
Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity The deviation of the transfer function from a reference line
measured in fractions of an LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate The encode rate at which parametric testing is performed.
Output Propagation Delay The delay between a differential crossing of CLK+ and CLK−
and the time when all output data bits are within valid logic
levels.
Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full-scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.
Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. It also may be
reported in dBc (i.e., degrades as signal level is lowered) or
dBFS (i.e., always related back to converter full scale). SFDR
does not include harmonic distortion components.
Worst Other Spur The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonics) reported in dBc.
THEORY OF OPERATION
SYSTEM BLOCK The AD9863 is targeted to cover the mixed-signal front end
needs of multiple wireless communication systems. It features a
receive path that consists of dual 12-bit receive ADCs, and a
transmit path that consists of dual 12-bit transmit DACs
(TxDAC). The AD9863 integrates additional functionality
typically required in most systems, such as power scalability, Tx
gain control, and clock multiplication circuitry.
The AD9863 minimizes both size and power consumption to
address the needs of a range of applications from the low power
portable market to the high performance base station market.
The part is provided in a 64-lead lead frame chip scale package
(LFCSP) that has a footprint of only 9 mm × 9 mm. Power
consumption can be optimized to suit the particular application
beyond just a speed grade option by incorporating power-down
controls, low power ADC modes, TxDAC power scaling, and a
half-duplex mode, which automatically disables the unused
digital path.
The AD9863 uses two 12-bit buses to transfer Rx path data and
Tx path data. These two buses support 24-bit parallel data
transfers or 12-bit interleaved data transfers. The bus is
configurable through either external mode pins or through
internal registers settings. The registers allow many more
options for configuring the entire device.
The following sections discuss the various blocks of the AD9863:
Rx block, Tx block, the digital block, programmable registers
and the clock distribution block.
Rx PATH BLOCK
Rx Path General Description The AD9863 Rx path consists of two 12-bit, 50 MSPS analog-to-
digital converters (ADCs). The dual ADC paths share the same
clocking and reference circuitry to provide optimal matching
characteristics. Each of the ADCs consists of a 9-stage differen-
tial pipelined switched capacitor architecture with output error
correction logic.
The pipelined architecture permits the first stage to operate on a
new input sample, while the remaining stages operate on
preceding samples. Sampling occurs on the falling edge of the
input clock. Each stage of the pipeline, excluding the last,
consists of a low resolution flash ADC and a residual multiplier
to drive the next stage of the pipeline. The residual multiplier
uses the flash ADC output to control a switched capacitor
digital-to-analog converter (DAC) of the same resolution. The
DAC output is subtracted from the stage’s input signal, and the
residual is amplified (multiplied) to drive the next pipeline
stage. The residual multiplier stage is also called a multiplying
DAC (MDAC). One bit of redundancy is used in each one of
the stages to facilitate digital correction of flash errors. The last
The differential input stage is dc self-biased and allows
differential or single-ended inputs. The output-staging block
aligns the data, carries out the error correction, and passes the
data to the output buffers.
The latency of the Rx path is about 5 clock cycles.
Rx Path Analog Input Equivalent Circuit The Rx path analog inputs of the AD9863 incorporate a novel
structure that merges the function of the input sample-and-
hold amplifiers (SHAs) and the first pipeline residue amplifiers
into a single, compact switched capacitor circuit. This structure
achieves considerable noise and power savings over a conven-
tional implementation that uses separate amplifiers, by eliminating
one amplifier in the pipeline.
Figure 46 illustrates the equivalent analog inputs of the AD9863
(a switched capacitor input). Bringing CLK to logic high opens
switch S3 and closes switches S1 and S2; this is the sample mode
of the input circuit. The input source connected to VIN+ and
VIN− must charge capacitor CH during this time. Bringing CLK
to a logic low opens S2, and then switch S1 opens followed by
closing S3. This puts the input circuit into hold mode.
VIN+
RIN
VCM
CINS1
Figure 46. Differential Input Architecture
The structure of the input SHA places certain requirements on
the input drive source. The differential input resistors are
typically 2 kΩ each. The combination of the pin capacitance,
CIN, and the hold capacitance, CH, is typically less than 5 pF. The
input source must be able to charge or discharge this capaci-
tance to 12-bit accuracy in one-half of a clock cycle. When the
SHA goes into sample mode, the input source must charge or
discharge capacitor CH from the voltage already stored on it to
the new voltage. In the worst case, a full-scale voltage step on
the input source must provide the charging current through the
RON of switch S1 (typically 100 Ω) to a settled voltage within
one-half of the ADC sample period. This situation corresponds
to driving a low input impedance. On the other hand, when the
source voltage equals the value previously stored on CH, the
hold capacitor requires no input current and the equivalent
input impedance is extremely high.
Rx Path Application Section Adding series resistance between the output of the signal source
and the VIN pins reduces the drive requirements placed on the
signal source. Figure 47 shows this configuration.
RSERIES
RSERIES
AD9863
Figure 47. Typical Input
The bandwidth of the particular application limits the size of
this resistor. For applications with signal bandwidths less than
10 MHz, the user may insert series input resistors and a shunt
capacitor to produce a low-pass filter for the input signal.
Additionally, adding a shunt capacitance between the VIN pins
can lower the ac load impedance. The value of this capacitance
depends on the source resistance and the required signal
bandwidth.
The Rx input pins are self-biased to provide this midsupply,
common-mode bias voltage, so it is recommended to ac couple
the signal to the inputs using dc blocking capacitors. In systems
that must use dc coupling, use an op amp to comply with the
input requirements of the AD9863. The inputs accept a signal
with a 2 V p-p differential input swing centered about one-half
of the supply voltage (AVDD/2). If the dc bias is supplied exter-
nally, the internal input bias circuit should be powered down by
writing to registers Rx_A dc bias [Register 0x3, Bit 6] and Rx_B
dc bias [Register 0x4, Bit 7].
The ADCs in the AD9863 are designed to sample differential
input signals. The differential input provides improved noise
immunity and better THD and SFDR performance for the Rx
path. In systems that use single-ended signals, these inputs can
be digitized, but it is recommended that a single-ended-to-
differential conversion be performed. A single-ended-to-
differential conversion can be performed by using a transformer
coupling circuit (typically for signals above 10 MHz) or by
using an operational amplifier, such as the AD8138 (typically
for signals below 10 MHz).
ADC Voltage References The AD9863 12-bit ADCs use internal references that are
designed to provide for a 2 V p-p differential input range. The
internal band gap reference generates a stable 1 V reference level
and is decoupled through the VREF pin. REFT and REFB are
the differential references generated based on the voltage level
of VREF. Figure 48 shows the proper decoupling of the refer-
ence pins VREF, REFT, and REFB when using the internal
reference. Decoupling capacitors should be placed as close to
the reference pins as possible.
default 1 V VREF reference accepts a 2 V p-p differential input
swing and the offset voltage should be
REFT = AVDD/2 + 0.5 V
REFB = AVDD/2 – 0.5 V
03604-0-075
10µF
10µFFigure 48. Typical Rx Path Decoupling
An external reference may be used for systems that require a
different input voltage range, high accuracy gain matching
between multiple devices, or improvements in temperature drift
and noise characteristics. When an external reference is desired,
the internal Rx band gap reference must be powered down
using the VREF2 register [Register 0x5, Bit 4] and the external
reference driving the voltage level on the VREF pin. The exter-
nal voltage level should be one-half of the desired peak-to-peak
differential voltage swing. The result is that the differential
voltage references are driven to new voltages:
REFT = AVDD/2 +VREF/2 V
REFB = AVDD/2 – VREF/2 V
If an external reference is used, it is recommended not to exceed
a differential offset voltage for the reference greater than 1 V.
Clock Input and Considerations Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensi-
tive to clock duty cycle. Commonly, a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance
characteristics. The AD9863 contains clock duty cycle stabilizers
circuitry (DCSs). The DCS retimes the internal ADC clock
(nonsampling edge) and provides the ADC with a nominal 50%
duty cycle. Input clock rates of over 40 MHz can use the DCS so
that a wide range of input clock duty cycles can be
accommodated. Conversely, DCS should not be used for Rx
sampling below 40 MSPS. Maintaining a 50% duty cycle clock is
particularly important in high speed applications when proper
sample-and-hold times for the converter are required to
maintain high performance. The DCS can be enabled by writing
highs to the Rx_A/Rx_B CLK Duty register bits [Register
0x06/0x07, Bit 4].
The duty cycle stabilizer uses a delay-locked loop to create the
ADCs are sensitive to the quality of the clock input. The
degradation in SNR at a given full-scale input frequency (fINPUT),
due only to aperture jitter (tA), can be calculated with the
following equation:
SNR degradation = 20 log [(½)πFINtA)]
In the equation, the rms aperture jitter, tA, represents the root-
sum-square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
The clock input is a digital signal that should be treated as an
analog signal with logic level threshold voltages, especially in
cases where aperture jitter may affect the dynamic range of the
AD9863. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other meth-
ods), it should be retimed by the original clock at the last step.
Power Dissipation and Standby Mode The power dissipation of the AD9863 Rx path is proportional to
its sampling rate. The Rx path portion of the digital (DRVDD)
power dissipation is determined primarily by the strength of the
digital drivers and the load on each output bit. The digital drive
current can be calculated by
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
where N is the number of bits changing and CLOAD is the average
load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates, which increases with clock fre-
quency. The baseline power dissipation for either speed grade
can be reduced by asserting the ADC_LO_PWR pin, which
reduces internal ADC bias currents by half, in some case
resulting in degraded performance.
To further reduce power consumption of the ADC, the
ADC_LO_PWR pin can be combined with a serial programmable
register setting to configure an ultralow power mode. The
ultralow power mode reduces the power consumption by a
fourth of the normal power consumption. The ultralow power
mode can be used at slower sampling frequencies or if reduced
performance is acceptable. To configure the ultralow power
mode, assert the ADC_LO_PWR pin during power-up and
write the following register settings:
Register 0x08 (MSB) ‘0000 1100’
Register 0x09 (MSB) ‘0111 0000’
Register 0x0A (MSB) ‘0111 0000’
Either of the ADCs in the AD9863 Rx path can be placed in
standby mode independently by writing to the appropriate SPI
register bits in Registers 3, 4, and 5. The minimum standby
power is achieved when both channels are placed in full power-
down mode using the appropriate SPI register bits in Registers
3, 4, and 5. Under this condition, the internal references are
powered down. When either or both of the channel paths are
enabled after a power-down, the wake-up time is directly related
to the recharging of the REFT and REFB decoupling capacitors
and the duration of the power-down. Typically, it takes
approximately 5 ms to restore full operation with fully
discharged 0.1 µF and 10 µF decoupling capacitors on REFT
and REFB.
12005101520253035404550Rx PATH SAMPLING RATE (MHz)
DD CURRE
NT (mA)
Figure 49. Typical Rx Path Analog Supply Current vs. Sample Rate,
VDD = 3.3 V for Normal, Low and Ultralow Power Modes
Tx PATH BLOCK The AD9863 transmit (Tx) path includes dual interpolating
12-bit current output DACs that can be operated independently
or can be coupled to form a complex spectrum in an image
reject transmit architecture. Each channel includes two FIR
filters, making the AD9863 capable of 1×, 2×, or 4× interpola-
tion. High speed input and output data rates can be achieved
within the limitations listed in Table 9.
Table 9. AD9863 Tx Path Maximum Data Rate By using the dual DAC outputs to form a complex signal, an
external analog quadrature modulator, such as the Analog
Devices AD8349, can enable an image rejection architecture.
