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AD9861BCP-50
10-Bit Mixed-Signal Front-End (MxFE™)Processor
Mixed-Signal Front-End (MxFE™) Baseband
Transceiver for Broadband Applications
Rev. 0
FEATURES
Receive path includes dual 10-bit analog-to-digital
converters with internal or external reference, 50 MSPS
and 80 MSPS versions
Transmit path includes dual 10-bit, 200 MSPS digital-to-
analog converters with 1×, 2×, or 4× interpolation and
programmable gain control
Internal clock distribution block includes a programmable
phase-locked loop and timing generation circuitry,
allowing single-reference clock operation
20-pin flexible I/O data interface allows various interleaved
or noninterleaved data transfers in half-duplex mode and
interleaved data transfers in full-duplex mode
Configurable through register programmability or
optionally limited programmability through mode pins
Independent Rx and Tx power-down control pins
64-lead LFCSP package (9 mm × 9 mm footprint)
3 configurable auxiliary converter pins
APPLICATIONS
Broadband access
Broadband LAN
Communications (modems)
FUNCTIONAL BLOCK DIAGRAM
I/OINTERFACE
CONTROL
FLEXIBLEI/O BUS[0:19]
VIN+A
VIN–A
VIN+B
VIN–B
IOUT+A
IOUT–A
IOUT+B
IOUT–B
CLKIN03606-0-001Figure 1.
GENERAL DESCRIPTION The AD9861 is a member of the MxFE family—a group of
integrated converters for the communications market. The
AD9861 integrates dual 10-bit analog-to-digital converters
(ADC) and dual 10-bit digital-to-analog converters (TxDAC®).
Two speed grades are available, -50 and -80. The -50 is opti-
mized for ADC sampling of 50 MSPS and less, while the -80 is
optimized for ADC sample rates between 50 MSPS and 80 MSPS.
The dual TxDACs operate at speeds up to 200 MHz and
include a bypassable 2× or 4× interpolation filter. Three
auxiliary converters are also available to provide required
system level control voltages or to monitor system signals. The
AD9861 is optimized for high performance, low power, small
form factor, and to provide a cost-effective solution for the
broadband communication market.
The AD9861 uses a single input clock pin (CLKIN) to generate
all system clocks. The ADC and TxDAC clocks are generated
within a timing generation block that provides user programma-
ble options such as divide circuits, PLL multipliers, and switches.
A flexible, bidirectional 20-bit I/O bus accommodates a variety
of custom digital back ends or open market DSPs.
In half-duplex systems, the interface supports 20-bit parallel
transfers or 10-bit interleaved transfers. In full-duplex systems,
the interface supports an interleaved 10-bit ADC bus and an
interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin
count and, therefore, reduces the required package size on the
AD9861 and the device to which it connects.
The AD9861 can use either mode pins or a serial program-
mable interface (SPI) to configure the interface bus, operate the
ADC in a low power mode, configure the TxDAC interpolation
rate, and control ADC and TxDAC power-down. The SPI
provides more programmable options for both the TxDAC path
(for example, coarse and fine gain control and offset control for
channel matching) and the ADC path (for example, the internal
duty cycle stabilizer, and twos complement data format).
The AD9861 is packaged in a 64-lead LFCSP (low profile, fine
pitched, chip scale package). The 64-lead LFCSP footprint is
only 9 mm × 9 mm, and is less than 0.9 mm high, fitting into
tightly spaced applications such as PCMCIA cards
TABLE OF CONTENTS Tx Path Specifications......................................................................3
Rx Path Specifications......................................................................4
Power Specifications.........................................................................5
Digital Specifications........................................................................5
Timing Specifications.......................................................................6
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configuration and Pin Function Descriptions......................8
Typical Performance Characteristics...........................................10
Terminology....................................................................................21
Theory of Operation......................................................................22
System Block...............................................................................22
Rx Path Block..............................................................................22
Tx Path Block..............................................................................24
Auxiliary Converters..................................................................27
Digital Block................................................................................30
Programmable Registers............................................................42
Clock Distribution Block..........................................................45
Outline Dimensions.......................................................................49
Ordering Guide..........................................................................50
REVISION HISTORY Revision 0: Initial Version
Tx PATH SPECIFICATIONS
Table 1. AD9861-50 and AD9861-80
FDAC = 200 MSPS; 4× interpolation; RSET = 4.02 kΩ; differential load resistance of 100 Ω1; TxPGA = 20 dB, AVDD = DVDD = 3.3 V,
unless otherwise noted See Figure 2 for description of the TxDAC termination scheme.
Figure 2. Diagram Showing Termination of 100 Ω Differential
Load for Some TxDAC Measurements
Rx PATH SPECIFICATIONS
Table 2. AD9861-50 and AD9861-80
FADC = 50 MSPS for the AD9861-50, 80 MSPS for the AD9861-80; internal reference; differential analog inputs,
ADC_AVDD = DVDD = 3.3V, unless otherwise noted
POWER SPECIFICATIONS
Table 3. AD9861-50 and AD9861-80
Analog and digital supplies = 3.3 V; FCLKIN = 50 MHz; PLL 4× setting; normal timing mode
DIGITAL SPECIFICATIONS
Table 4. AD9861-50 and AD9861-80
