AD9852ASQ-AD9852AST Fast Delivery |IC PHOENIX CO.,LIMITED

AD9852ASQ ,CMOS 300 MHz Complete-DDSGENERAL DESCRIPTIONLinear or Nonlinear FM Chirp Functions with SingleThe AD9852 digital synthesizer ..
AD9852AST ,CMOS 300 MHz Complete-DDSCHARACTERISTICSLogic “1” Voltage, High Z Load FULL VI 3.10 3.10 VLogic “0” Voltage, High Z Load FUL ..
AD9852ASTZ , CMOS 300 MSPS Complete DDS
AD9853AS ,Programmable Digital OPSK/16-QAM ModulatorSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*EXPLANATION OF TEST LEVELS ..
AD9854ASQ ,CMOS 300 MHz Quadrature Complete-DDSCHARACTERISTICSI and Q DAC Quad. Phase Error 25

AD9852ASQ-AD9852AST
CMOS 300 MHz Complete-DDS
REV.0
CMOS 300 MHz
Complete-DDS
FUNCTIONAL BLOCK DIAGRAM
DIFF/SINGLE
SELECT
REFERENCE
CLOCK IN
FSK/BPSK/HOLD
DATA IN
BIDIRECTIONAL
I/O UPDATE
READ
WRITE
SERIAL/PARALLEL
SELECT6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT PARALLEL
LOAD
MASTER
RESET
+VSGND
CLOCK OUT
ANALOG IN
SHAPED
ON/OFF KEYING
ANALOG OUT
DAC RSET
ANALOG OUT
FEATURES
300 MHz Internal Clock Rate
Integrated 12-Bit Output DACs
Ultrahigh-Speed, 3 ps RMS Jitter Comparator
Excellent Dynamic Performance: 80 dB SFDR @ 100 MHz
(61 MHz) AOUT
43 to 203 Programmable Reference Clock Multiplier
Dual 48-Bit Programmable Frequency Registers
Dual 14-Bit Programmable Phase Offset Registers
12-Bit Amplitude Modulation and Programmable
Shaped On/Off Keying Function
Single Pin FSK and PSK Data Interface
Linear or Nonlinear FM Chirp Functions with Single
Pin Frequency “Hold” Function
Frequency-Ramped FSK
<25 ps RMS Total Jitter in Clock Generator Mode
Automatic Bidirectional Frequency Sweeping
SIN(x)/x Correction
Simpliﬁed Control Interface
10 MHz Serial, 2-Wire or 3-Wire SPI-Compatible or
100 MHz Parallel 8-Bit Programming
3.3 V Single Supply
Multiple Power-Down Functions
Single-Ended or Differential Input Reference Clock
Small 80-Lead LQFP Packaging
APPLICATIONS
Agile, L.O. Frequency Synthesis
Programmable Clock Generator
FM Chirp Source for Radar and Scanning Systems
Test and Measurement Equipment
Commercial and Amateur RF Exciter
GENERAL DESCRIPTION
The AD9852 digital synthesizer is a highly integrated device
that uses advanced DDS technology, coupled with an internal
high-speed, high-performance D/A converters and a comparator
to form a digitally-programmable agile synthesizer function. When
referenced to an accurate clock source, the AD9852 generates a
highly stable, frequency-phase amplitude-programmable sine
wave output that can be used as an agile L.O. in communications,
radar, and many other applications. The AD9852’s innovative
high-speed DDS core provides 48-bit frequency resolution
(1 microHertz tuning steps). Phase truncation to 17 bits assures
excellent SFDR. The AD9852’s circuit architecture allows the
(continued on page 13)
AD9852–SPECIFICATIONS(VS = 3.3 V 6 5%, RSET = 3.9 kV external reference clock frequency = 30 MHz with
REFCLK Multiplier enabled at 103 for AD9852ASQ, external reference clock frequency = 20 MHz with REFCLK Multiplier enabled at 103 for
AD9852AST, unless otherwise noted.)
DAC STATIC OUTPUT CHARACTERISTICS
DAC WIDEBAND SFDR
DAC NARROWBAND SFDR
RESIDUAL PHASE NOISE
AD9852
COMPARATOR OUTPUT CHARACTERISTICS
COMPARATOR NARROWBAND SFDR
CLOCK GENERATOR OUTPUT JITTER
PARALLEL I/O TIMING CHARACTERISTICS
SERIAL I/O TIMING CHARACTERISTICS
AD9852–SPECIFICATIONS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9852 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
NOTESThe reference clock inputs are conﬁgured to accept a 1 V p-p (minimum) dc offset sine wave centered at one-half the applied VDD or a 3 V TTL-level pulse input.Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.Represents comparator’s inherent cycle-to-cycle jitter contribution. Input signal is a 1 V, 40 MHz square wave. Measurement device Wavecrest DTS – 2075.Comparator input originates from Analog Out section via external 7-pole elliptic LPF. Single-ended input, 0.5 V p-p. Comparator output terminated in 50 W.Important: In the 80-lead LQFP package simultaneous operation at the maximum ambient temperature of 85°C and at the maximum internal clock frequency at
200 MHz may cause the maximum die junction temperature of 150°C to be exceeded. Refer to the section of the data sheet entitled Power Dissipation section and
Thermal Considerations section for derating and thermal management information.All functions engaged.All functions except inverse sinc engaged.All functions except inverse sinc and digital multipliers engaged.
Speciﬁcations subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level–100% Production Tested.
III–Sample Tested Only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–Devices are 100% production tested at 25°C and
guaranteed by design and characterization testing
for industrial operating temperature range.
ABSOLUTE MAXIMUM RATINGS*
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C
Maximum Clock Frequency . . . . . . . . . . . . . . . . . . 300 MHz
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect device
reliability.
ORDERING GUIDE
PIN FUNCTION DESCRIPTIONS
AD9852
PIN CONFIGURATION
DVDD
DVDD
DGND
DGND
A2/IO RESET
A1/SDO
A0/SDIO
I/O UD
WRB/SCLK
RDB/CSB
DVDDDVDDDVDDDGNDDGNDDGND
FSK/BPSK/HOLDSHAPED KEYING
AVDDAVDDAGNDAGND
VOUT
AVDDAVDDAGNDAGND
AGND
VINP
VINN
AVDD
AGND
AGND
AGND
IOUT1
IOUT1B
AVDD
IOUT2B
IOUT2
AGND
AVDD
DACBP
DAC RSET
AGND
AVDD
PLL FILTERAGNDNCDIFF CLK ENABLEAVDDAGNDAGNDREFCLOCKBREFCLOCKS/P SELECTMASTER RESETDGNDDVDDDVDDDGNDDGNDDGNDDGNDDVDDDVDD
NC = NO CONNECT
Figure 1.Equivalent Input and Output CircuitsDAC Outputsb.Comparator Outputc.Comparator Inputd.Digital Input
VDD
IOUTIOUTB
VDD
DIGITALDIGITAL
OUT
VDD
AD9852
START 0Hz
15MHz/STOP 150MHz
Figure 2.Wideband SFDR, 19.1 MHz
START 0Hz
15MHz/STOP 150MHz
Figure 3.Wideband SFDR, 39.1 MHz
START 0Hz
15MHz/STOP 150MHz
Figure 4.Wideband SFDR, 59.1 MHz
START 0Hz
15MHz/STOP 150MHz
Figure 5.Wideband SFDR, 79.1 MHz
START 0Hz
15MHz/STOP 150MHz
Figure 6.Wideband SFDR, 99.1 MHz
START 0Hz
15MHz/STOP 150MHz
Figure 7.Wideband SFDR, 119.1 MHz
Figures 2–7 indicate the wideband harmonic distortion Performance of the AD9852 from 19.1 MHz to 119.1 MHz Fundamen-
tal Output, Reference Clock = 30 MHz, REFCLK Multiplier = 10. Each graph plotted from 0 MHz to 150 MHz.
Figures 8–11 show the tradeoff in elevated noise floor, increased phase noise, and occasional discrete spurious energy when the
internal REFCLK Multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown.
Figure 10. Narrowband SFDR, 39.1 MHz, 1 MHz BW,
30 MHz EXTCLK with REFCLK Multiply = 10·
Figure 11.Narrowband SFDR, 39.1 MHz, 50 kHz BW,
30 MHz EXTCLK/REFCLK Multiplier = 10·
CENTER 39.1MHz
5kHz/SPAN 50kHz
CENTER 39.1MHz
100kHz/SPAN 1MHz
Figure 8.Narrowband SFDR, 39.1 MHz, 1 MHz BW,
300 MHz EXTCLK with REFCLK Multiply Bypassed
CENTER 39.1MHz
5kHz/SPAN 50kHz
Figure 9.Narrowband SFDR, 39.1 MHz, 50 kHz BW,
300 MHz EXTCLK with REFCLK Multiplier Bypassed
Figures 12 and 13 show the slight increase in noise floor both with and without the PLL when slower clock speeds are used to
generate the same fundamental frequency, that is, with a 100 MHz clock as opposed to a 300 MHz clock in Figures 9 and 11.
AD9852
Figures 14 and 15 show the effects of utilizing “sweet spots” in the tuning range of a DDS. Figure 14 represents a tuning word that
accentuates the aberrations associated with truncation in the DDS algorithm. Figure 15 is essentially the same output frequency (a few
tuning codes over), but it displays much fewer spurs on the output due to the selection of a tuning “sweet spot.” Consideration
should be given to all DDS applications to exploit the beneﬁt of sweet spot tuning.
CENTER 112.499MHz
50kHz/SPAN 500kHz
Figure 14.The Opposite of a “Sweet Spot.” 112.469 MHz
with multiple high energy spurs close around the
fundamental.
Figure 15.A slight change in tuning word yields
dramatically better results. 112.499 MHz with all
spurs shifted out-of-band.
Figures 16 and 17 show the narrowband performance of the AD9852 when operating with a 20 MHz reference clock and the
REFCLK Multiplier enabled at 10· vs. a 200 MHz external reference clock.
CENTER 39.1MHz
5kHz/SPAN 50kHz
Figure 16.Narrowband SFDR, 39.1 MHz, 50 kHz BW,
200 MHz EXTCLK with REFCLK Multiplier Bypassed
CENTER 39.1MHz
5kHz/SPAN 50kHz
Figure 17.Narrowband SFDR, 39.1 MHz, 50 kHz BW,
10 MHz EXTCLK with REFCLK Multiplier = 10·
DAC CURRENT – mA
SFDR – dBc510152025
Figure 19.SFDR vs. DAC Current, 59.1 MHz AOUT, 300 MHz
EXTCLK
FREQUENCY – MHz
SUPPLY CURRENT – mA
59020406080100120140
Figure 20.Supply Current vs. Output Frequency; Variation
FREQUENCY – Hz
PHASE NOISE – dBc/Hz
–15510k100kResidual Phase Noise 300 MHz Direct ClockingResidual Phase Noise, 300 MHz (10· REFCLK Multiplier
Enabled)
Figure 18.Residual Phase Noise, EXTCLK = 300 MHz, REFCLK Multiplier Disabled/Enabled at 10·
Figure 21.Typical Comparator Output Jitter, 40 MHz
AOUT, 300 MHz EXTCLK/REFCLK Multiplier Disabled
Figure 22.Comparator Rise/Fall Times
AD9852
FREQUENCY – MHz
AMPLITUDE – mV p-p
200100200300400500
Figure 23.Comparator Toggle Voltage Requirement
RF IN
Rx BASEBAND
DIGITAL DATA
OUT
VCA
Figure 25.Chip Rate Generator in Spread Spectrum Application
BANDPASS
FILTER
AD9852
SPECTRUM
FINAL OUTPUT
SPECTRUM
Figure 26.Using an Aliased Image to Generate a High
Frequency
REFERENCE
CLOCK
TUNING
WORD
FREQUENCY
OUT
DAC OUT
Figure 27.Programmable “Divide-by-N” Synthesizer
Figure 24.Synthesized L.O. Application for the AD9852
TUNING
WORD
REF
CLOCKRF
FREQUENCY
OUT
Figure 28.Agile High-Frequency Synthesizer
2kV
NOTES:
IOUT = APPROX 20mA MAX WHEN RSET = 2kV
SWITCH POSTION 1 PROVIDES COMPLEMENTARY SINUSOIDAL SIGNALS TO THE COMPARATOR
TO PRODUCE A FIXED 50% OUTPUT DUTY CYCLE FROM THE COMPARATOR.
SWITCH POSTION 2 PROVIDES A USER PROGRAMMABLE DC THRESHOLD VOLTAGE TO ALLOW
SETTING OF THE COMPARATOR OUTPUT DUTY CYCLE.
Figure 30.Frequency Agile Clock Generator Applications for the AD9852
(continued from page 1)
generation of a sine output at frequencies up to 150 MHz, which
can be digitally tuned at a rate of up to 100 million new frequencies
per second. The (externally ﬁltered) sine wave output can be
converted to a square wave by the internal comparator for agile
clock generator applications. The device provides 14 bits of
digitally-controlled phase modulation and single-pin PSK. The
on-board 12-bit DAC, coupled with the innovative DDS
architecture, provide excellent wideband and narrowband out-
put SFDR. There is also an auxiliary DAC that can be conﬁgured
as a user-programmable control DAC. When conﬁgured with
the on-board comparator, the 12-bit control DAC facilitates
duty cycle control, in the high-speed clock generator application. A
12-bit digital multiplier permits programmable amplitude modu-
lation, shaped on/off keying and precise amplitude control of
the output. Chirp functionality is also included which facilitates
wide bandwidth frequency sweeping applications. The AD9852’s
programmable 4·–20· REFCLK multiplier circuit generates
the 300 MHz clock internally from a lower frequency external
reference clock. This saves the user the expense and difﬁculty of
implementing a 300 MHz clock source. Direct 300 MHz clocking
is also accommodated with either single-ended or differential
inputs. Single-pin conventional FSK and the enhanced spectral
qualities of “ramped” FSK are supported. The AD9852 uses
The AD9852 is available in a space-saving 80-lead LQFP
surface-mount package and a thermally-enhanced 80-lead LQFP
package. The AD9852 is pin-for-pin compatible with the AD9854
quadrature output synthesizer device. It is speciﬁed to operate over
the extended industrial temperature range of –40°C to +85°C.
OVERVIEW
The AD9852 digital synthesizer is a highly flexible device that
will address a wide range of applications. The device consists
of an NCO with 48-bit phase accumulator, programmable ref-
erence clock multiplier, inverse sinc ﬁlters, digital multipliers,
two 12-bit/300 MHz DACs, high-speed analog comparator,
and interface logic. This highly integrated device can be conﬁg-
ured to serve as a synthesized L.O., agile clock generator, and
FSK/BPSK modulator. The theory of operation of the func-
tional blocks of the device, and a technical description of the
signal flow through a DDS device, can be found in a tutorial
from Analog Devices, called, “A Technical Tutorial on Digital
Signal Synthesis.” This tutorial is available on CD-ROM and
information on obtaining it can be found at the Analog Devices
DDS website at /dds. The tutorial also
provides basic applications information for a variety of digital
synthesis implementations. The DDS background subject matter is
Figure 29.Differential Output Connection for Reduction of
Common-Mode Signals
AD9852
USING THE AD9852
Internal and External Update Clock
This function is comprised of a bidirectional I/O pin, Pin 20, and a
programmable 32-bit down-counter. In order for programming
changes to be transferred from the I/O Buffer registers to the active
core of the DDS, a clock signal (low-to-high edge) must be externally
supplied to Pin 20 or internally generated by the 32-bit Update Clock.
An externally generated Update Clock is internally synchronized
with the system clock to prevent partial transfer of program
register information due to violation of data setup or hold times.
This mode gives the user complete control of when updated
program information becomes effective. The default mode is set
for internal update clock (Int Update Clk control register bit is
logic high). To switch to external update clock mode, the Int
Update Clk register bit must be set to logic low. The internal
update mode generates automatic, periodic update pulses whose
time period is set by the user.
An internally generated Update Clock can be established by
programming the 32-bit Update Clock registers (address 16–19
hex) and setting the Int Update Clk (address 1F hex) control
register bit to logic high. The update clock down-counter function
operates at the system clock/2 (150 MHz maximum) and counts
down from a 32-bit binary value (programmed by the user).
When the count reaches 0, an automatic I/O Update of the DDS
output or functions is generated. The update clock is routed
internally and externally on Pin 20 to allow users to synchronize
programming of update information with the update clock rate.
The time period between update pulses is given as:
(N+1) · (SYSTEM CLOCK PERIOD · 2)
where N is the 32-bit value programmed by the user. Allow-
able range of N is from 1 to (232 –1). The internally generated
update pulse output on Pin 20 has a ﬁxed high time of eight system
clock cycles.
Shaped On/Off Keying
Allows user to control the ramp-up and ramp-down time of an
“on/off” emission from the I and Q DACs. This function is
used in “burst transmissions” of digital data to reduce the adverse
spectral impact of short, abrupt bursts of data. Users must ﬁrst
enable the digital multipliers by setting the OSK EN bit (con-
trol register address 20 hex) to logic high in the control register.
Otherwise, if the OSK EN bit is set low, the digital multipliers
responsible for amplitude control are bypassed and the I and Q
DAC outputs are set to full-scale amplitude. In addition to
setting the OSK EN bit, a second control bit, OSK INT (also at
address 20 hex) must be set to logic high. Logic high selects the
linear internal control of the output ramp-up or ramp-down
function. A logic low in the OSK INT bit switches control of
ABRUPT ON/OFF KEYING
the digital multipliers to user programmable 12-bit registers
allowing users to dynamically shape the amplitude transition in
practically any fashion. These 12-bit registers, labeled “Out-
put Shape Key” are located at addresses 21 through 24 hex in
Table V. The maximum output amplitude is a function of the
RSET resistor and is not programmable when OSK INT is enabled.
Next, the transition time from zero-scale to full-scale must
be programmed. The transition time is a function of two ﬁxed
elements and one variable. The variable element is the program
mable 8-bit RAMP RATE COUNTER. This is a down-counter
being clocked at the system clock rate (300 MHz max) that
outputs one pulse whenever the counter reaches zero. This pulse
is routed to a 12-bit counter that increments one LSB for every
pulse received. The outputs of the 12-bit counter are connected
to the 12-bit digital multiplier. When the digital multiplier has a
value of all zeros at its inputs, the input signal is multiplied by
zero, producing zero-scale. When the multiplier has a value of
all ones, the input signal is multiplied by a value of one, producing
full-scale. There are 4094 remaining fractional multiplier values
that will produce output amplitudes corresponding to their
binary values.
Figure 32.Block Diagram of Data Pathway of the Digital
Multiplier Section Responsible for Shaped Keying Function
The two ﬁxed elements are the clock period of the system clock,
which drives the Ramp Rate Counter, and the 4096 amplitude
steps between zero-scale and full-scale. To give an example,
assume that the System Clock of the AD9852 is 100 MHz (10 ns
period). If the Ramp Rate Counter is programmed for a minimum
count of five, it will take two system clock periods (one rising
edge loads the count-down value, the next edge decrements the
counter from five to four). The relationship of the 8-bit count-
down value to the time period between output pulses is given as:
(N+1) · SYSTEM CLOCK PERIOD,
where N is the 8-bit count-down value. It will take 4096 of these
pulses to advance the 12-bit up-counter from zero-scale to full-
scale. Therefore, the minimum shaped keying ramp time for a
100 MHz system clock is 4096 · 6 · 10 ns = approximately
246 ms. The maximum ramp time will be 4096 · 256 · 10 ns =
approximately 10.5 ms.
Finally, changing the logic state of Pin 30, “shaped keying” will
automatically perform the programmed output envelope functions
when OSK INT is high. A logic high on Pin 30 causes the out-
puts to linearly ramp up to full-scale amplitude and hold until
the logic level is changed to low, causing the outputs to ramp
down to zero-scale.
Cosine DAC
The cosine DAC generates the 300 MSPS (maximum) cosine
output of the DDS. The maximum output amplitude is set
by the DAC RSET resistor at Pin 56. This is a current-out DAC
with a full-scale maximum output of 20 mA; however, a nomi-
nal 10 mA output current provides best spurious-free dynamic
range (SFDR) performance. The value of RSET = 39.93/IOUT,
where IOUT is in amps. DAC output compliance speciﬁcation lim-
its the maximum voltage developed at the outputs to –0.5 V to
+1 V. Voltages developed beyond this limitation will cause exces-
sive DAC distortion and possibly permanent damage. The user
must choose a proper load impedance to limit the output voltage
swing to the compliance limits. For best SFDR, both DAC outputs
should be terminated equally, especially at higher output fre-
quencies where harmonic distortion errors are more prominent.
The cosine DAC is preceded by inverse SIN(x)/x ﬁlters (a.k.a.
inverse sinc ﬁlter) that precompensate for DAC output amplitude
variations over frequency to achieve flat amplitude response from
dc to Nyquist. A digital multiplier follows the inverse sinc ﬁlters
to allow amplitude control, amplitude modulation and ampli-
tude shaped keying. The inverse sinc ﬁlter (address 20 hex, Bypass
Inv Sinc bit)) and digital multiplier (address 20 hex, OSK EN
bit) can be bypassed for power conservation by setting those bits
high. Both DACs can be powered down by setting the DAC PD
bit high (address 1D of control register) when not needed.
Cosine DAC outputs are designated as IOUT1 and IOUT1B,
Pins 48 and 49 respectively.
Control DAC
The 12-bit auxiliary, or control DAC can provide dc control
levels to external circuitry, generate ac signals, or duty cycle con-
trol, of the on-board comparator. The input twos complement
data is channeled through the serial or parallel interface to the
12-bit register (address 26 and 27 hex) at a maximum 100 MHz
data rate. This DAC is clocked at the system clock, 300 MSPS
(maximum), and has the same maximum output current capa-
bility as that of the cosine DAC. The single RSET resistor on the
AD9852 sets the full-scale output current for both cosine DAC
and the control DACs. The control DAC can be separately
powered down for power conservation when not needed by
setting the Control DAC POWER-DOWN bit high (address
1D hex). Control DAC outputs are designated as IOUT2 and
IOUT2B (Pins 52 and 51 respectively).
Figure 33.Normal SIN(x)/x DAC Output Power Envelope
Filter
Figure 34.Inverse SIN(x)/x (Inverse Sinc) Filter Engaged
Inverse SINC Function
This ﬁlter precompensates input data to the cosine DAC for
the SIN(x)/x roll-off function to allow wide bandwidth signals
(such as QPSK) to be output from the DACs without appreciable
amplitude variations that will cause increased EVM (error vector
magnitude). The inverse SINC function may be bypassed to
signiﬁcantly reduce power consumption, especially at higher
clock speeds. Inverse sinc is engaged by default and is bypassed
by bringing the “Bypass Inv Sinc” bit high in control register 20
(hex) in Table V.
REFCLK Multiplier
This is a programmable PLL-based reference clock multiplier
that allows the user to select an integer clock multiplying value
over the range of 4· to 20· by which the REFCLK input will be
multiplied. Use of this function allows users to input as little as
15 MHz to produce a 300 MHz internal system clock. Five bits
in control register 1E hex set the multiplier value as follows in
Table I.
AD9852
Table I.REFCLK Multiplier Control Register Values
The REFCLK Multiplier function can be bypassed to allow
direct clocking of the AD9852 from an external clock source.
The system clock for the AD9852 is either the output of the
REFCLK Multiplier (if it is engaged) or the REFCLK inputs.
REFCLK may be either a single-ended or differential input by
setting Pin 64, DIFF CLK ENABLE, low or high respectively.
PLL Range Bit
The PLL Range Bit selects the frequency range of the REFCLK
Multiplier PLL. For operation from 200 MHz to 300 MHz
(internal system clock rate) the PLL Range Bit should be set to
Logic 1. For operation below 200 MHz, the PLL Range Bit
should be set to Logic 0. The PLL Range Bit adjusts the PLL
loop parameters for optimized phase noise performance within
each range.
Pin 61, PLL FILTER
This pin provides the connection for the external zero compen-
sation network of the PLL loop ﬁlter. The zero compensation
network consists of a 1.3 kW resistor in series with a 0.01 mF
capacitor. The other side of the network should be connected to
as close as possible to Pin 60, AVDD. For optimum phase noise
performance the clock multiplier can be bypassed by setting the
“Bypass PLL” bit in control register address 1E.
Differential REFCLK Enable
A high level on this pin enables the differential clock Inputs,
REFCLOCK and REFCLOCKB (Pins 69 and 68 respec-
tively). The minimum differential signal amplitude required
is 800 mV p-p. The centerpoint or common-mode range of the
differential signal can range from 1.6 V to 1.9 V.
When Pin 64 (DIFF CLK ENABLE) is tied low, REFCLK
(Pin 69) is the only active clock input. This is referred to as
the single-ended mode. In this mode, Pin 68 (REFCLKB) should
be tied low or high, but not left floating.
Parallel/Serial Programming Mode
Setting Pin 70 high invokes parallel mode, whereas setting Pin
70 low will invoke the serial programming mode. Please refer
to the text describing the serial and parallel programming
protocol contained in this data sheet for further information.
Two control bits located at address 20 hex in the Table V apply
only to the serial programming mode. LSB First when high,
dictates that serial data will be loaded starting with the LSB of
the word. When low (the default value), serial data is loaded
starting with the MSB of the word. SDO Active when high
indicates that the SDO pin, Pin 18, is dedicated to reading back
data from the AD9852 registers. When SDO Active is low
(default value), this indicates that the SDIO pin, Pin 19, acts
as a bidirectional serial data input and output pin and Pin 18
has no function in the serial mode.
DESCRIPTION OF AD9852 MODES OF OPERATION
There are ﬁve programmable modes of operation of the AD9852.
Selecting a mode requires that three bits in the Control Register
(parallel address 1F hex) be programmed as follows in Table II.
Table II.Mode Selection Table
In each mode, engaging certain functions may or may not be
permitted. Shown in Table III is a listing of some important
functions and their availability for each mode.
Single-Tone (Mode 000)
This is the default mode when master reset is asserted or when
it is user-programmed into the control register. The Phase
Accumulator, responsible for generating an output frequency, is
presented with a 48-bit value from Frequency Tuning Word 1
registers whose default values are zero. Default values from the
remaining applicable registers will further deﬁne the single-tone
output signal qualities.
The default values after a master reset, deﬁne a safe, “no output”
value resulting in an output signal of 0 Hertz, 0 phase. Upon
power-up and reset the output from both I and Q DACs will be
a dc value equal to the midscale output current. This is the
default mode amplitude setting of zero. Refer to the digital multi-
plier section for further explanation of the output amplitude
control. It will be necessary to program all or some of the 28
program registers to realize a user-deﬁned output signal.
Figure 35 graphically shows the transition from the default con-
dition (0 Hz) to a user-deﬁned output frequency (F1).
As with all Analog Devices DDSs, the value of the frequency
tuning word is determined using the following equation:
FTW = (Desired Output Frequency · 2N)/SYSCLK.
Figure 35.Default State to User-Deﬁned Output Transition
Where N is the phase accumulator resolution (48 bits in this
instance), frequency is expressed in Hertz, and the FTW,
Frequency Tuning Word, is a decimal number. Once a decimal
number has been calculated, it must be rounded to an integer
and then converted to binary format—a series of 48 binary-
weighted 1s or 0s. The fundamental sine wave DAC output
frequency range is from dc to 1/2 SYSCLK.
Changes in frequency are phase continuous—that is, the new
frequency uses the last phase of the old frequency as the reference
point to compute the ﬁrst new frequency phase.
The single-tone mode allows the user to control the following
signal qualities:Output Frequency to 48-Bit AccuracyOutput Amplitude to 12-Bit AccuracyFixed, User-Deﬁned, Amplitude ControlVariable, Programmable Amplitude ControlAutomatic, Programmable, Single-Pin-Controlled, “Shaped
On/Off Keying”Output Phase to 14-Bit Accuracy
Furthermore, all of these qualities can be changed or modulated
via the 8-bit parallel programming port at a 100 MHz parallel-byte
rate, or at a 10 MHz serial rate. Incorporating this attribute will
permit FM, AM, PM, FSK, PSK, ASK operation in the single-
tone mode.
Table III.Function Availability vs. Mode of Operation
AD9852
Unramped FSK (Mode 001)
When selected, the output frequency of the DDS is a function
of the values loaded into Frequency Tuning Word registers 1
and 2 and the logic level of Pin 29 (FSK/BPSK/HOLD). A logic
low on Pin 29 chooses F1 (frequency tuning word 1, parallel
address 4–9 hex) and a logic high chooses F2 (frequency tuning
word 2, parallel register address A–F hex). Changes in frequency
are phase-continuous and practically instantaneous. (Please refer to
pipeline delays in speciﬁcation table.) Other than F2 and Pin 29
becoming active, this mode is identical to single-tone.
The unramped FSK mode, Figure 36, is representative of
traditional FSK, RTTY (Radio Teletype) or TTY (Teletype)
transmission of digital data. Frequency transitions occur nearly
instantaneously from F1 to F2. This simple method works
extremely well and is the most reliable form of digital communica-
tion, but it is also wasteful of RF spectrum.
See the following Ramped FSK section for an alternative FSK
method that conserves bandwidth.
Ramped FSK (Mode = 010)
A method of FSK whereby changes from F1 to F2 are not
instantaneous but instead are accomplished in a frequency
sweep or “ramped” fashion. The “ramped” notation implies
that the sweep is linear. While linear sweeping or frequency
ramping is easily and automatically accomplished, it is only one
of many possibilities. Other frequency transition schemes may
be implemented by changing the ramp rate and ramp step size
“on-the-fly,” in piecewise fashion.
Frequency ramping, whether linear or nonlinear, necessitates
that many intermediate frequencies between F1 and F2 will be
output in addition to the primary F1 and F2 frequencies. Fig-
ures 37 and 38 graphically depict the frequency versus time
characteristics of a linear ramped FSK signal.
The purpose of ramped FSK is to provide better bandwidth
containment than traditional FSK by replacing the instantaneous
frequency changes with more gradual, user-deﬁned frequency
changes. The dwell time at F1 and F2 can be equal to or much
greater than the time spent at each intermediate frequency. The
user controls the dwell time at F1 and F2, the number of inter-
mediate frequencies and time spent at each frequency. Unlike
unramped FSK, ramped FSK requires the lowest frequency to be
loaded into F1 registers and the highest frequency into F2 registers.
Several registers must be programmed to instruct the DDS
regarding the resolution of intermediate frequency steps (48
bits) and the time spent at each step (20 bits). Furthermore, the
CLR ACC1 bit in the control register should be toggled (low-high-
low) prior to operation to assure that the frequency accumulator
is starting from an “all zeros” output condition. For piecewise,
nonlinear frequency transitions, it is necessary to reprogram the
registers while the frequency transition is in progress to affect the
desired response.
Figure 36.Traditional FSK Mode
Parallel register addresses 1A–1C hex comprise the 20-bit “Ramp
Rate Clock” registers. This is a count-down counter that outputs a
single pulse whenever the count reaches zero. The counter is
activated any time a logic level change occurs on FSK input
Pin 29. This counter is run at the System Clock Rate, 300 MHz
maximum. The time period between each output pulse is given as
(N+1) · (SYSTEM CLOCK PERIOD)
where N is the 20-bit ramp rate clock value programmed by the
user. Allowable range of N is from 1 to (220 –1). The output of
this counter clocks the 48-bit Frequency Accumulator shown be-
low in Figure 39. The Ramp Rate Clock determines the amount
of time spent at each intermediate frequency between F1 and F2.
The counter stops automatically when the destination frequency
is achieved. The “dwell time” spent at F1 and F2 is determined
by the duration that the FSK input, Pin 29, is held high or low
after the destination frequency has been reached.
FREQUENCY
ACCUMULATOR
ACCUMULATOR
OUT
ADDER
FSK
(PIN 29)
Figure 39.Block Diagram of Ramped FSK Function
Parallel register addresses 10–15 hex comprise the 48-bit, straight
binary, “Delta Frequency Word” registers. This 48-bit word
is accumulated (added to the accumulator’s output) every time
it receives a clock pulse from the ramp rate counter. The output
Figure 38.Ramped FSK Mode
is ramped up and down in frequency, according to the logic-
state of Pin 29. The rate at which this happens is a function of
the 20-bit ramp rate clock. Once the destination frequency is
achieved, the ramp rate clock is stopped, which halts the frequency
accumulation process.
Generally speaking, the Delta Frequency Word will be a much
smaller value as compared to that of the F1 or F2 tuning word.
For example, if F1 and F2 are 1 kHz apart at 13 MHz, the Delta
Frequency Word might be only 25 Hz.
Figure 41 shows that premature toggling causes the ramp to
immediately reverse itself and proceed at the same rate and resolu-
tion back to originating frequency.
The control register contains a Triangle bit at parallel register
address 1F hex. Setting this bit high in Mode 010 causes an
automatic ramp-up and ramp-down between F1 and F2 to occur
without having to toggle Pin 29 as shown in Figure 40. In fact,
the logic state of Pin 29 has no effect once the Triangle bit is set
high. This function uses the ramp-rate clock time period and the
delta-frequency-word step size to form a continuously sweeping
linear ramp from F1 to F2 and back to F1 with equal dwell times
at every frequency. Using this function, one can automatically
sweep from dc to the Nyquist limit or any other two frequencies
between dc and Nyquist.
MODE
TW1
TW2
FSK DATA
AD9852
In the ramped FSK mode with the triangle bit set high an auto-
matic frequency sweep will begin at either F1 or F2, according
to the logic level on Pin 29 (FSK input pin) when the triangle
bit’s rising edge occurs as shown in Figure 42. If the FSK data bit
had been high instead of low, F2 would have been chosen instead
of F1 as the start frequency.
MODE
TW1
TW2
FSK DATA
TRIANGLE BIT
Figure 42.Automatic Linear Ramping Using the Triangle Bit
Additional flexibility in the ramped FSK mode is provided in
the ability to respond to changes in the 48-bit delta frequency
word and/or the 20-bit ramp-rate counter on-the-fly during the
ramping from F1 to F2 or vice versa. To create these nonlinear
frequency changes it is necessary to combine several linear
ramps in a piecewise fashion whose slopes are different. This is
done by programming and executing a linear ramp at some rate
or “slope” and then altering the slope (by changing the ramp
rate clock or delta frequency word or both). Changes in slope are
made as often as needed to form the desired nonlinear frequency
sweep response before the destination frequency has been reached.
These piecewise changes can be precisely timed using the 32-bit
Internal Update Clock (see detailed description elsewhere in
Figure 41.Effect of Premature Ramped FSK Data
Nonlinear ramped FSK will have the appearance of a chirp
function that is graphically illustrated in Figure 43. The major
difference between a ramped FSK function and a chirp function
is that FSK is limited to operation between F1 and F2. Chirp
operation has no F2 limit frequency.
Two additional control bits are available in the ramped FSK mode
that allow even more options. CLR ACC1, register address 1F
hex, will, if set high, clear the 48-bit frequency accumulator (ACC1)
output with a retriggerable one-shot pulse of one system clock
duration. If the CLR ACC1 bit is left high, a one-shot pulse will
be delivered on the rising edge of every Update Clock. The
effect is to interrupt the current ramp, reset the frequency back
to the start point, F1 or F2, and then continue to ramp up (or
down) at the previous rate. This will occur even when a static F1
or F2 destination frequency has been achieved. (See Figure 43.)
Next, CLR ACC2 control bit (register address 1F hex) is avail-
able to clear both the frequency accumulator (ACC1) and the phase
accumulator (ACC2). When this bit is set high, the output of the
phase accumulator will result in 0 Hz output from the DDS. As
long as this bit is set high, the frequency and phase accumula-
tors will be cleared, resulting in 0 Hz output. To return to
previous DDS operation, CLR ACC2 must be set to logic low.
Chirp (Mode 011)
This mode is also known as pulsed FM. Most chirp systems use
a linear FM sweep pattern although any pattern may be used.
This is a type of spread spectrum modulation that can realize
“processing gain.” In radar applications, use of chirp or pulsed
FM allows operators to signiﬁcantly reduce the output power
needed to achieve the same result as a single-frequency radar
system would produce. Figure 43 represents a very low-resolution
nonlinear chirp meant to demonstrate the different “slopes” that
are created by varying the time steps (ramp rate) and frequency
steps (delta frequency word).
The AD9852 permits precise, internally generated linear or
externally programmed nonlinear pulsed or continuous FM over
a user-deﬁned frequency range, duration, frequency resolution and
sweep direction(s). A block diagram of the FM chirp components
is shown in Figure 44.
FREQUENCY
ACCUMULATOR
ACCUMULATOR
OUT
ADDER
CLR ACC2
CLR ACC1
HOLD
Figure 44.FM Chirp Components
Basic FM Chirp Programming StepsProgram a start frequency into Frequency Tuning Word 1
(parallel register addresses 4–9 hex) hereafter called FTW1.Program the frequency step resolution into the 48-bit, twos
complement, Delta Frequency Word (parallel register addresses
10–15 hex).Program the rate of change (time at each frequency) into the
20-bit Ramp Rate Clock (parallel register addresses 1A–C).When programming is complete, an I/O update pulse at Pin
20 will engage the program commands.
The necessity for a twos complement Delta Frequency Word is
to deﬁne the direction in which the FM chirp will move. If the
48-bit delta frequency word is negative (MSB is high), the
incremental frequency changes will be in a negative direction from
FTW1. If the 48-bit word is positive (MSB is low), the incre-
mental frequency changes will be in a positive direction.
Figure 43.Example of a Nonlinear Chirp
It is important to note that the FTW1 is only a starting point for
FM chirp. There is no built-in restraint requiring a return to
FTW1. Once the FM chirp has left FTW1 it is free to move
(under program control) within the Nyquist bandwidth (dc to
1/2 system clock). Instant return to FTW1 is easily achieved,
though, and this option is explained in the next few paragraphs.
Two control bits are available in the FM Chirp mode that will
allow practically instantaneous return to the beginning frequency,
FTW1, or to 0 Hz. First, CLR ACC1 bit, register address 1F
hex will, if set high, clear the 48-bit frequency accumulator (ACC1)
output with a retriggerable one-shot pulse of one system clock
duration. The 48-bit Delta Frequency Word input to the accu-
mulator is unaffected by CLR ACC1 bit. If the CLR ACC1 bit
is left high, a one-shot pulse will be delivered to the Frequency
Accumulator (ACC1) on every rising edge of the I/O Update
Clock. The effect is to interrupt the current chirp, reset the
frequency back to FTW1, and continue the chirp at the previously
programmed rate and direction. Clearing the Frequency
Accumulator in the chirp mode is illustrated in Figure 45. Not
shown in the diagram is the I/O update signal, which is either
user-supplied or internally generated. A discussion of I/O Update
is presented elsewhere in this data sheet.
Next, CLR ACC2 control bit (register address 1F hex) is available to
clear both the frequency accumulator (ACC1) and the phase
accumulator (ACC2). When this bit is set high, the output of the
phase accumulator will result in 0 Hz output from the DDS. As
long as this bit is set high, the frequency and phase accumulators
will be cleared, resulting in 0 Hz output. To return to previous
DDS operation, CLR ACC2 must be set to logic low. This bit is
useful in generating pulsed FM.

Partno	Mfg	Dc	Qty	Available	Descript
AD9852ASQ	ADAPTEC	N/a	470	avai	CMOS 300 MHz Complete-DDS
AD9852AST	ADI	N/a	5	avai	CMOS 300 MHz Complete-DDS