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AD9851BRSZ-AD9851BRSZRL
180 MHz Complete DDS synthesizer
ANALOG
DEVICES
CMOS 180 MHz
DDS/DAB Synthesizer
A09851
FEATURES
180 MHz Clock Rate with Selectable 6x Reference Clock
Multiplier
On-Chip High Performance 10-Bit DAC and High Speed
Comparator with Hysteresis
SFDR >43 dB @ 70 MHz AOUT
32-Bit FrequencyTuning Word
Simplified Control Interface: Parallel or Serial
Asynchronous Loading Format
5-Bit Phase Modulation and Offset Capability
Comparator Jitter <80 ps p-p @ 20 MHz
2.7 V to 5.25 V Single-Supply Operation
Low Power: 555 mW @ 180 MHz
Power-Down Function, 4 mW @ 2.7 V
Ultrasmall 28-Lead SSOP Packaging
APPLICATIONS
Frequency/Phase-Agile SineWave Synthesis
Clock Recovery and Locking Circuitry for Digital
Communications
Digitally Controlled ADC Encode Generator
Agile Local Oscillator Applications in Communications
Quadrature Oscillator
CW,AM, FM, FSK, MSK ModeTransmitter
GENERAL DESCRIPTION
The AD9851 is a highly integrated device that uses advanced
DDS technology, coupled with an internal high speed, high
performance D/A converter, and comparator, to form a digitally
programmable frequency synthesizer and clock generator func-
tion. When referenced to an accurate clock source, the AD9851
generates a stable frequency and phase-programmable digitized
analog output sine wave. This sine wave can be used directly as
a frequency source, or internally converted to a square wave for
agile-clock generator applications. The AD9851's innovative
high speed DDS core accepts a 32-bit frequency tuning word,
which results in an output tuning resolution of approximately
0.04 Hz with a 180 MHz system clock. The AD9851 contains
a unique 6)4 REFCLK Multiplier circuit that eliminates the
need for a high speed reference oscillator. The 6X REFCLK
Multiplier has minimal impact on SFDR and phase noise char-
acteristics. The AD9851 provides five bits of programmable
phase modulation resolution to enable phase shifting of its
output in increments of 11.25°.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed byAnalog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
+VS GND
AD9851 C.' DAC RSET
REF 6x REFCLK -N,
CLOCK INI: MULTIPLIER HIGH SPEED ANALOG
MASTER
RESET [V
32- {me PHASE
WORD COSEEgL|> ANALOG
FREQUENCY
UPDATE/DATA '- ''Rg%lf2ll'l'lti"
REGISTER
RESET CDs) CLOCK OUT
WORD LOAD toATAiNPuTrtEmsrER - -
CLOCK DATA INPUT REGISTER - CLOCK OUT
SERIAL COMPARATOR
PARALLEL
LOAD LOAD
1 BIT X 8 BITS X
40 LOADS 5 LOADS
FREQUENCY, PHASE
AND CONTROL DATA INPUT
The AD9851 contains an internal high speed comparator that
can be configured to accept the (externally) filtered output of the
DAC to generate a low jitter output pulse.
The frequency tuning, control, and phase modulation words are
asynchronously loaded into the AD9851 via a parallel or serial
loading format. The parallel load format consists of five iterative
loads of an 8-bit control word (byte). The first 8-bit byte controls
output phase, 6)4 REFCLK Multiplier, power-down enable and
loading format; the remaining bytes comprise the 32-bit frequency
tuning word. Serial loading is accomplished via a 40-bit serial data
stream entering through one of the parallel input bus lines. The
AD9851 uses advanced CMOS technology to provide this break-
through level of functionality on just 555 mW of power dissipation
(5 V supply), at the maximum clock rate of 180 MHz.
The AD9851 is available in a space-saving 28-lead SSOP,
surface-mount package that is pin-for-pin compatible with the
popular AD9850 125 MHz DDS. It is specified to operate over
the extended industrial temperature range of -4(y'C to +85°C
at >3.0 V supply voltage. Below 3.0 V, the specifications apply
over the commercial temperature range of 0°C to 85°C.
One Technology Way, RO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703 © 2004 Analog Devices, |nc.All rights reserved.
Jllyl851-SPEillFliWl0lG
(gsl = 5 ll i 5%, Rss, = 3.9 kn, " REFCLK Multiplier Disabled, External Reference
Clock = 18ll MHz, except " noted.)
Test AD9851BRS
Parameter Temp Level Min Typ Max Unit
CLOCK INPUT CHARACTERISTICS
Frequency Range (6X REFCLK Multiplier Disabled)
5.0 V Supply Full IV 1 180 MHz
3.3 V Supply Full IV 1 125 MHz
2.7 V Supply 0°C to 85°C IV 1 100 MHz
Frequency Range (6X REFCLK Multiplier Enabled)
5.0 V Supply Full IV 5 30 MHz
3.3 V Supply Full IV 5 20.83 MHz
2.7 V Supply 0°C to 85°C IV 5 16.66 MHz
Duty Cycle Full IV 45 60 %
Duty Cycle (6X REFCLK Multiplier Enabled) Full IV 35 65 %
Input Resistance 25°C V 1 M9
Minimum Switching Threshold
Logic l, 5.0 V Supply 25°C IV 3.5 V
Logic l, 3.3 V Supply 25°C IV 2.3 V
Logic 0, 5.0 V Supply 25°C IV 1.5 V
Logic 0, 3.3 V Supply 25°C IV V
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current 25°C IV 5 10 20 mA
Gain Error 25°C I -10 +10 % FS
Output Offset 25°C I 10 yA
Differential Nonlinearity 25°C I 0.75 LSB
Integral Nonlinearity 25°C I 1 LSB
Residual Phase Noise, 5.2 MHz, 1 kHz Offset
PLL On 25°C V -125 dBc/Hz
PLL Off 25°C V -132 dBc/Hz
Output Impedance 25°C V 120 k!)
Voltage Compliance Range 25°C I A).5 +1.5 V
Wideband Spurious-Free Dynamic Range
1.1 MHz Analog Out (DC to 72 MHz) 25°C IV 60 64 dBc
20.1 MHz Analog Out (DC to 72 MHz) 25°C IV 51 53 dBc
40.1 MHz Analog Out (DC to 72 MHz) 25°C IV 51 55 dBc
50.1 MHz Analog Out (DC to 72 MHz) 25°C IV 46 53 dBc
70.1 MHz Analog Out (DC to 72 MHz) 25°C IV 42 43 dBc
Narrowband Spurious-Free Dynamic Range
1.1 MHz (t50 kHz) 25°C V 85 dBc
1.1 MHz (i200 kHz) 25°C V 80 dBc
40.1 MHz (-+50 kHz) 25°C V 85 dBc
40.1 MHz (i200 kHz) 25°C V 80 dBc
70.1 MHz ($50 kHz) 25°C V 85 dBc
70.1 MHz (i200 kHz) 25°C V 73 dBc
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance 25°C V 3 pF
Input Resistance 25°C IV 500 ldl
Input Bias Current 25°C I 12 pA
InputVoltage Range 25°C IV 0 5 V
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1Voltage 5V Supply 25°C VI 4.8 V
Logic lVoltage 3.3V Supply 25°C VI 3.1 V
Logic 1Voltage 2.7V Supply 25°C VI 2.3 V
Logic 0 Voltage 25°C VI +0.4 V
Continuous Output Current 25°C IV 20 mA
Hysteresis 25°C IV 10 mV
Propagation Delay 25°C IV 7 ns
Toggle Frequency (1 V p-p Input Sine Wave) 25°C IV 200 MHz
Rise/FallTime, 15 pF Output Load 25°C IV 7 ns
Output Jitter (p-p)3 25°C IV 80 ps (p-p)
CLOCK OUTPUT CHARACTERISTICS
Output Jitter (Clock Generator Configuration,
40 MHz IV p-p Input Sine Wave) 25°C V 250 ps (p-p)
Clock Output Duty Cycle Full IV 50 i' 10 %
REV. D
A0985]
Test AD9851BRS
Parameter Temp Level Min Typ Max Unit
TIMING CHARACTERISTICS4
tWH, twt (W_CLK Min Pulse Width High/Low) Full IV 3.5 ns
tos, tDH (Data to W_CLK Setup and Hold Times) Full IV 3.5 ns
tFH, tFL (FQ_UD Min Pulse Width High/Low) Full IV 7 ns
tco (REFCLK Delay After FQ_UD)5 Full IV 3.5 ns
tFD (FQ_UD Min Delay After W_CLK) Full IV 7 ns
tCF (Output Latency from FQ_UD)
Frequency Change Full IV 18 SYSCLK
Cycles
Phase Change Full IV 13 SYSCLK
Cycles
tRH (CLKIN Delay After RESET Rising Edge) Full IV 3.5 ns
tRL (RESET Falling Edge After CLKIN) Full IV 3.5 ns
tRR (Recovery from RESET) Full IV 2 SYSCLK
Cycles
tRs (Minimum RESET Width) Full IV 5 SYSCLK
Cycles
tot (RESET Output Latency) Full IV 13 SYSCLK
Cycles
Wake-Up Time from Power-Down Mode6 25°C V 5 us
CMOS LOGIC INPUTS
Logic 1Voltage, 5V Supply 25°C I 3.5 V
Logic lVoltage, 3.3V Supply 25°C IV 2.4 V
Logic 1Voltage, 2.7V Supply 25°C IV 2.0 V
Logic 0 Voltage 25°C IV 0.8 V
Logic 1 Current 25°C I 12 "
Logic 0 Current 25°C I 12 11A
Rise/Fall Time 2 5°C IV 100 ns
Input Capacitance 25°C V 3 pF
POWER SUPPLY
vp Current @:
62.5 MHz Clock, 2.7 V Supply 25°C VI 30 35 mA
100 MHz Clock, 2.7 V Supply 25°C VI 40 50 mA
62.5 MHz Clock, 3.3 V Supply 25°C VI 35 45 mA
125 MHz Clock, 3.3V Supply 25°C VI 55 70 mA
62.5 MHz Clock, 5 V Supply 25°C VI 50 65 mA
125 MHz Clock, 5 V Supply 25''C VI 70 90 mA
180 MHz Clock, 5V Supply 25°C VI 110 130 mA
Power Dissipation @ :
62.5 MHz Clock, 5 V Supply 25°C VI 250 325 mW
62.5 MHz Clock, 3.3V Supply 25°C VI 115 150 mW
62.5 MHz Clock, 2.7 V Supply 25°C VI 85 95 mW
100 MHz Clock, 2.7V Supply 25°C VI 110 135 mW
125 MHz Clock, 5V Supply 25°C VI 365 450 mW
125 MHz Clock, 3.3V Supply 25°C VI 180 230 mW
180 MHz Clock, 5 V Supply 25°C VI 555 650 mW
Pmss Power-Down Mode C:
5V Supply 25°C VI 17 55 mW
2.7 V Supply 25°C VI 20 mW
1+VS collectively refers to the positive voltages applied to DVDD, PVCC, and AVDD.Voltages applied to these pins should be of the same potential.
ZIndicates the minimum signal levels required to reliably clock the device at the indicated supply voltages. This specifies the p-p signal level and dc offset needed when the
clocking signal is not of CMOS/IT L origin, i.e., a sine wave with 0V dc offset.
3The comparator's jitter contribution to any input signal.This is the minimum jitter on the outputs that can be expected from an ideal input. Considerably more output
jitter is seen when nonideal input signals are presented to the comparator inputs. Nonideal characteristics include the presence of extraneous, nonharmonic signals (spur's,
noise), slower slew rate, and low comparator overdrive.
4Timing of input signals FQ_UD,WCLK, RESET are asynchronous to the reference clock; however, the presence of a reference clock is required to implement those
functions. In the absence of a reference clock, the AD9851 automatically enters power-down mode rendering the IC, including the comparator, inoperable until a refer-
ence clock is restored.Very high speed updates of frequency/phase word will require FQ_UD and WCLK to be externally synchronized with the external reference clock to
ensure proper timing.
5Not applicable when " REFCLK Multiplier is engaged.
6Assumes no capacitive load on DACBP (Pin 17).
Specifications subject to change without notice.
REV. D
AD9851
ABSOLUTE MAXIMUM RATINGS''
Maximum Junction Temperature ................... 150°C
Storage Temperature ................... -65aC to +150°C
Vs ............................................ 6 V
Operating Temperature ................... -40oC to +85°C
Digital Inputs ...................... -0.7 V to +Vs + 0.7 V
Lead Temperature (10 sec) Soldering ................ 300°C
Digital Output Current .......................... 30 mA
SSOP BJAThermal Impedance ................... 82°C/W
DAC Output Current ........................... 30 mA
'Absolute maximum ratings are limiting values, to be applied individually, and beyond
which the serviceability of the circuit may be impaired. Functional operability under
any of these conditions is not necessarily implied. Exposure of absolute maximum
rating conditions for extended periods of time may affect device reliability.
EXPLANATION OF TEST LEVELS
Test Level
I - 100% Production Tested.
III - Sample Tested Only.
IV - Parameter is guaranteed by design and characterization
testing.
V - Parameter is a typical value only.
VI - Devices are 100% production tested at 25°C and guaran-
teed by design and characterization testing for industrial
operating temperature range.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9851BRS -4(Y'C to +85°C Shrink Small Outline (SSOP) RS-28
AD9851BRSRL -4(Y'C to +85°C Shrink Small Outline (SSOP) RS-28
AD9851/CGPCB Evaluation Board Clock Generator
AD9851/FSPCB Evaluation Board Frequency Synthesizer
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD9851 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Application Note: Users are cautioned not to apply digital input signals prior to power-up of this device.
Doing so may result in a latch-up condition.
ESD SENSITIVE DEVICE
REV. D
A0985]
PIN CONFIGURATION
03E . V E D4
D2 E E D5
D1 IE E De
LSB DO IE E D7 MSB/SERIAL LOAD
PGND IE E DGND
PVCCE AD9851 EDVDD
W_CLK IE TOP VIEW E RESET
FQ_UD IE (Not to Scale) E IOUT
REFCLOCKE E IOUTB
AGNDE E AGND
AVDD 11 E AVDD
RSET IE E DACBP
VOUTN 13 E VINP
VOUTP 14 E VINN
PIN FUNCTION DESCRIPTIONS
No. Mnemonic Function
4-1, DO-D 8-Bit Data Input. The data port for loading the 32-bit frequency and 8-bit phase/control words. D7 = MSB;
28-25 D0 = LSB. D7, Pin 25, also serves as the input pin for 40-bit serial data word.
5 PGND 6X REFCLK Multiplier Ground Connection.
6 PVCC 6X REFCLK Multiplier Positive Supply Voltage Pin.
7 SCCLK Word Load Clock. Rising edge loads the parallel or serial frequency/phase/control words asynchronously
into the 40-bit input register.
8 FQ_UD Frequency Update. A rising edge asynchronously transfers the contents of the 40-bit input register to be
acted upon by the DDS core. FQ_UD should be issued when the contents of the input register are known
to contain only valid, allowable data.
9 REFCLOCK Reference Clock Input. CMOS/TTL-level pulse train, direct or via the 6X REFCLK Multiplier. In direct
mode, this is also the SYSTEM CLOCK. If the 6X REFCLK Multiplier is engaged, then the output of the
multiplier is the SYSTEM CLOCK. The rising edge of the SYSTEM CLOCK initiates operations.
10, 19 AGND Analog Ground. The ground return for the analog circuitry (DAC and Comparator).
l 1, 18 AVDD Positive supply voltage for analog circuitry (DAC and Comparator, Pin 18) and bandgap voltage reference,
Pin II.
12 RSET The DAC's external RSET connection-nominally a 3.92 kft resistor to ground for 10 mA out.This sets
the DAC full-scale output current available from IOUT and IOUTB. RSET = 39.93/IOUT.
l3 VOUTN Voltage Output Negative. The comparator's complementary CMOS logic level output.
14 VOUTP Voltage Output Positive.The comparator's true CMOS logic level output.
15 VINN Voltage Input Negative.The comparator's inverting input.
16 VINP Voltage Input Positive. The comparator's noninverting input.
17 DACBP DAC Bypass Connection.This is the DAC voltage reference bypass connection normally NC (NO
CONNECT) for optimum SFDR performance.
20 IOUTB The complementary DAC output with same characteristics as IOUT except that IOUTB = (full-scale
output-IOL/D. Output load should equal that of IOUT for best SFDR performance.
21 IOUT The true output of the balanced DAC. Current is sourcing and requires current-to-voltage
conversion, usually a resistor or transformer referenced to GND. IOU T = (full-scale output-IOC/TB).
22 RESET Master Reset pin; active high; clears DDS accumulator and phase offset register to achieve 0 Hz and 0°
output phase. Sets programming to parallel mode and disengages the 6X REFCLK Multiplier. Reset does
not clear the 40-bit input register. On power-up, asserting RESET should be the first priority before pro-
gramming commences.
23 DVDD Positive supply voltage pin for digital circuitry.
24 DGND Digital Ground. The ground return pin for the digital circuitry.
REV. D -5-
hM851-Typical Performance Characteristics
RBW = 5kHz
-10 VBW = 5kHz
SWT = T.2s
-20 RF ATT = 20dB
REF LVL = -7dBm
OHz 7.2MHzl 72MHz
START STOP
TPC 1. Wideband (dc to 72 MHz) output SFDR for
a 1.1 MHz fundamental output signal. System
clock = 180 MHz (6X REFCLK multiplier engaged),
Vs = 5 V.
RBW = 5kHz
-10 VBW = 5kHz
SWT = 7.2s
-20 RF ATT = 20dB
REF LVL = -7dBm
-40 2AP
-100 .
0H2 7.2MHzl 72MHz
START STO P
TPC 2. Wideband (dc to 72 MHz) output SFDR for
a 40.1 MHz fundamental output signal. System
clock = 180 MHz (6X HEFCLK multiplier engaged),
Vs = 5 V.
RBW = 5kHz
-10 VBW = 5kHz
SWT = 7.2s
-20 RF ATT = 20:18
REF LVL = -NBm
0H1 7.2MHz/ 72MH2
START STOP
TPC 3. Wideband (dc to 72 MHz) output SFDR for
a 70.1 MHz fundamental output signal. System
clock = 180 MHz (6X REFCLK multiplier engaged),
VS = 5 V.
RBW = 300Hz
-10 VBW = 300Hz
SWT = 11.5s
-20 RF ATT = 20dB
REF LVL = -htBm
1.1MHz 20KHzl 200kHz
CENTER SPAN
TPC 4. Narrowband (1. 1 i- 0.1 MHz) output SFDR
for a 1.1 MHz fundamental output signal. System
clock =180 MHz (6X REFCLK multiplier engaged),
VS = 5 V
RBW = 300Hz
-10 VBW = 300Hz
SWT = 11.55
-20 RF ATT = 20dB
REF LVL = -NBm
40.1 MHz 200kHz
CENTER SPAN
TPC 5. Narrowband (40.1 i- 0.1 MHz) output SFDR
for a 40.1 MHz fundamental output signal. System
clock = 180 MHz (6X REFCLK multiplier engaged),
Vs = 5 V.
RBW = 300Hz
-10 VBW = 300Hz
SWT = 11.55
-20 RF ATT = 20dB
REF LVL = -7dBm
70.1MHz 20kHzl 200kHz
CENTER SPAN
TPC 6. Narrowband (70.1 i- 0.1 MHz) output SFDR
for a 70.1 MHz fundamental output signal. System
clock = 180 MHz (6X HEFCLK multiplier engaged),
Vs = 5 v.
REV. D
A0985]
Tek Run 4.00GS/s Sample
_A|:208;ls ii- i / /
@:1.940ns --
ii, /
1+m: (Ill ,'lll ,'lll ,,,,y,i-'(/rC,,,, llll ,'lll ,'lll
/ 25/: -
/ /ii I
// , (
Chl 200mm M12.5ns Ch1/-200mV
D 200ps Runs After
TPC 7. Typical CMOS comparatorp-p outputjitter with
the AD9851 configured as a clock generator, DDS four =
10.1 MHz, Vs = 5 V, system clock = 180 MHz, 70 MHz LPE
Graph details the center portion of a rising edge with
scope in delayed trigger mode, 200 ps/div. Cursors show
208 ps p-p jitter.
Tek Run 4.00GS/s Sample
- A : 204ps
@ :3.672ns
nun u... I|II
nu nu In:
1tll1tll 'litter'''''''''
nun” unuunuuuxuuu
Ch1 200mVn M 12.5ns Ch1 f -200mV
D 200ps Runs After
”N...“
TPC 8. Typical CMOS comparator p-p outputjitter with the
AD9851 configured as a clock generator, DDS four = 40.1 MHz,
Vs = 5 V, system clock = 180 MHz, 70 MHz LPF. Graph details
the center portion of a rising edge with scope in delayed
trigger mode, 200 ps/div. Cursors show 204 ps p-p jitter.
REV. D
I||| 'ttt tlet
run: run: llll
Illl |l|l I||| ll|l
III! In: llll IIII
IH/I/L
Tek Run 4.00GSls Sample
I I I CC
_A :280ps I CC / /
@ :2.668ns I c: /
I cc I
I 2: / /
1-> I _ V
Alll IAIA
In. I...
Ch1 200mWt
M 12.5ns Ch1 / -200mV
D 200ps Runs After
TPC 9. Typical CMOS comparator p-p output
jitter with the AD9851 configured as a clock
generator, DDS four = 70.1 MHz, Vs = 5 V, system
clock = 180 MHz, 70 MHz LPF. Graph details
the center portion ofa rising edge with scope
in delayed trigger mode, 200 ps/div. Cursors
show 280 ps p-p jitter.
I 1llll l I l I
AD9851 PHASE NOISE
MAGNITUDE — —dBcle
1k 10k
FREQUENCY OFFSET - Hz
TPC 10. Output Phase Noise (5.2 MHz AOUT), 6X REFCLK
Multiplier Enabled, System Clock = 180 MHz, Reference
Clock = 30 MHz
A0985]
Tek Stop 2.SOGSls 2227 Acgs
-120 lllllllll lllllll
AD9851 RESIDUAL PHASE NOISE
.' 2.3ns
-125 l : 103.6ns
C1 Fall
g -130 2.33ns
I -135 ,
t -140
g -145 1
-150 - _
100 1k 10k 100k cm 100mm M20.0ns Chl I 252mV
FREQUENCY OFFSET- Hz D 5.00ns Runs After
TPC 11. Output Residual Phase Noise (5.2 MHz Aour), 6X TPC 14. Comparator FalITime, 15 pF Load
REFCLK Multiplier Disabled, System Clock = 180 MHz, Ref-
erence Clock = 180 MHz
75 1 1 l 1 1
7o hc FUNDAMENTAL OUTPUT =
"C::::, SYSTEM CLOCKIS
I so . Vs = +3.3v g
tu 'ist A 2
55 vs = +511 k
"iss..,
45 IO 20 40 so so 100 120 140 160 180 o 10 20 so 40 so so 70
SYSTEM CLOCK FREQUENCY - MHz ANALOG OUTPUT FREQUENCY - MHz
TPC 12. Spurious-free dynamic range (SFDR) is generally TPC 15. Supply current variation with analog
a function of the DAC analog output frequency. Analog output frequency at 180 MHz system clock (upper
output frequencies of 1/3 the system clock rate are consid- trace) and 125 MHz system clock (lower trace)
ered worst case. Plotted below are typical worst case SFDR
numbers for various system clock rates.
Tek Stop 2.50GS/s 22 Aegs
: 2.0ns w,,,,,,,,-'''''''
: 105.2ns A
CI Rise ""'"
2.03ns l
I so vs=+5v
E "w''''"
1 il s,,,,-'''"
/ 4/ Vs = +3.3v
Chl 100mm M20.0ns Chl 1 252mV o 20 40 so so 100 120 140 160 180
D S.OOns Runs After SYSTEM CLOCK-MHZ
TPC 13. Comparator Rise Time, 15 pF Load TPC 16. Supply current variation with system
clock frequency
-8- REV. D
A0985]
1.1MH2 _ w...,-''''"
so ",,,i''''
'i' 40.1NV\
I 55 r
n ,,,,,w'''''
70.1MHz
45 ble------"'"''" 's,
..,.,.--"
5 1o 15 20
MAXIMUM DAC IOUT - mA
TPC 12 Effect of DAC maximum output current on
wideband (0 to 72 MHz) SFDR at three representa-
tive DAC output frequencies: 1.1 MHz, 40.1 MHz,
and 70.1 MHz. Vs = 5 V, 180 MHz system clock (6X
HEFCLK multiplier disabled). Currents are set using
appropriate values of RSET.
REV. D
500 ,,pr''''"
'i''.',."-'''''''''''''"
Vs = +3.3v X/r
',,,w'''C
t,,',',,''.''r" Vs = +5V
r,,,,,,,,,,,,,,,,,,-;:'-''''''-''''''''''
p-p AMPLITUDE — mV
100 //
0 20 40 60 80 100 120 140 160
INPUT FREQUENCY - MHz
TPC 18. Minimum p-p input signal needed to tog-
gle the AD9851 comparator output. Comparator
input is a sine wave compared with a fixed volt-
age threshold. Use this data in addition to sin(X)/x
rolloff and any filter losses to determine whether
adequate signal is being presented to the AD9851
comparator.
A0985]
" MIXER = =
Rx AND AD9059 DIGITAL Rx BASEBAND
RF IN LOW-PASS o DUAL 8 DEMODULATOR DIGITAL DATA our
_ s-BIT ADC _
FILTER r r
ADC CLOCK FREQUENCY T AGC
LOCKED TO "
Tx CHIP/SYMBOL/PN RATE ADC ENCODE
180MHz
on 30MHz
AD9851 32
CLOCK = /
REFERENCE GENERATOR CHIP/SYMBOL/PN
CLOCK RATE DATA
Figure 1. Chip Rate Clock GeneratorApp/ication in a Spread Spectrum Receiver
IOUT - LOW-PASS -
q FILTER
_1 s BIT PARALLEL DATA "OFF it100kn 200n 200n
MICROPROCESSOR - , f
on Itll' 0R1-BIT x 40 SERIAL DATA, fh q = "H,g'l.ilzEl2yilf'Jlf" =
MICROCONTROLLER RESET, W_CLK AND FCLUD T it100kn 2oon IMPEDANCE
L IOUTB _ K
AD9851 11oon VOLTAGE HERE = CENTER POINT o TO1V p- p
h == OF SINE WAVE (0.5V TYPICALLY)
"'0gl'lzgilbi'l'Pz USING PASSIVE AVERAGING CIRCUIT SINE WAVE
CLOCK -v CMOS
OUTPUTS
RSET OOUT OUTB
Figure 2. Basic Clock Generator Configuration
IOUT and IOUTB are equally loaded with 100 n. Two 100 k0 "gr/ir"
resistors sample each output and average the two voltages. The RF
. . . . Ci)-- PHASE
result IS filtered with the 470 pF capacrtor and applied to one COMPARATOR _ hR1 --(/io)-- glfP'ENCY
comparator input as a dc switching threshold. The filtered DAC I
sine wave output is applied to the other comparator input. The FILTER
. . l 0 d l th . AD9851 REF CLK IN
comparator will toggle with near y 50 l uty cyc e as e sme DDS
wave alternately traverses the center pomt threshold. PROGRAMMABLE
I DIVIDE-BYa-ZN FUNCTION
RF TUNING (WHERE N = 2 ITUNING WORD)
IF Fneouenex - X WORD
FREQUENCY
FILTER
REFERENCE
AD9851
TUNING
Figure 3. Frequency/Phase-Agile Local Oscillator
for Frequency Mixing/Multiplying
REFERENCE
AD9851
TUNING
_ FREQUENCY
FILTER OUT
COMPARATOR
Figure 4. Frequency/Phase-Agile Reference for PLL
Figure 5. Digitally Programmable Divide-by-N
Function in PLL
8-BIT AD9851/FSPCB
EZ-KIT LITE ADSP-21B1 DATA EVALUATION
DSP BUS BUS BOARD
/ \ DAC
ADSP-2181 -'N, INPUT/ -'N OUT
DSP OUTPUT AD9851 - FM RF
PROCESSOR "Iggy DDS OUTPUT
AD1847 é) REF
L e. R OSC
STEREO
AUDIO IN CODEC
Figure 6. High Quality, All Digital RF Frequency
Modulation
High quality, all digital RF frequency modulation generation with
the ADSP-2181 DSP and the AD9851 DDS is well documented
in Analog Devices' application note AN-543. It uses an image of
the DDS output as illustrated in Figure 8.
REV. D
A0985]
W_CLK #1
W_CLK IOUT
AD9851
W_CLK #1 -v #1
" UD FQ_UD
FQ_UD - RESETA
MICROPROCESSOR I DIFEQEECE
OR 8-BIT DATA BUS REF
MICROCONTROLLER CLOCK
RESET I
RESET V
RESET IOUT
W_CLK #2 F0 UD
-ts AD9851 - =
W_CLK #2 - #2
Figure 7. Application Showing Synchronization of
Two AD9851 DDSs to Form a Quadrature Oscillator
After a common RESET command is issued, separate W_CLKs
allow independent programming of each AD9851 40-bit input reg-
ister via the 8-bit data bus or serial input pin. A common FQ_UD
pulse is issued after programming is completed to simultaneously
engage both oscillators at their specified frequency and phase.
BANDPASS
AMPLIFIER
FILTER 240MHz
A09851 KNIT ' F.kr. i l o
x 6 -= I
d 5on 500 =-
30MHz AD9851 FINAL OUTPUT
CLOCK SPECTRUM SPECTRUM
FUNDAMENTAL E E
Lu Fc - Fo Fe + Fo Lu C + o
' IMAGE IMAGE a IMAGE
3 FCLK 3 BANDPASS
'st 'h FILTER
60 120 180 240 240
FREQUENCY - MHz FREQUENCY - MHz
Figure 8. Deriving a High Frequency Output Signal
from the AD9851 by Using an Alias or Image Signal
The differential DAC output connection in Figure 9 enables
reduction of common-mode signals and allows highly reactive
filters to be driven without a filter input termination resistor (see
above single-ended example, Figure 8). A 6 dB power advantage
is obtained at the filter output as compared with the single-ended
example, since the filter need not be doubly terminated.
DIFFERENTIAL
TRANSFORMER COUPLED
21 OUTPUT
REFERENCE
CO- AD9851 I
1:1 TRANSFORMER
i.e., MIM-CIRCUITS TI-IT
Figure 9. Differential DAC Output Connection for
Reduction of Common-Mode Signals
The AD9851 RSET input is driven by an external DAC (Figure 10)
to provide amplitude modulation or fixed, digital amplitude control
of the DAC output current. Full description of this application is
found as a Technical Note in the AD9851 data sheet under Related
Information. An Analog Devices' application note for the AD9850,
AN-423, describes another method of amplitude control using
an enhancement mode MOSFET that is equally applicable to
the AD9851.
NOTE: If the 6X REFCLK multiplier of the AD9851 is engaged,
the 125 MHz clocking source shown in Figure 10 can be reduced
by a factor of six.
+5V +5V +5V
I I DIFFERENTIAL
TRANSFORMER COUPLED
DATA -h 10-BIT DAC 21 OUTPUT
GENERATOR 1OBITS AD9731 RSET IOUT
e.g.,DG-2020 -v 500
I AD9851
5v T DDS = T
125MHz y IOUT 20 =
l""''-"''"] son
1:1 TRANSFORMER
CONTROL
COMPUTER
Figure 10. The AD9851 RSET Input Being Driven by an External DAC
REV. D
