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AD9850BRS-AD9850BRS.
CMOS, 125 MHz Complete DDS Synthesizer
REV.E
CMOS, 125 MHz
Complete DDS Synthesizer
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD9850 is a highly integrated device that uses advanced
DDS technology coupled with an internal high speed, high
performance, D/A converter and comparator, to form a com-
plete digitally programmable frequency synthesizer and clock
generator function. When referenced to an accurate clock
source, the AD9850 generates a spectrally pure, frequency/
phase-programmable, analog output sine wave. This sine wave
can be used directly as a frequency source or converted to a
square wave for agile-clock generator applications. The AD9850’s
innovative high speed DDS core provides a 32-bit frequency
tuning word, which results in an output tuning resolution of
0.0291 Hz, for a 125 MHz reference clock input. The
AD9850’s circuit architecture allows the generation of output
frequencies of up to one-half the reference clock frequency (or
62.5 MHz), and the output frequency can be digitally changed
(asynchronously) at a rate of up to 23 million new frequencies
per second. The device also provides fivebits of digitally
controlled phase modulation, which enables phase shifting of its
output in increments of 180°, 90°, 45°, 22.5°, 11.25° and any
combination thereof. The AD9850 also contains a high speed
comparator that can be configured to accept the (externally)
filtered output of the DAC to generate a low jitter square wave
output. This facilitates the device’s use as an agile clock gen-
erator function.
The frequency tuning, control, and phase modulation words are
loaded into the AD9850 via a parallel byte or serial loading
format. The parallel load format consists of five iterative loads
of an 8-bit control word (byte). The first byte controls phase
modulation, power-down enable, and loading format; bytes 2–5
comprise the 32-bit frequency tuning word. Serial loading is
accomplished via a 40-bit serial data stream on a single pin. The
AD9850 Complete-DDS uses advanced CMOS technology to
provide this breakthrough level of functionality and performance
on just 155 mW of power dissipation (+3.3 V supply).
The AD9850 is available in a space saving 28-lead SSOP, sur-
face mount package. It is specified to operate over the extended
industrial temperature range of –40°C to +85°C.
FEATURES
125 MHz Clock Rate
On-Chip High Performance DAC and High Speed
Comparator
DAC SFDR > 50 dB @ 40MHz AOUT
32-Bit Frequency Tuning Word
Simplified Control Interface:Parallel Byte or Serial
Loading Format
Phase Modulation Capability
+3.3 V or +5 V Single Supply Operation
Low Power:380 mW @ 125 MHz (+5 V)
Low Power:155 mW @ 110 MHz (+3.3 V)
Power-Down Function
Ultrasmall 28-Lead SSOP Packaging
APPLICATIONS
Frequency/Phase–Agile Sine-Wave Synthesis
Clock Recovery and Locking Circuitry for Digital
Communications
Digitally Controlled ADC Encode Generator
Agile Local Oscillator Applications
(VS = +5 V � 5% except as noted, RSET = 3.9 k�)AD9850–SPECIFICATIONS
NOTES
*Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
TIMING CHARACTERISTICS*NOTES
*Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
(VS = +5 V � 5% except as noted, RSET = 3.9 k�)
AD9850
AD9850
ABSOLUTE MAXIMUM RATINGS*Maximum Junction Temperature . . . . . . . . . . . . . . . +165°C
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS
Digital Output Continuous Current . . . . . . . . . . . . . . . 5 mA
DAC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . .–40°C to +85°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . +300°C
SSOP θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 82°C/W
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
EXPLANATION OF TEST LEVELS
Test Level–100% Production Tested.
III–Sample Tested Only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–All devices are 100% production tested at +25°C.
100% production tested at temperature extremes for
military temperature devices; guaranteed by design and
characterization testing for industrial devices.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9850 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Application Note: Users are cautioned not to apply digital input signals prior to power-up of thisdevice. Doing so may result in a latch-up condition.
ORDERING GUIDE
Table I.Lead Function Descriptions5, 24
6, 23
10, 19
11, 18
PIN CONFIGURATIONS
CH1SSpectrum10dB/REF–8.6dBm
RBW # 100Hz
START 0Hz
VBW 100HzATN # 30dBSWP 762 sec
STOP 62.5MHzFigure 1.SFDR, CLKIN = 125 MHz/fOUT = 1 MHz
CH1SSpectrum10dB/REF–10dBm
RBW # 300Hz
START 0Hz
VBW 300HzATN # 30dBSWP 182.6 sec
STOP 62.5MHzFigure 2.SFDR, CLKIN = 125 MHz/fOUT = 41 MHz
Figure 3.Typical Comparator Output Jitter, AD9850
Configured as Clock Generator w/42 MHz LP Filter
(40 MHz AOUT/125 MHz CLKIN)
AD9850–Typical Performance Characteristics
CH1SSpectrum10dB/REF–10dBm
RBW # 300Hz
START 0Hz
VBW 300HzATN # 30dBSWP 182.6 sec
STOP 62.5MHzFigure 4.SFDR, CLKIN = 125 MHz/fOUT = 20 MHz
CH1SSpectrum12dB/REF0dBm–85.401 dB
RBW # 3Hz
CENTER 4.513579MHz
VBW 3HzATN # 20dBSWP 399.5 sec
SPAN 400kHzFigure 5.SFDR, CLKIN = 20.5 MHz/fOUT = 4.5 MHz
Figure 6. Output Residual Phase Noise (5 MHz AOUT/
125 MHz CLKIN)
Figure 7.Comparator Output Rise Time
(5 V Supply/15 pF Load)
Figure 8.SFDR vs. CLKIN Frequency
(AOUT = 1/3 of CLKIN)
FREQUENCY OUT – MHz04010
SUPPLY CURRENT
mA30Figure 9.Supply Current vs. AOUT Frequency
(CLKIN = 125/110 MHz for 5 V/3.3 V Plot)
Figure 10.Comparator Output Fall Time
(5 V Supply/15 pF Load)
Figure 11.Supply Current vs. CLKIN Frequency
(AOUT = 1/3 of CLKIN)
Figure 12.SFDR vs. DAC IOUT (AOUT = 1/3 of CLKIN)
AD9850Figure 13.Basic AD9850 Clock Generator Application
with Low-Pass Filter
Figure 14.AD9850 Clock Generator Application in a
Spread-Spectrum ReceiverFrequency/Phase–Agile Local OscillatorFrequency/Phase–Agile Reference for PLLDigitally-Programmable ”Divide-by-N“ Function in PLL
Figure 15.AD9850 Complete-DDS Synthesizer in
Frequency Up-Conversion Applications
THEORY OF OPERATION AND APPLICATIONThe AD9850 uses direct digital synthesis (DDS) technology, in
the form of a numerically controlled oscillator, to generate a
frequency/phase-agile sine wave. The digital sine wave is con-
verted to analog form via an internal 10-bit high speed D/A
converter, and an onboard high speed comparator is provided to
translate the analog sine wave into a low jitter TTL/CMOS-
compatible output square wave. DDS technology is an innova-
tive circuit architecture that allows fast and precise manipulation
of its output frequency under full digital control. DDS also
enables very high resolution in the incremental selection of
output frequency; the AD9850 allows an output frequency
resolution of 0.0291 Hz with a 125 MHz reference clock ap-
plied. The AD9850’s output waveform is phase-continuous
when changed.
The basic functional block diagram and signal flow of the
AD9850 configured as a clock generator is shown in Figure 16.
The DDS circuitry is basically a digital frequency divider function
whose incremental resolution is determined by the frequency of
the reference clock divided by the 2N number of bits in the
tuning word. The phase accumulator is a variable-modulus
counter that increments the number stored in it each time it
receives a clock pulse. When the counter overflows it wraps
around, making the phase accumulator’s output contiguous.
The frequency tuning word sets the modulus of the counter that
effectively determines the size of the increment (∆ Phase) that
gets added to the value in the phase accumulator on the next
clock pulse. The larger the added increment, the faster the ac-
cumulator overflows, which results in a higher output fre-
quency. The AD9850 uses an innovative and proprietary
algorithm that mathematically converts the 14-bit truncated
value of the phase accumulator to the appropriate COS value.
This unique algorithm uses a much reduced ROM look-up table
and DSP techniques to perform this function, which contributes
to the small size and low power dissipation of the AD9850. The
relationship of the output frequency, reference clock, and tuning
word of the AD9850 is determined by the formula:
fOUT = (∆ Phase × CLKIN)/232
where:∆ Phase=value of 32-bit tuning word
CLKIN=input reference clock frequency in MHz
fOUT=frequency of the output signal in MHz
The digital sine wave output of the DDS block drives the inter-
nal high speed 10-bit D/A converter that reconstructs the sine
Figure 16.Basic DDS Block Diagram and Signal Flow of AD9850
The reference clock frequency of the AD9850 has a minimum
limitation of 1 MHz. The device has internal circuitry that
senses when the minimum clock rate threshold has been exceeded
and automatically places itself in the power-down mode. When
in this state, if the clock frequency again exceeds the threshold,
the device resumes normal operation. This shutdown mode
prevents excessive current leakage in the dynamic registers of
the device.
The D/A converter output and comparator inputs are available
as differential signals that can be flexibly configured in any
manner desired to achieve the objectives of the end-system. The
typical application of the AD9850 is with single-ended output/
input analog signals, a single low-pass filter, and generating the
comparator reference midpoint from the differential DAC out-
put as shown in Figure 13.
Programming the AD9850The AD9850 contains a 40-bit register that is used to program the
32-bit frequency control word, the 5-bit phase modulation word
and the power-down function. This register can be loaded in a
parallel or serial mode.
In the parallel load mode, the register is loaded via an 8-bit bus;
the full 40-bit word requires five iterations of the 8-bit word.
The W_CLK and FQ_UD signals are used to address and load
the registers. The rising edge of FQ_UD loads the (up to) 40-bit
control data word into the device and resets the address pointer
to the first register. Subsequent W_CLK rising edges load the
8-bit data on words [7:0] and move the pointer to the next
register. After five loads, W_CLK edges are ignored until either
a reset or an FQ_UD rising edge resets the address pointer to
the first register.
In serial load mode, subsequent rising edges of W_CLK shift
the 1-bit data on Lead 25 (D7) through the 40 bits of program-
ming information. After 40 bits are shifted through, an FQ_UD
pulse is required to update the output frequency (or phase).
The function assignments of the data and control words are
shown in Table III; the detailed timing sequence for updating
the output frequency and/or phase, resetting the device, and
powering-up/down, are shown in the timing diagrams of Figures
Note:There are specific control codes, used for factory test
purposes, that render the AD9850 temporarily inoperable. The
wave in analog form. This DAC has been optimized for dynamic
performance and low glitch energy as manifested in the low
jitter performance of the AD9850. Since the output of the
AD9850 is a sampled signal, its output spectrum follows the
Nyquist sampling theorem. Specifically, its output spectrum
contains the fundamental plus aliased signals (images) that
occur at multiples of the Reference Clock Frequency ± the
selected output frequency. A graphical representation of the
sampled spectrum, with aliased images, is shown in Figure 17.
Figure 17. Output Spectrum of a Sampled Signal
In this example, the reference clock is 100 MHz and the output
frequency is set to 20 MHz. As can be seen, the aliased images
are very prominent and of a relatively high energy level as deter-
mined by the sin(x)/x roll-off of the quantized D/A converter
output. In fact, depending on the fo/Ref Clk relationship, the
first aliased image can be on the order of –3dB below the fun-
damental. A low-pass filter is generally placed between the out-
put of the D/A converter and the input of the comparator to
further suppress the effects of aliased images. Obviously, con-
sideration must be given to the relationship of the selected
output frequency and the Reference Clock frequency to avoid
unwanted (and unexpected) output anomalies.
A good rule-of-thumb for applying the AD9850 as a clock
generator is to limit the selected output frequency to <33% of
Reference Clock frequency, thereby avoiding generating aliased
signals that fall within, or close to, the output band of interest
(generally dc-selected output frequency). This practice will ease
the complexity (and cost) of the external filter requirement for
the clock generator application.
AD9850
Table II.Factory-Reserved Internal Test Control Codes
Table III.8-Bit Parallel-Load Data/Control Word Functional AssignmentFigure 18.Parallel-Load Frequency/Phase Update Timing Sequence
