AD9849KST ,CCD Signal Processors with Integrated Timing DriverSPECIFICATIONSParameter Min Typ Max UnitTEMPERATURE RANGEOperating –20 +85 °CStorage –65 +150 °CMAX ..
AD9849KST ,CCD Signal Processors with Integrated Timing DriverSPECIFICATIONS DVDD2 = 5.25 V [AD9849], C = 20 pF, unless otherwise noted.)L Parameter Symbol Min T ..
AD9850BRS ,CMOS, 125 MHz Complete DDS SynthesizerCHARACTERISTICSClock Output Duty Cycle (Clk Gen. Config.) +25°C IV 50 ± 10 %–2–REV. EAD9850AD9850BR ..
AD9850BRS. ,CMOS, 125 MHz Complete DDS SynthesizerGENERAL DESCRIPTION combination thereof. The AD9850 also contains a high speedThe AD9850 is a highl ..
AD9850BRS-REEL , CMOS, 125 MHz Complete DDS Synthesizer
AD9851 ,180 MHz Complete DDS synthesizerCHARACTERISTICSt , t (W_CLK Min Pulsewidth High/Low) FULL IV 3.5 nsWH WLt , t (Data to W_CLK Setup ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2180-Lead PQFP, 80-Lead TQFP . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersFEATURES(ADSP-2111)25 MIPS, 40 ns Maximum Instruction Rate ADSP-2100 CORE Separate On-Chip Buses fo ..
ADSP-2101BS-100 ,ADSP-2100 Family DSP Microcomputersfeatures plus 80K bytes of on-chip RAMand, on the ADSP-2111, a host interface port.configured as 16 ..
ADSP-2101BS-66 ,ADSP-2100 Family DSP MicrocomputersADSP-2100 FamilyaDSP MicrocomputersADSP-21xxFUNCTIONAL BLOCK DIAGRAMSUMMARY16-Bit Fixed-Point DSP M ..
ADSP-2101BS-80 ,ADSP-2100 Family DSP Microcomputersapplications. TheFamily processor with host interface port,ADSP-21xx processors are all built upon ..
ADSP-2101KG-100 ,ADSP-2100 Family DSP MicrocomputersFEATURES(ADSP-2111)25 MIPS, 40 ns Maximum Instruction Rate ADSP-2100 CORE Separate On-Chip Buses fo ..
AD9848KST-AD9849KST
CCD Signal Processors with Integrated Timing Driver
REV.0
CCD Signal Processors with
Integrated Timing Driver
FUNCTIONAL BLOCK DIAGRAM
DOUTCCDIN
PBLK
VRTVRB
2dB TO 36dB
SDATASCKSL
CLPOB
10 OR 12
AD9848/AD9849
4�6dB
INTERNAL
CLOCKS
H1–H4
HD VD
CLI
CLPDM
FEATURES
AD9848: 10-Bit, 20 MHz Version
AD9849: 12-Bit, 30 MHz Version
Correlated Double Sampler (CDS)
–2 dB to +10 dB Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 20 MHz A/D Converter (AD9848)
12-Bit 30 MHz A/D Converter (AD9849)
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Driver
Precision Timing™ Core with 1 ns Resolution @ 20 MSPS
On-Chip 3 V Horizontal and RG Drivers (AD9848)
On-Chip 5 V Horizontal and RG Drivers (AD9849)
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
PRODUCT DESCRIPTIONThe AD9848 and AD9849 are highly integrated CCD signal pro-
cessors for digital still camera applications. Both include a complete
analog front end with A/D conversion, combined with a program-
mable timing driver. The Precision Timing core allows adjustment
of high speed clocks with approximately 1 ns resolution.
The AD9848 is specified at pixel rates of 20 MHz, and the
AD9849 is specified at 30 MHz. The analog front end includes
black level clamping, CDS, PxGA, VGA, and a 10- or 12-bit A/D
converter. The timing driver provides the high-speed CCD clock
drivers for RG and H1-H4. Operation is programmed using a
3-wire serial interface.
Packaged in a space-saving 48-lead LQFP, the AD9848 and
AD9849 are specified over an operating temperature range of
–20°C to +85°C.
PxGA is a registered trademark and Precision Timing is a trademark of Analog Devices, Inc.
AD9848/AD9849–TARGET SPECIFICATIONS
GENERAL SPECIFICATIONSSpecifications subject to change without notice.
AD9848/AD9849
(TMIN to TMAX, AVDD1 = DVDD3, DVDD4 = 2.7 V, DVDD1, DVDD2 = 2.7 V [AD9848], DVDD1,
DVDD2 = 5.25 V [AD9849], CL = 20 pF, unless otherwise noted.)DIGITAL SPECIFICATIONSLOGIC OUTPUTS
Specifications subject to change without notice.
AD9848/AD9849
AD9848–ANALOG SPECIFICATIONS(TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 20 MHz, unless otherwise noted.)VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
A/D CONVERTER
NOTESInput signal characteristics defined as follows:
Specifications subject to change without notice.
AD9848/AD9849
AD9849–ANALOG SPECIFICATIONS(TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 30 MHz, unless otherwise noted.)VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
A/D CONVERTER
NOTESInput signal characteristics defined as follows:
AD9848/AD9849
TIMING SPECIFICATIONS
(CL = 20 pF, fCLI = 20 MHz [AD9848] or 30 MHz [AD9849], Serial Timing in Figure 3, unless
otherwise noted.)MASTER CLOCK (CLI), AD9849
SERIAL INTERFACE
NOTESMaximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9848/AD9849 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
THERMAL CHARACTERISTICS
Thermal Resistance48-Lead LQFP Package
�JA = 92°C
AD9848/AD9849
REFT
REFB
CMLEVEL
AVSS3
AVDD3
CCDIN
(LSB) D0
NC = NO CONNECT
DVSS3
DVDD3BYP2
AVDD2
AVSS2NCDVDD4DVSS4HDVDPBLKHBLKCLPDMCLPOBSCKSDIH2
DVSS1DVDD1H4
DVSS2
DVDD2AVSS1
CLI
AVDD1
(MSB) D9
BYP1
BYP3
REFT
REFB
CMLEVEL
AVSS3
AVDD3
CCDIN
DVSS3
DVDD3
BYP2
AVDD2
AVSS2D0 (LSB)DVDD4DVSS4HDVDPBLKHBLKCLPDMCLPOBSCKSDIH2
DVSS1DVDD1H4
DVSS2
DVDD2AVSS1
CLI
AVDD1
(MSB) D11
BYP1
BYP3
D10
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
EQUIVALENT INPUT/OUTPUT CIRCUITSCircuit 1. CCDIN (Pin 29)
Circuit 2. CLI (Pin 23)
DVDD4DVDD3
DVSS4DVSS3
DATA
THREE-
STATEDOUTCircuit 3. Data Outputs D0–D11 (Pins 1–5, 8–12, 47–48)
Circuit 4. Digital Inputs (Pins 36–44)
DVDD1
DVSS1
DATA
ENABLEOUTPUTCircuit 5. H1–H4 and RG (Pins 13, 14, 17, 18, 20)
AD9848/AD9849
—Typical Linearity and Noise Performance CharacteristicsTPC 1.AD9848 Typical DNL
TPC 2.AD9848 Output Noise vs. VGA Gain Setting
TPC 3.AD9849 Typical DNL
TPC 4.AD9849 Output Noise vs. VGA Gain Setting
SYSTEM OVERVIEWFigure 1a.Typical Application (Internal Mode)
Figure 1b.Typical Application (External Mode)
Figure 1a and 1b show the typical system application diagrams
for the AD9848/AD9849. The CCD output is processed by the
AD9848/AD9849’s AFE circuitry, which consists of a CDS,
PxGA, VGA, black level clamp, and A/D converter. The digi-
tized pixel information is sent to the digital image processor
chip, where all post-processing and compression occurs. To
operate the CCD, CCD timing parameters are programmed
into the AD9848/AD9849 from the image processor, through
the 3-wire serial interface. From the system master clock, CLI,
provided by the image processor, the AD9848/AD9849 gener-
ates the high speed CCD clocks and all internal AFE clocks. All
AD9848/AD9849 clocks are synchronized with VD and HD.
Figure 1a shows the AD9848/AD9849 used in Internal mode,
in which all the horizontal pulses (CLPOB, CLPDM, PBLK,
and HBLK) are programmed and generated internally. Figure 1b
shows the AD9848/AD9849 operating in external mode, in
which the horizontal pulses are supplied externally by the
image processor.
The H-drivers for H1–H4 and RG are included in the AD9848/
AD9849, allowing these clocks to be directly connected to the
CCD. H-drive voltage of 5 V is supported in the AD9849.
Figure 2 shows the horizontal and vertical counter dimensions
for the AD9848/AD9849. All internal horizontal clocking is
programmed using these dimensions, to specify line and
pixel locations.
Figure 2.Vertical and Horizontal Counters
AD9848/AD9849
SERIAL INTERFACE TIMINGFigure 3a.Serial Write Operation
Figure 3b.Continuous Serial Write Operation
COMPLETE REGISTER LISTING
Table INotes on Register Listing:
1. All addresses and default values are expressed in Hexadecimal.
2. All registers are VD/HD updated as shown in Figure 3, except for the above-listed registers that are SL updated.
AFE Registers# Bits56
Miscellaneous/Extra# Bits26
Notes about Accessing a Double-Wide RegisterThere are many double-wide registers in the AD9848/AD9849, for example: oprmode, clpdmtog1_0, clpdmscp3, etc. These regis-
ters are configured into two consecutive 6-bit registers with the least significant six bits located in the lower of the two addresses and
the remaining most significant bits located in the higher of the two addresses. For example, the 6 LSBs of the clpdmscp3 regis-
ter, clpdmscp3[5:0], are located at address 0x81. The most significant six bits of the clpdmscp3 register, clpdmscp3[11:6], are
located at address 0x82. The following rules must be followed when accessing double-wide registers:When accessing a double-wide register, BOTH addresses must be written to.The lower of the two consecutive addresses for the double-wide register must be written to first. In the example of the clpdmscp3
register, the contents of address 0x81 must be written first followed by the contents of address 0x82. The register will be updated
after the completion of the write to register 0x82, either at the next SL rising edge or next VD/HD falling edge.A single write to the lower of the two consecutive addresses of a double-wide register that is not followed by a write to the higher
address of the registers, is not permitted. This will not update the register.A single write to the higher of the two consecutive addresses of a double-wide register that is not preceded by a write to the lower
of the two address, is not permitted. Although the write to the higher address will update the full double-wide register, the lower
six bits of the register will be written with an indeterminate value if the lower address was not written first.
AD9848/AD9849
CLPDM# Bits146
CLPOB# Bits146
AD9848/AD9849
HBLK# Bits147PBLK# Bits146
H1–H4, RG, SHP, SHD# Bits53
AD9848/AD9849
AFE REGISTER BREAKDOWN
Serial Address:
oprmode[7:0]8'h08'h00 {oprmode[5:0]}, 8'h01 {oprmode[7:6]}
ctlmode[5:0]6'h0Serial Address: 8'h06 {cltmode[5:0]}
