AD9847AKST ,10-Bit 40 MSPS CCD Signal Processor with Integrated Timing DriverSPECIFICATIONS MIN MAX CLI Parameter Min Typ Max Unit NotesCDSGain 0 dBAllowable CCD Reset Transien ..
AD9847AKSTRL ,10-Bit 40 MSPS CCD Signal Processor with Integrated Timing DriverAPPLICATIONSDigital Still CamerasPackaged in a space-saving 48-lead LQFP, the AD9847 is speci-fied ..
AD9847AKSTZ ,10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driverapplications. The AD9847 includes a com-2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) plete an ..
AD9848AKST ,10-Bit, 20 MHz CCD Signal Processor with Integrated Timing DriverSPECIFICATIONSParameter Min Typ Max UnitTEMPERATURE RANGEOperating –20 +85 °CStorage –65 +150 °CMAX ..
AD9848AKSTZ ,10-Bit, 20 MHz CCD Signal Processor with Integrated Timing Driverapplications. Both include a completeCorrelated Double Sampler (CDS) analog front end with A/D conv ..
AD9848KST ,CCD Signal Processors with Integrated Timing DriverAPPLICATIONS–20°C to +85°C.Digital Still CamerasFUNCTIONAL BLOCK DIAGRAMVRT VRBVREF46dB 2dB TO 36d ..
ADSP-2100AJG ,12.5 MIPS DSP Microprocessorspecifications differ as shown in those sections of the data sheet.
Both processors integrate co ..
ADSP-2101BP-100 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2180-Lead PQFP, 80-Lead TQFP . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersFEATURES(ADSP-2111)25 MIPS, 40 ns Maximum Instruction Rate ADSP-2100 CORE Separate On-Chip Buses fo ..
ADSP-2101BS-100 ,ADSP-2100 Family DSP Microcomputersfeatures plus 80K bytes of on-chip RAMand, on the ADSP-2111, a host interface port.configured as 16 ..
ADSP-2101BS-66 ,ADSP-2100 Family DSP MicrocomputersADSP-2100 FamilyaDSP MicrocomputersADSP-21xxFUNCTIONAL BLOCK DIAGRAMSUMMARY16-Bit Fixed-Point DSP M ..
AD9847AKST-AD9847AKSTRL-AD9847AKSTZ
10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver
REV.A
10-Bit 40 MSPS CCD Signal Processor
with Integrated Timing Driver
FUNCTIONAL BLOCK DIAGRAM
DOUTCCDIN
PBLK
VRTVRB
SDATASCKSL
CLPOB
H1–H4
HD VD
CLI
CLPDM
GENERAL DESCRIPTIONThe AD9847 is a highly integrated CCD signal processor for
digital still camera applications. The AD9847 includes a com-
plete analog front end with A/D conversion, combined with
a programmable timing driver. The Precision Timing core allows
adjustment of high speed clocks with approximately 500 ps
resolution at clock speeds of 40 MHz.
The AD9847 is specified at pixel rates of 40 MHz. The analog
front end includes black level clamping, CDS, PxGA, VGA, and a
10-bit A/D converter. The timing driver provides the high speed
CCD clock drivers for RG and H1–H4. Operation is programmed
using a 3-wire serial interface.
Packaged in a space-saving 48-lead LQFP, the AD9847 is speci-
fied over an operating temperature range of –20°C to +85°C.
FEATURES
Correlated Double Sampler (CDS)
–2 dB to +10 dB Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 40 MHz A/D Converter
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Driver
Precision Timing™ Core with 500 ps
Resolution at 40 MSPS
On-Chip 5 V Horizontal and RG Drivers
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
AD9847–SPECIFICATIONS
GENERAL SPECIFICATIONSSpecifications subject to change without notice.
LOGIC OUTPUTS
Specifications subject to change without notice.
(TMIN to TMAX, AVDD1 = DVDD3, DVDD4 = 2.7 V, DVDD1, DVDD2 = 5.25 V, CL = 20 pF, unless
otherwise noted.)DIGITAL SPECIFICATIONS
AD9847
ANALOG SPECIFICATIONS(TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 40 MHz, unless otherwise noted.)VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
A/D CONVERTER
*Input signal characteristics defined as follows:
Specifications subject to change without notice.
AD9847
TIMING SPECIFICATIONSEXTERNAL MODE CLAMPING
*Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
(CL to 29 pF, fCLI = 40 MHz, Serial Timing in Figures 3a and 3b, unless otherwise noted.)
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGSAVDD1, 2, 3 to AVSS . . . . . . . . . . . . . . . . . . .–0.3 to +3.9 V
DVDD1, 2 to DVSS . . . . . . . . . . . . . . . . . . . .–0.3 to +5.5 V
DVDD3, 4 to DVSS . . . . . . . . . . . . . . . . . . . .–0.3 to +3.9 V
Digital Outputs to DVSS3 . . . . . . . . –0.3 to DVDD3 + 0.3 V
CLPOB, CLPDM, BLK to DVSS4 . –0.3 to DVDD4 + 0.3 V
CLI to AVSS . . . . . . . . . . . . . . . . . . . –0.3 to AVDD + 0.3 V
SCK, SL, SDATA to DVSS4 . . . . . –0.3 to DVDD4 + 0.3 V
VRT, VRB to AVSS . . . . . . . . . . . . . –0.3 to AVDD + 0.3 V
BYP1–3, CCDIN to AVSS . . . . . . . . –0.3 to AVDD + 0.3 V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
Lead Temperature (10 sec) . . . . . . . . . . . . . . . . . . . . . .300°C
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9847 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
THERMAL CHARACTERISTICS
Thermal Resistance48-Lead LQFP Package . . . . . . . . . . . . . . . . . . .�JA = 92°C/W
AD9847
PIN CONFIGURATION
REFT
REFB
CMLEVEL
AVSS3
AVDD3
CCDIN
(LSB) D0
DVSS3
DVDD3
BYP2
AVDD2
AVSS2NCDVDD4DVSS4HDVDPBLKHBLKCLPDMCLPOBSCKSDIH2
DVSS1DVDD1H4
DVSS2
DVDD2AVSS1
CLI
AVDD1
(MSB) D9
BYP1
BYP3
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS8–12
Circuit 1. CCDIN (Pin 29)
Circuit 2. CLI (Pin 23)
DVDD4DVDD3
DVSS4DVSS3
DATA
THREE-
STATEDOUTCircuit 3. Data Outputs D0–D9 (Pins 1–5, 8–12)
Circuit 4. Digital Inputs (Pins 36–44)
DVDD1
DVSS1
DATA
ENABLEOUTPUTCircuit 5. H1–H4 and RG (Pins 13, 14, 17, 18, 20)
Equivalent Input/Output Circuits
Typical Performance Characteristics
AD9847
SYSTEM OVERVIEWFigures 1a and 1b show the typical system application diagrams
for the AD9847. The CCD output is processed by the AD9847’s
AFE circuitry, which consists of a CDS, PxGA, VGA, black
level clamp, and A/D converter. The digitized pixel information is
sent to the digital image processor chip, where all post-processing
and compression occurs. To operate the CCD, CCD timing param-
eters are programmed into the AD9847 from the image processor
through the 3-wire serial interface. From the system master clock,
CLI, provided by the image processor, the AD9847 generates
the high speed CCD clocks and all internal AFE clocks. All
AD9847 clocks are synchronized with VD and HD.
Figure 1a.Typical Application (Internal Mode)
Figure 1a shows the AD9847 used in internal mode, in which all
the horizontal pulses (CLPOB, CLPDM, PBLK, and HBLK)
are programmed and generated internally. Figure 1b shows the
AD9847 operating in external mode, in which the horizontal
pulses are supplied externally by the image processor.
The H-drivers for H1–H4 and RG are included in the AD9847,
allowing these clocks to be directly connected to the CCD. The
AD9847 supports H-drive voltage of 5 V.
Figure 1b.Typical Application (External Mode)
Figure 2 shows the horizontal and vertical counter dimensions for
the AD9847. All internal horizontal clocking is programmed using
these dimensions to specify line and pixel locations.
Figure 2.Vertical and Horizontal Counters
SERIAL INTERFACE TIMINGFigure 3a.Serial Write Operation
Figure 3b.Continuous Serial Write Operation
COMPLETE REGISTER LISTING
Table I.SL Updated RegistersNOTES
All addresses and default values are expressed in hexadecimal.
All registers are VD/HD updated as shown in Figure 3a, except for those that are SL updated.
AD9847
Address
AFE Registers # Bits 56
Miscellaneous/Extra # Bits 26
Accessing a Double-Wide RegisterThere are many double-wide registers in the AD9847, e.g.,
oprmode, clpdmtog1_0, and clpdmscp3, and so on. These regis-
ters are configured into two consecutive 6-bit registers with the
least significant six bits located in the lower of the two addresses
and the remaining most significant bits located in the higher of
the two addresses. For example, the six LSBs of the clpdmscp3
register, clpdmscp3[5:0], are located at address 0x81. The most
significant six bits of the clpdmscp3 register, clpdmscp3[11:6],
are located at Address 0x82. The following rules must be fol-
lowed when accessing double-wide registers:When accessing a double-wide register, BOTH addresses
must be written to.The lower of the two consecutive addresses for the double-
wide register must be written to first. In the example of the
clpdmscp3 register, the contents of Address 0x81 must be
written first, followed by the contents of Address 0x82. The
register will be updated after the completion of the write to
Register 0x82, either at the next SL rising edge or the next
VD/HD falling edge.A single write to the lower of the two consecutive addresses
of a double-wide register that is not followed by a write to the
higher address of the registers is not permitted. This will not
update the register.A single write to the higher of the two consecutive addresses of a
double-wide register that is not preceded by a write to the lower
of the two addresses is not permitted. Although the write to the
higher address will update the full double-wide register, the
lower six bits of the register will be written with an indetermi-
nate value if the lower address was not written to first.
CLPDM # Bits 146
AD9847
Address
CLPOB # Bits 146
HBLK # Bits 147
AD9847
PBLK # Bits 146
H1–H4, RG, SHP, SHD # Bits 53
