AD9846A Fast Delivery |IC PHOENIX CO.,LIMITED

AD9846A ,Complete 10-Bit 30 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotePOWER CONSUMPTION 117 mW See TP ..
AD9846AJST ,Complete 10-Bit 30 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotePOWER CONSUMPTION 117 mW See TP ..
AD9846AJSTRL ,Complete 10-Bit 30 MSPS CCD Signal ProcessorAPPLICATIONSpower-down modes.Digital Still CamerasDigital Video CamcordersThe AD9846A operates from ..
AD9846AJSTRL ,Complete 10-Bit 30 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotePOWER CONSUMPTION 117 mW See TP ..
AD9847AKST ,10-Bit 40 MSPS CCD Signal Processor with Integrated Timing DriverSPECIFICATIONS MIN MAX CLI Parameter Min Typ Max Unit NotesCDSGain 0 dBAllowable CCD Reset Transien ..
AD9847AKSTRL ,10-Bit 40 MSPS CCD Signal Processor with Integrated Timing DriverAPPLICATIONSDigital Still CamerasPackaged in a space-saving 48-lead LQFP, the AD9847 is speci-fied ..
ADSP-2100AJG ,12.5 MIPS DSP Microprocessorspecifications differ as shown in those sections of the data sheet. Both processors integrate co ..
ADSP-2101BP-100 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2180-Lead PQFP, 80-Lead TQFP . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersFEATURES(ADSP-2111)25 MIPS, 40 ns Maximum Instruction Rate ADSP-2100 CORE Separate On-Chip Buses fo ..
ADSP-2101BS-100 ,ADSP-2100 Family DSP Microcomputersfeatures plus 80K bytes of on-chip RAMand, on the ADSP-2111, a host interface port.configured as 16 ..
ADSP-2101BS-66 ,ADSP-2100 Family DSP MicrocomputersADSP-2100 FamilyaDSP MicrocomputersADSP-21xxFUNCTIONAL BLOCK DIAGRAMSUMMARY16-Bit Fixed-Point DSP M ..

AD9846A
Complete 10-Bit 30 MSPS CCD Signal Processor
REV.0
Complete 10-Bit 30 MSPS
CCD Signal Processor
FUNCTIONAL BLOCK DIAGRAM
DATACLKSHDSHPDOUT
AUX2IN
CLPDM
CCDIN
PBLK
AUX1IN
VRT
VRB
AVDD
DVDD
DVSS
AVSS
DRVDD
DRVSS
CML
SDATASCKSL
CLPOBVD
FEATURES
30 MSPS Correlated Double Sampler (CDS)
4 dB � 6 dB 6-Bit Pixel Gain Ampliﬁer (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Ampliﬁer (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit 30 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 100 mW @ 2.7 V
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
PRODUCT DESCRIPTION
The AD9846A is a complete analog signal processor for CCD
applications. It features a 30 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9846A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
Pixel Gain Ampliﬁer (PxGA), digitally controlled variable gain
ampliﬁer (VGA), black level clamp, and a 10-bit A/D con-
verter. Additional input modes are provided for processing
analog video signals.
The internal registers are programmed through a 3-wire
serial digital interface. Programmable features include gain
adjustment, black level adjustment, input conﬁguration, and
power-down modes.
The AD9846A operates from a single 3 V power supply, typi-
cally dissipates 117 mW, and is packaged in a 48-lead LQFP.
PxGA is a registered trademark of Analog Devices, Inc.
AD9846A–SPECIFICATIONS
GENERAL SPECIFICATIONS
POWER SUPPLY VOLTAGE
Speciﬁcations subject to change without notice.
DIGITAL SPECIFICATIONS
Speciﬁcations subject to change without notice.
(DRVDD = 2.7 V, CL = 20 pF unless otherwise noted.)
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.)
AD9846A
PIXEL GAIN AMPLIFIER (PxGA)
VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
SYSTEM PERFORMANCE
NOTESInput Signal Characteristics deﬁned as follows:PxGA gain fixed at 4 dB (Code 63).
Speciﬁcations subject to change without notice.
CCD-MODE SPECIFICATIONS(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 30 MHz, unless otherwise noted.)
AD9846A–SPECIFICATIONS
AUX1-MODE SPECIFICATIONS
Speciﬁcations subject to change without notice.
AUX2-MODE SPECIFICATIONS
ACTIVE CLAMP
Speciﬁcations subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.)
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.)
TIMING SPECIFICATIONS
SERIAL INTERFACE
NOTESMinimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Speciﬁcations subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9846A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
(CL = 20 pF, fSAMP = 30 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 21–24.)
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θJA = 92°C
AD9846A
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a ﬁnite width. No missing codes guaranteed to 10-bit
resolution indicates that all 1024 codes, respectively, must be
present over all operating conditions.
PEAK NONLINEARITY
Peak nonlinearity, a full signal chain speciﬁcation, refers to the
peak deviation of the output of the AD9846A from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
ﬁrst code transition. “Positive full scale” is deﬁned as a Level 1,
1/2 LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the true straight
line. The error is then expressed as a percentage of the 2 V ADC
full-scale signal. The input signal is always appropriately gained up
to ﬁll the ADC’s full-scale range.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
chain at the speciﬁed gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2N codes) when N is the bit resolution of the
ADC. For the AD9846A, 1 LSB is 2 mV.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9846A’s power supply. The PSR speciﬁcation is calculated
from the change in the data outputs for a given step change in
the supply voltage.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD9846A
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
Figure 1.Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
DVDD
DRVDD
THREE-
STATE
DATA
DOUT
Figure 3.CCDIN (Pin 30)
AD9846A
–Typical Performance Characteristics
TPC 1.Power vs. Sample Rate
TPC 2.Typical DNL Performance
TPC 3.Output Noise vs. VGA Gain
CCD-MODE AND AUX MODE TIMING
Figure 5.CCD-Mode Timing
CCD
SIGNAL
EFFECTIVE PIXELS
CLPOB
CLPDM
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKINGDUMMY PIXELSEFFECTIVE PIXELS
PBLK
NOTES:
1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
OUTPUT
DATA
Figure 6.Typical CCD-Mode Line Clamp Timing
DATACLK
OUTPUT
DATA
VIDEO
SIGNALN+1
N+2
N+8
N+9
N–10N–9N–8N–1N
tID
tODtH
N+10
AD9846A
PIXEL GAIN AMPLIFIER (PxGA) TIMING
Figure 8.PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence
Figure 9.PxGA Mode 1 (Mosaic Separate) Detailed Timing
Figure 10.PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence
Figure 12.PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence
Figure 13.PxGA Mode 3 (3-Color) Detailed Timing
Figure 14.PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence
Figure 15.PxGA Mode 4 (4-Color) Detailed Timing
AD9846A
Figure 16.PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence
Figure 17.PxGA Mode 5 (VD Selected) Detailed Timing
Figure 18.PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence
Figure 19.PxGA Mode 6 (Mosaic Repeat) Detailed Timing

Partno	Mfg	Dc	Qty	Available	Descript
AD9846A	AD	N/a	4	avai	Complete 10-Bit 30 MSPS CCD Signal Processor