AD9844AJST ,Complete 12-Bit 20 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotesPOWER CONSUMPTION 78 mW See TP ..
AD9845AJST ,Complete 12-Bit 30 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotesPOWER CONSUMPTION 140 mW See T ..
AD9845BJST ,Complete 12-Bit 30 MSPS CCD Signal Processorfeatures a 30 MHz single-channel architec-30 MSPS Correlated Double Sampler (CDS) ture designed to ..
AD9845BJSTZ ,Complete 12-Bit 30 MSPS CCD Signal ProcessorSPECIFICATIONS MIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotesPOWER CONSUMPTION 153 mW See ..
AD9846A ,Complete 10-Bit 30 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotePOWER CONSUMPTION 117 mW See TP ..
AD9846AJST ,Complete 10-Bit 30 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotePOWER CONSUMPTION 117 mW See TP ..
ADSP-2100AJG ,12.5 MIPS DSP Microprocessorspecifications differ as shown in those sections of the data sheet.
Both processors integrate co ..
ADSP-2101BP-100 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2180-Lead PQFP, 80-Lead TQFP . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersFEATURES(ADSP-2111)25 MIPS, 40 ns Maximum Instruction Rate ADSP-2100 CORE Separate On-Chip Buses fo ..
ADSP-2101BS-100 ,ADSP-2100 Family DSP Microcomputersfeatures plus 80K bytes of on-chip RAMand, on the ADSP-2111, a host interface port.configured as 16 ..
ADSP-2101BS-66 ,ADSP-2100 Family DSP MicrocomputersADSP-2100 FamilyaDSP MicrocomputersADSP-21xxFUNCTIONAL BLOCK DIAGRAMSUMMARY16-Bit Fixed-Point DSP M ..
AD9844AJST
Complete 12-Bit 20 MSPS CCD Signal Processor
REV. 0
Complete 12-Bit 20 MSPS
CCD Signal Processor
FUNCTIONAL BLOCK DIAGRAM
DATACLKSHDSHPDOUT
AUX2IN
CLPDM
CCDIN
PBLK
AUX1IN
VRT
VRB
AVDD
DVDD
DVSS
AVSS
DRVDD
DRVSS
CML
SDATASCKSL
CLPOB
FEATURES
20 MSPS Correlated Double Sampler (CDS)
4 dB � 6 dB Variable CDS Gain with 6-Bit Resolution
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
12-Bit 20 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 65 mW @ 2.7 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
PC Cameras
PRODUCT DESCRIPTIONThe AD9844A is a complete analog signal processor for CCD
applications. It features a 20 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9844A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally controlled variable gain amplifier (VGA), black level
clamp, and 12-bit A/D converter. Additional input modes are
provided for processing analog video signals.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment,
black level adjustment, input configuration, and power-down
modes.
The AD9844A operates from a single 3 V power supply, typi-
cally dissipates 78 mW, and is packaged in a 48-lead LQFP.
AD9844A–SPECIFICATIONS
GENERAL SPECIFICATIONSPOWER SUPPLY VOLTAGE
Specifications subject to change without notice.
DIGITAL SPECIFICATIONSLOGIC OUTPUTS
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
(DRVDD = 2.7 V, CL = 20 pF unless otherwise noted.)
AD9844AVARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
SYSTEM PERFORMANCE
NOTESInput Signal Characteristics defined as follows, with 4 dB CDS gain:
Specifications subject to change without notice.
CCD-MODE SPECIFICATIONS(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 20 MHz, unless otherwise noted.)
AD9844A–SPECIFICATIONS
AUX1-MODE SPECIFICATIONSSpecifications subject to change without notice.
AUX2-MODE SPECIFICATIONSACTIVE CLAMP
Specification subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
TIMING SPECIFICATIONSSERIAL INTERFACE
NOTESMinimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9844A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
(CL = 20 pF, fSAMP = 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 8–10.)
ABSOLUTE MAXIMUM RATINGSCLPOB, CLPDM, PBLK
SCK, SL, SDATA
VRT, VRB, CMLEVEL
BYP1-4, CCDIN
Junction Temperature
Lead Temperature
ORDERING GUIDE
THERMAL CHARACTERISTICS
Thermal Resistance48-Lead LQFP Package
θJA = 92°C
AD9844A
PIN CONFIGURATION
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
CCDIN
(LSB) D0
NC = NO CONNECT
BYP2
BYP1
AVDD1
AVSS
AVSS
SCKSDATASLNCSTBYNCTHREE-STATEDVSSDVDD2VRBVRTCML
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
DVSSPBLK
CLPOB
SHPSHD
CLPDM
DVSS
D10
(MSB) D11
PIN FUNCTION DESCRIPTIONS
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 12-bit
resolution indicates that all 4096 codes, respectively, must be
present over all operating conditions.
PEAK NONLINEARITYPeak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9844A from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level
1, 1/2 LSB beyond the last code transition. The deviation is mea-
sured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of the
2 V ADC full-scale signal. The input signal is always appropriately
gained up to fill the ADC’s full-scale range.
TOTAL OUTPUT NOISEThe rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2N codes) when N is the bit resolution of the
ADC. For the AD9844A, 1 LSB is 0.5 mV.
POWER SUPPLY REJECTION (PSR)The PSR is measured with a step change applied to the supply
pins. This represents a very high-frequency disturbance on the
AD9844A’s power supply. The PSR specification is calcu-
lated from the change in the data outputs for a given step
change in the supply voltage.
INTERNAL DELAY FOR SHP/SHDThe internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD9844A
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITSFigure 1.Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
DVDD
DRVDD
THREE-
STATE
DATA
DOUTFigure 3.CCDIN (Pin 30)
Figure 4.SDATA (Pin 47)
AD9844A
SAMPLE RATE – MHz
POWER DISSIPATION – mWTPC 1.Power vs. Sample Rate
TPC 2.Typical DNL Performance
–Typical Performance CharacteristicsTPC 3.Output Noise vs. VGA Gain
