AD9835BRU Fast Delivery |IC PHOENIX CO.,LIMITED

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AD9835BRU
50 MHz CMOS Complete DDS
REV.0
50 MHz CMOS
Complete DDS
FUNCTIONAL BLOCK DIAGRAM
IOUT
COMP
REFINFS ADJUSTREFOUTAGNDAVDDDGNDDVDD
MCLK
PSEL0PSEL1FSELECT
FSYNCSCLKSDATA
FEATURES
5 V Power Supply
50 MHz Speed
On-Chip COS Look-Up Table
On-Chip 10-Bit DAC
Serial Loading
Power-Down Option
200 mW Power Consumption
16-Lead TSSOP
APPLICATIONS
DDS Tuning
Digital Demodulation
GENERAL DESCRIPTION
The AD9835 is a numerically controlled oscillator employing
a phase accumulator, a COS Look-Up Table and a 10-bit
D/A converter integrated on a single CMOS chip. Modulation
capabilities are provided for phase modulation and frequency
modulation.
Clock rates up to 50 MHz are supported. Frequency accuracy
can be controlled to one part in 4 billion. Modulation is ef-
fected by loading registers through the serial interface. A
power-down bit allows the user to power down the AD9835 when
it is not in use, the power consumption being reduced to 1.75mW.
The part is available in a 16-lead TSSOP package.
AD9835–SPECIFICATIONS1(VDD = +5 V 6 5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT;
RSET = 3.9 kV; RLOAD = 300 V for IOUT, unless otherwise noted)
VOLTAGE REFERENCE
NOTESOperating temperature range is as follows: B Version: –40°C to +85°C.100% production tested.fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, fOUT = 2.11 MHz.Measured with the digital inputs static and equal to 0 V or DVDD. The AD9835 is tested with a capacitive load of 50 pF. The part can be operated with higher
capacitive loads, but the magnitude of the analog output will be attenuated. See Figure 5.
Specifications subject to change without notice.
RSET
TIMING CHARACTERISTICS(VDD = +5 V 6 5%; AGND = DGND = 0 V, unless otherwise noted)
NOTESSee Pin Description section.
Guaranteed by design but not production tested.
MCLK
Figure 2.Master Clock
Figure 3.Serial Timing
Figure 4.Control Timing
AD9835
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
AGND to DGND. . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . .–0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . .–0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . .+150°C
TSSOP qJA Thermal Impedance . . . . . . . . . . . . . . .158°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
ORDERING GUIDE
*RU = Thin Shrink Small Outline Package (TSSOP).
PIN CONFIGURATION
FS ADJUST
AGND
IOUT
AVDD
COMP
REFIN
REFOUT
DVDD
FSELECT
PSEL1
PSEL0DGND
MCLK
SCLK
SDATAFSYNC
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero scale, a point 0.5 LSB
below the first code transition (000...00 to 000...01)
and full scale, a point 0.5 LSB above the last code transition
(111...10 to 111...11). The error is expressed in LSBs.
Differential Nonlinearity
This is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC.
Signal to (Noise + Distortion)
Signal to (Noise + Distortion) is measured signal to noise at the
output of the DAC. The signal is the rms magnitude of the
fundamental. Noise is the rms sum of all the nonfundamental
signals up to half the sampling frequency (fMCLK/2) but exclud-
ing the dc component. Signal to (Noise + Distortion) is depen-
dent on the number of quantization levels used in the digitization
process; the more levels, the smaller the quantization noise.
The theoretical Signal to (Noise + Distortion) ratio for a sine
wave input is given by
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
where N is the number of bits. Thus, for an ideal 10-bit con-
verter, Signal to (Noise + Distortion) = 61.96 dB.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD9835, THD is defined as
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
Output Compliance
The output compliance refers to the maximum voltage that can
be generated at the output of the DAC to meet the specifica-
tions. When voltages greater than that specified for the output
compliance are generated, the AD9835 may not meet the speci-
fications listed in the data sheet.
Spurious Free Dynamic Range
Along with the frequency of interest, harmonics of the funda-
mental frequency and images of the MCLK frequency are
present at the output of a DDS device. The spurious free dy-
namic range (SFDR) refers to the largest spur or harmonic
present in the band of interest. The wideband SFDR gives the
magnitude of the largest harmonic or spur relative to the magni-
tude of the fundamental frequency in the bandwidth –2 MHz
about the fundamental frequency. The narrow band SFDR gives
the attenuation of the largest spur or harmonic in a bandwidth of50 kHz about the fundamental frequency.
Clock Feedthrough
There will be feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
PIN FUNCTION DESCRIPTIONS
ANALOG SIGNAL AND REFERENCEFS ADJUSTFull-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines
the magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is
as follows:
IOUTFULL-SCALE = 12.5 · VREFIN/RSET
VREFIN = 1.21 V nominal, RSET = 3.9 kW typicalREFINVoltage Reference Input. The AD9835 can be used with either the onboard reference, which is available
from pin REFOUT, or an external reference. The reference to be used is connected to the REFIN pin.
The AD9835 accepts a reference of 1.21 V nominal.REFOUTVoltage Reference Output. The AD9835 has an onboard reference of value 1.21 V nominal. The refer-
ence is made available on the REFOUT pin. This reference is used as the reference to the DAC by con-
necting REFOUT to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.IOUTCurrent Output. This is a high impedance current source. A load resistor should be connected between
IOUT and AGND.COMPCompensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling
ceramic capacitor should be connected between COMP and AVDD.
POWER SUPPLYDVDDPositive Power Supply for the Digital Section. A 0.1 mF decoupling capacitor should be connected be-
tween DVDD and DGND. DVDD can have a value of +5 V – 5%.DGNDDigital Ground.AGNDAnalog Ground.AVDDPositive Power Supply for the Analog Section. A 0.1 mF decoupling capacitor should be connected be-
tween AVDD and AGND. AVDD can have a value of +5 V – 5%.
DIGITAL INTERFACE AND CONTROL
AD9835
Table V.Commands
Table VI.Controlling the AD9835
Table I.Control Registers
Table II.Addressing the Registers
Table III.32-Bit Frequency WordBSM61sBSL61
Table IV.12-Bit Frequency Word
Table VII.Writing to the AD9835 Data Registers
Table VIII.Setting SYNC and SELSRC
Table IX.Power-Down, Resetting and Clearing the AD9835
Typical Performance Characteristics
OUTPUT FREQUENCY – MHz
SIGNAL ATTENUATION – dB8101214
–10
Figure 5.Signal Attenuation vs. Output Frequency for
Various Capacitive Load (RL = 300 W)
MCLK FREQUENCY – MHz105020
TOTAL CURRENT – mA40
Figure 7.Narrow Band SFDR vs. MCLK Frequency
AD9835
fOUT/fMCLK
SFDR (
2MHz) – dB
0.0840.1640.2440.324
Figure 9.Wide Band SFDR vs. fOUT/fMCLK for Various MCLK
Frequencies
MCLK FREQUENCY – MHz5020
SNR – dB40
Figure 10.SNR vs. MCLK Frequency
fOUT/fMCLK
SNR – dB
0.0840.1640.2440.324
Figure 11.SNR vs. fOUT/fMCLK for Various MCLK
RBW 1kHz VBW 3kHz ST 50 SEC
10dB/DIV
0Hz
START
25MHz
STOP
Figure 12.fMCLK = 50 MHz, fOUT = 2.1 MHz. Frequency
Word = ACO8312
Figure 13.fMCLK = 50 MHz, fOUT = 3.1 MHz. Frequency
Word = FDF3B64
Figure 14.fMCLK = 50 MHz, fOUT = 7.1 MHz. Frequency

Partno	Mfg	Dc	Qty	Available	Descript
AD9835BRU		N/a	1	avai	50 MHz CMOS Complete DDS