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AD9835BRU-REEL , 50 MHz Direct Digital Synthesizer, Waveform Generator
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ADSP-2100AJG ,12.5 MIPS DSP Microprocessorspecifications differ as shown in those sections of the data sheet.
Both processors integrate co ..
ADSP-2101BP-100 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
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AD9834BRU
Low Power, +2.3 V to +5.5 V, 50 MHz Complete DDS
Low Power, +2.3 V to +5.5 V, 50 MHzComplete DDS
FEATURES
+2.3 V to +5.5 V Power Supply
50 MHz Speed
Low Jitter Clock Output
Sine Output/Triangular Output
Serial Loading
Power-Down Option
Narrowband SFDR > 72 dB
20 mW Power Consumption at 3 V
20-Pin TSSOP
APPLICATIONS
Test Equipment
Slow Sweep Generator
DDS Tuning
Digital Modulation
GENERAL DESCRIPTIONThe AD9834 is a numerically controlled oscillator
employing a phase accumulator, a SIN ROM and a
10-bit D/A converter integrated on a single CMOS
chip. Clock rates up to 50 MHz are supported with a
power supply from 2.3 V to 5.5 V.
FUNCTIONAL BLOCK DIAGRAM
IOUT
COMP
REFOUT
IOUTB
SIGNBITOUTVIN
SCLKSDATAFSYNC
SLEEPPSELECTAVDD
CAP/2.5V
RESETCapability for phase modulation and frequency modula-
tion is provided. Frequency accuracy can be controlled to
one part in 0.25 billion. Modulation is effected by loading
registers through the serial interface.
The AD9834 offers the user a variety of output
waveforms. The SIN ROM can be bypassed so that a
linear up/down ramp is output from the DAC. If the SIN
ROM is not by-passed, a sinusoidal output is available.
Also, if a clock output is required, the MSB of the DAC
data can be output, or the on-chip comparator can be
used.
The digital section is driven by an on-board regulator
which steps down the applied DVDD to +2.5 V when
DVDD exceeds +2.5 V. The analog and digital sections
are independent and can be run from different power
supplies e.g. AVDD can equals 5 V with DVDD equal to
3 V, etc.
The AD9834 has a power-down pin (SLEEP) which
allows external control of a power-down mode. Sections of
the device which are not being used can be powered down to
minimise the current consumption e.g. the DAC can be
powered down when a clock output is being generated.
The part is available in a 20-pin TSSOP package.
PRELIMINARY TECHNICAL DATA
AD9834
PRELIMINARY TECHNICAL DATANOTESOperating temperature range is as follows: B Version: –40°C to +85°C; typical specifications are at 25�CGuaranteed by Design.Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current.
SPECIFICATIONS1(VDD = +2.3 V to +5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX; RSET = 6.8kΩ;Ω;Ω;Ω;Ω;
RLOAD = 200 ΩΩΩΩΩ for IOUT and IOUTB unless otherwise noted)
PRELIMINARY TECHNICAL DATA
TIMING CHARACTERISTICS1(VDD = +2.3 V to +5.5 V; AGND = DGND = 0 V, unless otherwise noted)1 Guaranteed by design, not production tested.
*See Pin Description Section.
Figure 3.Control Timing
Figure 2.Master Clock
Figure 1.Test Circuit With which Specifications are tested.
AD9834
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
AVDD to DVDD . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
AGND to DGND. . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
CAP/2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.75 V
Digital I/O Voltage to DGND–0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND–0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . .–40°C to +85°C
ORDERING GUIDE
PIN CONFIGURATIONStorage Temperature Range . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . .+150°C
TSSOP Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . .143°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . .45°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . .300°C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . .220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9834 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PRELIMINARY TECHNICAL DATA
PIN FUNCTIONS DESCRIPTIONS
ANALOG SIGNAL AND REFERENCEFS ADJUSTFull-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This
determines the magnitude of the full-scale DAC current. The relationship between RSET and
the full-scale current is as follows:
IOUTFULL-SCALE = 18 x VREFOUT/RSET
VREFOUT = 1.20 V nominal, RSET = 6.8 kΩ typicalREFOUTVoltage Reference Output. The AD9834 has an internal 1.20 V reference, which is made
available at this pin.COMPA DAC Bias Pin. This pin is used for de-coupling the DAC bias voltage.VINInput to comparator. The comparator can be used to generate a square wave from the
sinusoidal DAC output. The DAC output should be filtered appropriately before being applied
to the comparator to improve jitter. When bits OPBITEN and SIGNPIB in the control
register are set to 1, the comparator input is connected to VIN.
19,20IOUT, IOUTBCurrent Output. This is a high impedance current source. A load resistor of nominally 200 Ω
should be connected between IOUT and AGND. IOUTB should preferably be tied through an
external load resistor of 200 Ω to AGND but can be tied directly to AGND. A20pF capacitor
to AGND is also recommended to prevent clock feedthrough.
POWER SUPPLYAVDDPositive power supply for the analog section. AVDD can have a value from +2.3 V to +5.5 V.
A 0.1 µF decoupling capacitor should be connected between AVDD and AGND.DVDDPositive power supply for the digital section. DVDD can have a value from +2.3 V to +5.5 V.
A 0.1 µF decoupling capacitor should be connected between DVDD and DGND.CAP/2.5VThe digital circuitry operates from a +2.5 V power supply. This +2.5 V is generated from
DVDD using an on board regulator (when DVDD exceeds +2.7 V). The regulator requires a
decoupling capacitor of typically 100 nF which is connected from CAP/2.5V to DGND. If
DVDD is equal to or less than +2.7 V, CAP/2.5 V should be shorted to DVDD.DGNDDigital Ground.AGNDAnalog Ground.
DIGITAL INTERFACE AND CONTROLMCLKDigital Clock Input. DDS output frequencies are expressed as a binary fraction of the
frequency of MCLK. The output frequency accuracy and phase noise are determined by this
clock.FSELECTFrequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is
used in the phase accumulator. The frequency register to be used can be selected using the pin
FSELECT or the bit FSEL. When the bit FSEL is being used to select the frequency register,
this pin, FSELECT, should be tied to CMOS high or low.PSELECTPhase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added
to the phase accumulator output. The phase register to be used can be selected using the pin
PSELECT or the bit PSEL. When the phase registers are being controlled by the bit PSEL,
this pin, PSELECT, should be tied to CMOS high or low.RESETActive high digital input. RESET resets appropriate internal registers to zero which
corresponds to an analog output of midscale. RESET does not affect any of the addressable
registers.SLEEPActive high digital input. When this pin is high, the DAC is powered down. This pin has the
same function as control bit SLEEP12.SDATASerial Data Input. The 16-bit serial data word is applied to this input.SCLKSerial Clock Input. Data is clocked into the AD9834 on each falling SCLK edge.FSYNCActive Low Control Input. This is the frame synchronisation signal for the input data. When
FSYNC is taken low, the internal logic is informed that a new word is being loaded into
the device.SIGN BIT OUTLogic Output. The comparator output is available on this pin or, alternatively, the MSB from
AD9834
PRELIMINARY TECHNICAL DATA
Typical Performance CharacteristicsTPC 1. Typical Current Consumption
vs. MCLK Frequency
TPC 4. Wide Band SFDR vs. fOUT/fMCLK
for Various MCLK Frequencies
TPC 7. Wake-Up Time vs.
Temperature
TPC 2. Narrow Band SFDR vs. MCLK
Frequency
TPC 5. SNR vs. MCLK Frequency
TPC 8. VREFOUT vs. Temperature
TPC 3. Wide Band SFDR vs. MCLK
Frequency
TPC 6. SNR vs. fOUT/fMCLK for
Various MCLK Frequencies
PRELIMINARY TECHNICAL DATA
Typical Performance CharacteristicsTPC 9. fMCLK = 10 MHz; fOUT = 2.4 kHz;
Frequency Word = 000FBA9
TPC 12. fMCLK = 50 MHz; fOUT = 12 kHz;
Frequency Word = 000FBA9
TPC 15. fMCLK = 50 MHz; fOUT = 4.8
MHz; Frequency Word = 189374C
TPC 10. fMCLK = 10 MHz; fOUT = 1.43 kHz
= fMCLK/7 ;
Frequency Word = 2492492
TPC 13. fMCLK = 50 MHz; fOUT = 120 kHz;
Frequency Word = 009D496
TPC 16. fMCLK = 50 MHz;
fOUT = 7.143 MHz = fMCLK/7 ;
Frequency Word = 2492492
TPC 11. fMCLK = 10 MHz; fOUT = 3.33 kHz
= fMCLK/3 ;
Frequency Word = 5555555
TPC 14. fMCLK = 50 MHz; fOUT = 1.2
MHz; Frequency Word = 0624DD3
TPC 17. fMCLK = 50 MHz;
fOUT = 16.667 MHz = fMCLK/3 ;
Frequency Word = 5555555
AD9834
PRELIMINARY TECHNICAL DATA
TERMINOLOGY
Integral NonlinearityThis is the maximum deviation of any code from a
straight line passing through the endpoints of the transfer
function. The endpoints of the transfer function are zero
scale, a point 0.5 LSB below the first code transition
(000...00 to 000...01) and full scale, a point 0.5 LSB
above the last code transition (111...10 to 111...11).
The error is expressed in LSBs.
Differential NonlinearityThis is the difference between the measured and ideal 1
LSB change between two adjacent codes in the DAC. A
specified differential nonlinearity of ±1 LSB maximium ensures
monotonicity.
Output ComplianceThe output compliance refers to the maximum voltage
that can be generated at the output of the DAC to meet
the specifications. When voltages greater than that speci-
fied for the output compliance are generated, the AD9834
may not meet the specifications listed in the data sheet.
Spurious Free Dynamic RangeAlong with the frequency of interest, harmonics of the
fundamental frequency and images of the these frequencies
are present at the output of a DDS device. The spurious
free dynamic range (SFDR) refers to the largest spur or
harmonic which is present in the band of interest. The
wide band SFDR gives the magnitude of the largest har-
monic or spur relative to the magnitude of the fundamental
frequency in the 0 to Nyquist bandwidth. The narrow band
SFDR gives the attenuation of the largest spur or harmonic
in a bandwidth of ±200 kHz about the fundamental fre-
quency.
Total Harmonic DistortionTotal Harmonic Distortion (THD) is the ratio of the rms
sum of harmonics to the rms value of the fundameltal. For
the AD9834, THD is defined as:
THD = 20 log√(V22 + V32 + V42 + V52 + V62)/V1
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the second
through thre sixth harmonic.
Signal-to-Noise Ratio (SNR)S/N is the ratio of the rms value of the measured output
signal to the rms sum of all other spectral components
below the Nyquist frequency, excluding the first six har-
monics and dc. The value for SNR is expressed in
decibels.
Clock FeedthroughThere will be feedthrough from the MCLK input to the
analog output. Clock feedthrough refers to the magnitude
of the MCLK signal relative to the fundamental frequency
in the AD9834’s output spectrum.
THEORY OF OPERATIONSine waves are typically thought of in terms of their
magnitude form a(t) = sin (ωt). However, these are
nonlinear and not easy to generate except through piece
wise construction. On the other hand, the angular
information is linear in nature. That is, the phase angle
rotates through a fixed angle for each unit of time. The
angular rate depends on the frequency of the signal by the
traditional rate of ω = 2πf.
Figure 5.Sine Wave
Knowing that the phase of a sine wave is linear and given
a reference interval (clock period), the phase rotation for
that period can be determined.
ΔPhase = ωδt
Solving for ω
ω = ΔPhase/δt = 2πf
Solving for f and substituting the reference clock
frequency for the reference period (1/fMCLK = δt)
f = ΔPhase x fMCLK/2π
The AD9834 builds the output based on this simple
equation. A simple DDS chip can implement this
equation with three major subcircuits:
Numerical Controlled Oscillator + Phase Modulator
SIN ROM
Digital- to- Analog Convertor.
Each of these sub-circuits are discussed in the following
section.
PRELIMINARY TECHNICAL DATA
CIRCUIT DESCRIPTIONThe AD9834 is a fully integrated Direct Digital Synthesis
(DDS) chip. The chip requires one reference clock, one
low precision resistor and eight decoupling capacitors to
provide digitally created sine waves up to 25 MHz. In
addition to the generation of this RF signal, the chip is
fully capable of a broad range of simple and complex
modulation schemes. These modulation schemes are fully
implemented in the digital domain allowing accurate and
simple realization of complex modulation algorithms us-
ing DSP techniques.
The internal circuitry of the AD9834 consists of the fol-
lowing main sections: a Numerical Controlled Oscillator
(NCO), Frequency and Phase Modulators, SIN ROM, a
Digital-to-Analog Converter, a Comparator and a
Regulator.
Numerical Controlled Oscillator + Phase ModulatorThis consists of two frequency select registers, a phase
accumulator, two phase offset registers and a phase offset
adder. The main component of the NCO is a 28-bit phase
accumulator which assembles the phase component of the
output signal. Continuous time signals have a phase range
of 0 to 2�. Outside this range of numbers, the sinusoid
functions repeat themselves in a periodic manner. The
digital implementation is no different. The accumulator
simply scales the range of phase numbers into a multibit
digital word. The phase accumulator in the AD9834 is
implemented with 28 bits. Therefore, in the AD9834, 2�
= 228. Likewise, the ΔPhase term is scaled into this range
of numbers 0 < ΔPhase < 228 – 1. Making these substitu-
tions into the equation above
f = ΔPhase x fMCLK/228
where 0 < ΔPhase < 228 - 1.
The input to the phase accumulator (i.e., the phase step)
can be selected either from the FREQ0 Register or
FREQ1 Register and this is controlled by the FSELECT
pin or the FSEL bit. NCOs inherently generate
continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies.
Following the NCO, a phase offset can be added to
perform phase modulation using the 12-bit Phase
Registers. The contents of one of these phase registers is
added to the most significant bits of the NCO. The
AD9834 has two Phase registers, the resolution of these
registers being 2π/4096.
SIN ROMTo make the output from the NCO useful, it must be
converted from phase information into a sinusoidal value.
Since phase information maps directly into amplitude, the
SIN ROM uses the digital phase information as an ad-
dress to a look-up table, and converts the phase
information into amplitude. Although the NCO contains a
28-bit phase accumulator, the output of the NCO is trun-
cated to 12 bits. Using the full resolution of the phase
accumulator is impractical and unnecessary as this would
DAC. This requires the SIN ROM to have two bits of
phase resolution more than the 10-bit DAC.
The SIN ROM is enabled using bits MODE and
OPBITEN in the control register. This is explained fur-
ther in Table 14.
Digital-to-Analog ConverterThe AD9834 includes a high impedance current source
10-bit DAC, capable of driving a wide range of loads.
Full-scale output current can be adjusted, for optimum
power and external load requirements, through the use of
a single external resistor (RSET).
The DAC can be configured for either single-ended or
differential operation. IOUT and IOUTB can be con-
nected through equal external resistors to AGND to
develop complementary output voltages. The load resis-
tors can be any value required, as long as the full-scale
voltage developed across it does not exceed the voltage
compliance range. Since full-scale current is controlled by
RSET, adjustments to RSET can balance changes made to the
load resistors.
ComparatorThe AD9834 can be used to generate synthesised digital
clock signals. This can be done by using the on-board
self-biasing comparator, which converts the DAC's sinu-
soidal signal to a square wave. The output from the DAC
may be filtered externally before being applied to the
comparator input. The comparator reference voltage is the
time-average of the signal applied to VIN. The comparator
can accept a signal of 1 Vpp. As the comparator's input is
ac-coupled, to operate correctly as a zero crossing
dectector, it requires a minimum input frequency of 3
MHz. The comparator's output will be a square wave with
an amplitude from 0 V to DVDD.
To enable the comparator, bits SIGNPIB and OPBITEN
in the control resister are set to '1'. This is explained fur-
ther in Table 13.
RegulatorThe AD9834 has separate power supplies for the analog
and digital section. AVDD provides the power supply
required for the analog section, while DVDD provides the
power supply for the digital section. Both of these supplies
can have a value of +2.3V to +5.5V, and are independant
of each other e.g. the analog section can be operated at 5V
and the digital section can be operated at 3V or vice versa.
The internal digital section of the AD9834 is operated at
2.5 V. An on-board regulator steps down the voltage ap-
plied at DVDD to 2.5 V. The digital inteface (serial port)
of the AD9834 is also operated from DVDD. These digi-
tal signals are level shifted within the AD9834 to make
them 2.5V compatible.
When the applied voltage at the DVDD pin of the
AD9834 is equal to or less than 2.5V, the pins CAP/2.5V
and DVDD should be tied together, thus by-passing the
on-board regulator.
AD9834
PRELIMINARY TECHNICAL DATA
FUNCTIONAL DESCRIPTION
Serial InterfaceThe AD9834 has a standard 3-wire serial interface, which
is compatible with SPI, QSPI, MICROWIRE and DSP
interface standards.
Data is loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK. The timing dia-
gram for this operation is given in Figure 4.
The FSYNC input is a level triggered input that acts as a
frame synchronisation and chip enable. Data can only be
transferred into the device when FSYNC is low. To start
the serial data transfer, FSYNC should be taken low, ob-
serving the minimum FSYNC to SCLK falling edge setup
time, t7. After FSYNC goes low, serial data will be shifted
into the device's input shift register on the falling edges of
SCLK for 16 clock pulses. FSYNC may be taken high
after the sixteenth falling edge of SCLK, observing the
minimum SCLK falling edge to FSYNC rising edge time,
t8. Alternatively, FSYNC can be kept low for a multiple of
16 SCLK pulses, and then brought high at the end of the
data transfer. In this way, a continuous stream of 16 bit
words can be loaded while FSYNC is held low, FSYNC
only going high after the 16th SCLK falling edge of the
last word loaded.
The SCLK can be continuous or, alternatively, the SCLK
can idle high or low between write operations.
Powering up the AD9834The flow chart in Figure 7 shows the operating routine for
the AD9834. When the AD9834 is powered up, the part
should be reset. This will reset appropriate internal regis-
ters to zero to provide an analog output of midscale. To
avoid spurious DAC outputs while the AD9834 is being
initialized, the RESET bit/pin should be set to 1 until the
part is ready to begin generating an output. RESET does
not reset the phase, frequency or control registers. These
registers will contain invalid data and, therefore, should be
set to a known value by the user. The RESET bit/pin
should then be set to 0 to begin generating an output. A
signal will appear at the DAC output 7 MCLK cycles after
RESET is set to 0.
LatencyAssociated with each operation is a latency. When the pins
FSELECT and PSELECT change value there is a pipe-
line delay before control is transfered to the selected
register. When the timing specifications t11 and t11A are
met (see figure 3) FSELECT and PSELECT have laten-
cies of 7 MCLK cycles. When the timing specifications
t11 and t11A are not met, the latency is increased by one
MCLK cycle.
Similarly there is a latency associated with each asynchro-
nous write operation. If a selected frequency/phase register
is loaded with a new word there is a delay of 7 to 8 MCLK
cycles before the analog output will change. (There is an
uncertainty of one MCLK cycle as it depends on the posi-
tion of the MCLK rising edge when the data is loaded into
the destination register.)
The negative transition of the RESET and SLEEP func-
tions are sampled on the internal falling edge of MCLK,
therefore also have a latency associated with them.
The Control RegisterThe AD9834 contains a 16-bit control register which sets
up the AD9834 as the user wishes to operate it. All control
bits, except MODE, are sampled on the internal negative
edge of MCLK.
Table 2, on the following page, describes the individual
bits of the control register. The different functions and the
various output options from the AD9834 are described in
more detail in the section following Table 2.
To inform the AD9834 that you wish to alter the contents
of the Control register, D15 and D14 must be set to '0' as
shown below.
Table 1. Control Register
MODE
SLEEP12
SLEEP1
AD9834
IOUT
IOUTB
VIN
SIGNBITOUT
